clk: ux500: move AB8500 sysclk over to PRCMU clk driver

The AB8500 sysclk is just another PRCMU-controlled clock, there
is no reason why it should be in the ABx500-controlled part of
the clock implementation. Doing this and the corresponding device
tree changes makes USB work on the Ux500 again.

Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c
index a07c31e6f26d2f926add57cc63520dceef610c3d..0467fcae3b0efef0bf8c1ee6266047930684691a 100644 (file)
--- a/drivers/clk/ux500/abx500-clk.c
+++ b/drivers/clk/ux500/abx500-clk.c
@@ -15,7 +15,6 @@
 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/mfd/dbx500-prcmu.h>
 #include "clk.h"
 
 /* Clock definitions for ab8500 */
@@ -39,13 +38,6 @@ static int ab8500_reg_clks(struct device *dev)
        if (ret)
                return ret;
 
-       /* ab8500_sysclk */
-       clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
-       clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
-       clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
-       clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
-       clk_register_clkdev(clk, "sysclk", "shrm_bus");
-
        /* ab8500_sysclk2 */
        clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
                AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,

diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index e960d686d9db81ebf282cc37e09d2fde5b0317c2..d5888591e1a9afdf6c4dc5a9ea42c515548c90b5 100644 (file)
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -206,6 +206,9 @@ static void u8500_clk_init(struct device_node *np)
        clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
        prcmu_clk[PRCMU_TIMCLK] = clk;
 
+       clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
+       prcmu_clk[PRCMU_SYSCLK] = clk;
+
        clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
                                        100000000, CLK_SET_RATE_GATE);
        prcmu_clk[PRCMU_SDMMCCLK] = clk;