drm/amd/powerplay: partial revert commit 01b0e7fb1.

when uvd is idle, we gate uvd clock.
and uvd is busy, we ungate uvd clock.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index cf2ee93d8475270421b451d4355a9f8a6ff74aa4..a1fc4fcac1e09a53f838e56ae2ca74d33dd034f0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -149,7 +149,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
        if (bgate) {
                cgs_set_clockgating_state(hwmgr->device,
                                AMD_IP_BLOCK_TYPE_UVD,
-                               AMD_CG_STATE_UNGATE);
+                               AMD_CG_STATE_GATE);
                cgs_set_powergating_state(hwmgr->device,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_GATE);
@@ -162,7 +162,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                                                AMD_CG_STATE_UNGATE);
                cgs_set_clockgating_state(hwmgr->device,
                                AMD_IP_BLOCK_TYPE_UVD,
-                               AMD_CG_STATE_GATE);
+                               AMD_CG_STATE_UNGATE);
                smu7_update_uvd_dpm(hwmgr, false);
        }