drm/amdgpu: pad gfx and compute rings to 256 dw
authorChristian König <christian.koenig@amd.com>
Wed, 5 Oct 2016 10:38:21 +0000 (12:38 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Oct 2016 18:38:34 +0000 (14:38 -0400)
The same as on windows to avoid further problems with CE/DE
command submission overlaps.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index 40abb6b81c095a677dd6f6992369d5db8f2ec4aa..e3be5bd7ec50e9513e9041ac05b7b4d85504bd1b 100644 (file)
@@ -2896,7 +2896,7 @@ static int gfx_v6_0_sw_init(void *handle)
                ring->ring_obj = NULL;
                sprintf(ring->name, "gfx");
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    0x80000000, 0xf,
+                                    0x80000000, 0xff,
                                     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
                                     AMDGPU_RING_TYPE_GFX);
                if (r)
@@ -2920,7 +2920,7 @@ static int gfx_v6_0_sw_init(void *handle)
                sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
                irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    0x80000000, 0xf,
+                                    0x80000000, 0xff,
                                     &adev->gfx.eop_irq, irq_type,
                                     AMDGPU_RING_TYPE_COMPUTE);
                if (r)
index b2cf1290c1cfbbf4274b58ff2f559ca54e1affb4..e239e1db3ab01902b25e074aa29348742f69315f 100644 (file)
@@ -4646,7 +4646,7 @@ static int gfx_v7_0_sw_init(void *handle)
                ring->ring_obj = NULL;
                sprintf(ring->name, "gfx");
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
                                     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
                                     AMDGPU_RING_TYPE_GFX);
                if (r)
@@ -4673,7 +4673,7 @@ static int gfx_v7_0_sw_init(void *handle)
                irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
                /* type-2 packets are deprecated on MEC, use type-3 instead */
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
                                     &adev->gfx.eop_irq, irq_type,
                                     AMDGPU_RING_TYPE_COMPUTE);
                if (r)
index 8dc8f576d2c7baffc35699c920dcf26e985d7f12..8efcc8d2ad605d6c992463fed394a4fdc3d12ea1 100644 (file)
@@ -2035,7 +2035,7 @@ static int gfx_v8_0_sw_init(void *handle)
                }
 
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
                                     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
                                     AMDGPU_RING_TYPE_GFX);
                if (r)
@@ -2062,7 +2062,7 @@ static int gfx_v8_0_sw_init(void *handle)
                irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
                /* type-2 packets are deprecated on MEC, use type-3 instead */
                r = amdgpu_ring_init(adev, ring, 1024,
-                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+                                    PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
                                     &adev->gfx.eop_irq, irq_type,
                                     AMDGPU_RING_TYPE_COMPUTE);
                if (r)