ARM: msm: Don't touch GIC registers outside of GIC code

The MSM code has some antiquated register writes to set up the
PPIs to be edge triggered. Now that we have the percpu irq
interface we don't need this code so let's remove it and update
the percpu irq user (msm_timer) to set the irq type.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>

diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 65f4a1daa2e5f6d5250bee88ceba4d3590a0f39e..bdafe791fd0b605496bfe33238e5411e1c7ff8e3 100644 (file)
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -55,24 +55,11 @@ static void __init msm8960_map_io(void)
 
 static void __init msm8960_init_irq(void)
 {
-       unsigned int i;
        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
                 (void *)MSM_QGIC_CPU_BASE);
 
-       /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-       writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
        if (machine_is_msm8960_rumi3())
                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-       /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-        * as they are configured as level, which does not play nice with
-        * handle_percpu_irq.
-        */
-       for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-               if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                       irq_set_handler(i, handle_percpu_irq);
-       }
 }
 
 static struct platform_device *sim_devices[] __initdata = {

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 13ca9bb5a4d66108434203601409a17a989625c5..9df5c8357495e40c469056e002ad3b43e15b3f16 100644 (file)
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -67,9 +67,6 @@ static void __init msm8x60_init_irq(void)
                of_irq_init(msm_dt_gic_match);
 #endif
 
-       /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-       writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
        /* RUMI does not adhere to GIC spec by enabling STIs by default.
         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
         */

diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index db0117ec55f4ad32a10d154d1eb2c41654a73bac..b119f9947dfe6da2363776ebe90eb64f18bf82be 100644 (file)
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,17 +22,12 @@
 #include <asm/mach-types.h>
 #include <asm/smp_plat.h>
 
-#include <mach/msm_iomap.h>
-
 #include "scm-boot.h"
 
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 
-/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
-
 extern void msm_secondary_startup(void);
 /*
  * control for which core is the next to come out of the secondary
@@ -50,9 +45,6 @@ static inline int get_core_count(void)
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-       /* Configure edge-triggered PPIs */
-       writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
        /*
         * if any interrupts are already enabled for the primary
         * core (e.g. timer irq), then they will not have been enabled

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 812808254936575efb06902de9b4bbe7d4941084..36bbc60b699f01725825486dcdb909a5ffce73df 100644 (file)
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 
        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
        clockevents_register_device(evt);
-       enable_percpu_irq(evt->irq, 0);
+       enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
        return 0;
 }
 
@@ -219,7 +219,7 @@ static void __init msm_timer_init(void)
                res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                         ce->name, msm_evt.percpu_evt);
                if (!res) {
-                       enable_percpu_irq(ce->irq, 0);
+                       enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 #ifdef CONFIG_LOCAL_TIMERS
                        local_timer_register(&msm_local_timer_ops);
 #endif