drm/i915/skl: Disable coarse power gating up until F0

There is conflicting info between E0 and F0 steppings
for this workarounds. Trust more authoritative source and
be conservative and extend also for F0.

This prevents numerous (>50) gpu hangs with SKL GT4e
during piglit run.

References: HSD: gen9lp/2134184
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-1-git-send-email-mika.kuoppala@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee05ce8bf79a404607e9fbb1924e7ac3f51f8eb3..7096c0668fbb74901001c5b88ba7eafc99b217d3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
         */
        if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
            ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
-            IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
+            IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
                I915_WRITE(GEN9_PG_ENABLE, 0);
        else
                I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?