drm/i915: Assorted INTEL_INFO(dev) cleanups

A bunch of source files with just a few instances of the
incorrect INTEL_INFO use.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 3784940a4e7afe0c13e47990e97e50e0df663939..d81232b79f00772c4a6de7d23739bfeb3ede4759 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -95,8 +95,7 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
 static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 {
        struct drm_crtc *crtc = crtc_state->crtc;
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int i, pipe = intel_crtc->pipe;
        uint16_t coeffs[9] = { 0, };
@@ -180,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
        I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
        I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 
-       if (INTEL_INFO(dev)->gen > 6) {
+       if (INTEL_GEN(dev_priv) > 6) {
                uint16_t postoff = 0;
 
                if (intel_crtc_state->limited_color_range)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index fed61958ffd48bf7e1192040de989d61767b2ebf..86ecec5601d42dd59f937f7c8c2203b3aeb105bc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -147,14 +147,13 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
                               struct intel_crtc_state *crtc_state,
                               int mode)
 {
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_crt *crt = intel_encoder_to_crt(encoder);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
        u32 adpa;
 
-       if (INTEL_INFO(dev)->gen >= 5)
+       if (INTEL_GEN(dev_priv) >= 5)
                adpa = ADPA_HOTPLUG_BITS;
        else
                adpa = 0;
@@ -673,8 +672,7 @@ static const struct dmi_system_id intel_spurious_crt_detect[] = {
 static enum drm_connector_status
 intel_crt_detect(struct drm_connector *connector, bool force)
 {
-       struct drm_device *dev = connector->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(connector->dev);
        struct intel_crt *crt = intel_attached_crt(connector);
        struct intel_encoder *intel_encoder = &crt->base;
        enum intel_display_power_domain power_domain;
@@ -731,7 +729,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
        if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
                if (intel_crt_detect_ddc(connector))
                        status = connector_status_connected;
-               else if (INTEL_INFO(dev)->gen < 4)
+               else if (INTEL_GEN(dev_priv) < 4)
                        status = intel_crt_load_detect(crt,
                                to_intel_crtc(connector->state->crtc)->pipe);
                else if (i915.load_detect_test)
@@ -793,11 +791,10 @@ static int intel_crt_set_property(struct drm_connector *connector,
 
 void intel_crt_reset(struct drm_encoder *encoder)
 {
-       struct drm_device *dev = encoder->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->dev);
        struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 
-       if (INTEL_INFO(dev)->gen >= 5) {
+       if (INTEL_GEN(dev_priv) >= 5) {
                u32 adpa;
 
                adpa = I915_READ(crt->adpa_reg);

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e16a639fa004dfebfe94ef5e0bc55bc62009..10ec9d4b7d455566464bdbeaa15e1026fd713f1b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1753,8 +1753,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
                                   struct drm_connector_state *old_conn_state)
 {
        struct drm_encoder *encoder = &intel_encoder->base;
-       struct drm_device *dev = encoder->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->dev);
        enum port port = intel_ddi_get_encoder_port(intel_encoder);
        int type = intel_encoder->type;
        uint32_t val;
@@ -1787,7 +1786,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
        if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
                                        DPLL_CTRL2_DDI_CLK_OFF(port)));
-       else if (INTEL_INFO(dev)->gen < 9)
+       else if (INTEL_GEN(dev_priv) < 9)
                I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 
        if (type == INTEL_OUTPUT_HDMI) {
@@ -1837,8 +1836,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
        struct drm_encoder *encoder = &intel_encoder->base;
        struct drm_crtc *crtc = encoder->crtc;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct drm_device *dev = encoder->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->dev);
        enum port port = intel_ddi_get_encoder_port(intel_encoder);
        int type = intel_encoder->type;
 
@@ -1856,7 +1854,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
        } else if (type == INTEL_OUTPUT_EDP) {
                struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-               if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
+               if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
                        intel_dp_stop_link_train(intel_dp);
 
                intel_edp_backlight_on(intel_dp);

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 21853a17b6d926ed396f805adf136d7921b2e412..58a756f2f2244d054f80baba8ef9afb6892fc21e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -188,13 +188,12 @@ out:
 
 void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
-       struct drm_device *dev = crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_shared_dpll *pll = crtc->config->shared_dpll;
        unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
 
        /* PCH only available on ILK+ */
-       if (INTEL_INFO(dev)->gen < 5)
+       if (INTEL_GEN(dev_priv) < 5)
                return;
 
        if (pll == NULL)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index de7b3e6ed47708612eeac16b19dfb933f5516029..d12ef0047d491b917a48ccbf70aa1eb89396f5c3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -122,8 +122,7 @@ out:
 static void intel_lvds_get_config(struct intel_encoder *encoder,
                                  struct intel_crtc_state *pipe_config)
 {
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
        u32 tmp, flags = 0;
 
@@ -139,12 +138,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
        pipe_config->base.adjusted_mode.flags |= flags;
 
-       if (INTEL_INFO(dev)->gen < 5)
+       if (INTEL_GEN(dev_priv) < 5)
                pipe_config->gmch_pfit.lvds_border_bits =
                        tmp & LVDS_BORDER_ENABLE;
 
        /* gen2/3 store dither state in pfit control, needs to match */
-       if (INTEL_INFO(dev)->gen < 4) {
+       if (INTEL_GEN(dev_priv) < 4) {
                tmp = I915_READ(PFIT_CONTROL);
 
                pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index be4b4d546fd9f258171986c815fa3257fdb17338..374a733864d4bd097958e47227967c79ceef55f4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -304,7 +304,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                              struct intel_crtc_state *pipe_config,
                              int fitting_mode)
 {
-       struct drm_device *dev = intel_crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
        u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 
@@ -325,7 +325,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                break;
        case DRM_MODE_SCALE_ASPECT:
                /* Scale but preserve the aspect ratio */
-               if (INTEL_INFO(dev)->gen >= 4)
+               if (INTEL_GEN(dev_priv) >= 4)
                        i965_scale_aspect(pipe_config, &pfit_control);
                else
                        i9xx_scale_aspect(pipe_config, &pfit_control,
@@ -339,7 +339,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
                    pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
                        pfit_control |= PFIT_ENABLE;
-                       if (INTEL_INFO(dev)->gen >= 4)
+                       if (INTEL_GEN(dev_priv) >= 4)
                                pfit_control |= PFIT_SCALING_AUTO;
                        else
                                pfit_control |= (VERT_AUTO_SCALE |
@@ -355,7 +355,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 
        /* 965+ wants fuzzy fitting */
        /* FIXME: handle multiple panels by failing gracefully */
-       if (INTEL_INFO(dev)->gen >= 4)
+       if (INTEL_GEN(dev_priv) >= 4)
                pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
                                 PFIT_FILTER_FUZZY);
 
@@ -366,7 +366,7 @@ out:
        }
 
        /* Make sure pre-965 set dither correctly for 18bpp panels. */
-       if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
+       if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
                pfit_control |= PANEL_8TO6_DITHER_ENABLE;
 
        pipe_config->gmch_pfit.control = pfit_control;

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 41e6e920d9d79c953e73087aa68c9b24c236d2b4..7b488e2793d98457c2ae09dd988d49707288acf5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -472,7 +472,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
                /* Enable PSR on the panel */
                hsw_psr_enable_sink(intel_dp);
 
-               if (INTEL_INFO(dev)->gen >= 9)
+               if (INTEL_GEN(dev_priv) >= 9)
                        intel_psr_activate(intel_dp);
        } else {
                vlv_psr_setup_vsc(intel_dp);
@@ -498,7 +498,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
         *     - On HSW/BDW we get a recoverable frozen screen until next
         *       exit-activate sequence.
         */
-       if (INTEL_INFO(dev)->gen < 9)
+       if (INTEL_GEN(dev_priv) < 9)
                schedule_delayed_work(&dev_priv->psr.work,
                                      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 3990c805a5b5a639c44cb29598539d58d1e13c73..27808e91cb5a6ca55c730545b58790953fb2b95e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1195,8 +1195,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
                                  struct intel_crtc_state *crtc_state,
                                  struct drm_connector_state *conn_state)
 {
-       struct drm_device *dev = intel_encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
        struct drm_display_mode *mode = &crtc_state->base.mode;
@@ -1269,13 +1268,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
                return;
 
        /* Set the SDVO control regs. */
-       if (INTEL_INFO(dev)->gen >= 4) {
+       if (INTEL_GEN(dev_priv) >= 4) {
                /* The real mode polarity is set by the SDVO commands, using
                 * struct intel_sdvo_dtd. */
                sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
                if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
                        sdvox |= HDMI_COLOR_RANGE_16_235;
-               if (INTEL_INFO(dev)->gen < 5)
+               if (INTEL_GEN(dev_priv) < 5)
                        sdvox |= SDVO_BORDER_ENABLE;
        } else {
                sdvox = I915_READ(intel_sdvo->sdvo_reg);
@@ -1294,7 +1293,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
        if (intel_sdvo->has_hdmi_audio)
                sdvox |= SDVO_AUDIO_ENABLE;
 
-       if (INTEL_INFO(dev)->gen >= 4) {
+       if (INTEL_GEN(dev_priv) >= 4) {
                /* done in crtc_mode_set as the dpll_md reg must be written early */
        } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
                   IS_G33(dev_priv)) {
@@ -1305,7 +1304,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
        }
 
        if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
-           INTEL_INFO(dev)->gen < 5)
+           INTEL_GEN(dev_priv) < 5)
                sdvox |= SDVO_STALL_SELECT;
        intel_sdvo_write_sdvox(intel_sdvo, sdvox);
 }

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 9212f00d5752b64ac17145cd222ec20dbe00f573..78cdfc6833d6e4dff50ec426420672439fa055b4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1029,8 +1029,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
                                struct intel_crtc_state *pipe_config,
                                struct drm_connector_state *conn_state)
 {
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
        struct intel_tv *intel_tv = enc_to_tv(encoder);
        const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
@@ -1116,7 +1115,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
 
        set_color_conversion(dev_priv, color_conversion);
 
-       if (INTEL_INFO(dev)->gen >= 4)
+       if (INTEL_GEN(dev_priv) >= 4)
                I915_WRITE(TV_CLR_KNOBS, 0x00404000);
        else
                I915_WRITE(TV_CLR_KNOBS, 0x00606000);

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index a0944dde7c41c9617ca6f3b433eba754b1db0995..868a195954a86eaae51c05822257a2ad67045c09 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1483,7 +1483,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
 
        for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
                if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
-                   (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
+                   (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
                        break;
        }