clk: mmp: Fix the wrong factor table for uart PLL

The suggested value in the mmp2 manual is wrong.
There are only 13 bits for numerator, but some suggested
value has 14 bits.
Fix the factor tabled and remove the unused items.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index 5c90a4230fa3d3f2718c7ed6452c32c51df70b24..09d2832fbd7821a56e53fe8dc22ab16548fa3f1c 100644 (file)
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -63,10 +63,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
 };
 
 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
-       {.num = 14634, .den = 2165},    /*14.745MHZ */
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
        {.num = 3521, .den = 689},      /*19.23MHZ */
-       {.num = 9679, .den = 5728},     /*58.9824MHZ */
-       {.num = 15850, .den = 9451},    /*59.429MHZ */
 };
 
 static const char *uart_parent[] = {"uart_pll", "vctcxo"};

diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 2cbc2b43ae527265c89f8a9deabfbf26a2f2bd28..b7e0b89b2e3f82ac8e2959e46e80d204ee014d1b 100644 (file)
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -98,10 +98,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = {
 };
 
 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
-       {.num = 14634, .den = 2165},    /*14.745MHZ */
+       {.num = 8125, .den = 1536},     /*14.745MHZ */
        {.num = 3521, .den = 689},      /*19.23MHZ */
-       {.num = 9679, .den = 5728},     /*58.9824MHZ */
-       {.num = 15850, .den = 9451},    /*59.429MHZ */
 };
 
 static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)