drm/radeon: allow PACKET3_PFP_SYNC_ME on evergreen
authorEdmondo Tommasina <edmondo.tommasina@gmail.com>
Mon, 30 May 2016 23:11:14 +0000 (01:11 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 7 Jul 2016 18:50:59 +0000 (14:50 -0400)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/evergreen_cs.c
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/radeon_drv.c

index 0d3f744de35aa4c7fb5a8ad3389d896a719b2a60..d960d3915408963569e6acbfe6612b70af631209 100644 (file)
@@ -2209,6 +2209,12 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                }
                break;
        }
+       case PACKET3_PFP_SYNC_ME:
+               if (pkt->count) {
+                       DRM_ERROR("bad PFP_SYNC_ME\n");
+                       return -EINVAL;
+               }
+               break;
        case PACKET3_SURFACE_SYNC:
                if (pkt->count != 3) {
                        DRM_ERROR("bad SURFACE_SYNC\n");
@@ -3381,6 +3387,7 @@ static int evergreen_vm_packet3_check(struct radeon_device *rdev,
        case PACKET3_MPEG_INDEX:
        case PACKET3_WAIT_REG_MEM:
        case PACKET3_MEM_WRITE:
+       case PACKET3_PFP_SYNC_ME:
        case PACKET3_SURFACE_SYNC:
        case PACKET3_EVENT_WRITE:
        case PACKET3_EVENT_WRITE_EOP:
index 0b174e14e9a688a84da9fbf575253fb72a868a99..c8e3d394cde70033798b696305da88c38a9c0c9c 100644 (file)
                 */
 #              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
 #              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
+#define        PACKET3_PFP_SYNC_ME                             0x42
 #define        PACKET3_SURFACE_SYNC                            0x43
 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
index a455dc7d4aa1a146ab3a59e4bbd6f0b9e2244159..e028ca385a4653d0bad763a45697bd98ee6feb3c 100644 (file)
  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
  *   2.44.0 - SET_APPEND_CNT packet3 support
  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
+ *   2.46.0 - Add PFP_SYNC_ME support on evergreen
  */
 #define KMS_DRIVER_MAJOR       2
-#define KMS_DRIVER_MINOR       45
+#define KMS_DRIVER_MINOR       46
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);