drm/dp: Add drm_dp_psr_setup_time()
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 18 May 2016 08:57:29 +0000 (11:57 +0300)
committerDave Airlie <airlied@redhat.com>
Tue, 2 Aug 2016 21:06:28 +0000 (07:06 +1000)
Add a small helper to parse the PSR setup time from the DPCD PSR
capabilities and return the value in microseconds.

v2: Don't waste so many bytes on the psr_setup_time_us[] table

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/drm_dp_helper.c
include/drm/drm_dp_helper.h

index 8f11b8741e425720b9ad25c622da7fa5b9bfbf48..eae5ef963cb790d261a5093aa8b8d72671b25e86 100644 (file)
@@ -860,3 +860,35 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux)
        i2c_del_adapter(&aux->ddc);
 }
 EXPORT_SYMBOL(drm_dp_aux_unregister);
+
+#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
+
+/**
+ * drm_dp_psr_setup_time() - PSR setup in time usec
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * PSR setup time for the panel in microseconds,  negative
+ * error code on failure.
+ */
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+       static const u16 psr_setup_time_us[] = {
+               PSR_SETUP_TIME(330),
+               PSR_SETUP_TIME(275),
+               PSR_SETUP_TIME(165),
+               PSR_SETUP_TIME(110),
+               PSR_SETUP_TIME(55),
+               PSR_SETUP_TIME(0),
+       };
+       int i;
+
+       i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
+       if (i >= ARRAY_SIZE(psr_setup_time_us))
+               return -EINVAL;
+
+       return psr_setup_time_us[i];
+}
+EXPORT_SYMBOL(drm_dp_psr_setup_time);
+
+#undef PSR_SETUP_TIME
index 72dee1213268100402fdd91313c353b709507ef8..63b8bd50244479a4cebe0d9ddf766fca375a7bcf 100644 (file)
@@ -657,6 +657,8 @@ struct edp_vsc_psr {
 #define EDP_VSC_PSR_UPDATE_RFB         (1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID   (1<<2)
 
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+
 static inline int
 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {