#include <mach/iomap.h>
#include <mach/system.h>
+#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441);
tegra_pmc_init();
+ tegra_powergate_init();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
tegra30_init_clocks();
tegra_init_cache(0x441, 0x551);
tegra_pmc_init();
+ tegra_powergate_init();
}
#endif
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
+int __init tegra_powergate_init(void);
+
+int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
#define PWRGATE_STATUS 0x38
static int tegra_num_powerdomains;
+static int tegra_num_cpu_domains;
+static u8 *tegra_cpu_domains;
+static u8 tegra30_cpu_domains[] = {
+ TEGRA_POWERGATE_CPU0,
+ TEGRA_POWERGATE_CPU1,
+ TEGRA_POWERGATE_CPU2,
+ TEGRA_POWERGATE_CPU3,
+};
static DEFINE_SPINLOCK(tegra_powergate_lock);
return ret;
}
+int tegra_cpu_powergate_id(int cpuid)
+{
+ if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
+ return tegra_cpu_domains[cpuid];
+
+ return -EINVAL;
+}
+
int __init tegra_powergate_init(void)
{
switch (tegra_chip_id) {
break;
case TEGRA30:
tegra_num_powerdomains = 14;
+ tegra_num_cpu_domains = 4;
+ tegra_cpu_domains = tegra30_cpu_domains;
break;
default:
/* Unknown Tegra variant. Disable powergating */
return 0;
}
-arch_initcall(tegra_powergate_init);
#ifdef CONFIG_DEBUG_FS