DHDCFLAGS = -Wall -Wstrict-prototypes -Wno-date-time \
-Dlinux -DLINUX -DBCMDRIVER \
-Wno-unused-but-set-variable \
- -Wno-maybe-uninitialized -Wno-error -Wno-format-security \
+ -Wno-maybe-uninitialized -Wno-error -Wno-format-security \
-Wno-unknown-warning-option -Wno-sometimes-uninitialized \
-Wno-parentheses-equality -Wno-implicit-fallthrough \
-DBCMDONGLEHOST -DBCMDMA32 -DBCMFILEIMAGE \
DHDOFILES += wl_linux_mon.o wl_cfg_btcoex.o wl_cfgvendor.o
DHDOFILES += dhd_cfg80211.o wl_cfgvif.o wl_roam.o
DHDCFLAGS += -DWL_CFG80211 -DWLP2P -DWL_CFG80211_STA_EVENT
+ DHDCFLAGS += -DWL_CAP_HE
DHDCFLAGS += -DWL_IFACE_COMB_NUM_CHANNELS
DHDCFLAGS += -DCUSTOM_PNO_EVENT_LOCK_xTIME=10
DHDCFLAGS += -DWL_SUPPORT_AUTO_CHANNEL
DHDCFLAGS += -DESCAN_RESULT_PATCH -DESCAN_BUF_OVERFLOW_MGMT
DHDCFLAGS += -DVSDB -DWL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
DHDCFLAGS += -DWLTDLS -DMIRACAST_AMPDU_SIZE=8
+# DHDCFLAGS += -DHOSTAPD_BW_SUPPORT
+# DHDCFLAGS += -DHOSTAPD_EID_EXTENSION_SUPPORT
DHDCFLAGS += -DWL_VIRTUAL_APSTA -DSTA_MGMT
DHDCFLAGS += -DPNO_SUPPORT -DEXPLICIT_DISCIF_CLEANUP
DHDCFLAGS += -DDHD_USE_SCAN_WAKELOCK
DHDCFLAGS += -DSPECIFIC_MAC_GEN_SCHEME
DHDCFLAGS += -DWL_IFACE_MGMT
+ DHDCFLAGS += -DSUPPORT_RSSI_SUM_REPORT
DHDCFLAGS += -DWLFBT -DWL_GCMP_SUPPORT
DHDCFLAGS += -DROAM_CHANNEL_CACHE -DDHD_LOSSLESS_ROAMING -DWL_ROAM_WAR
+# DHDCFLAGS += -DVNDR_IE_WAR -DGET_FW_IE_DATA
DHDCFLAGS += -DGTK_OFFLOAD_SUPPORT
DHDCFLAGS += -DRESTART_AP_WAR
DHDCFLAGS += -DWL_STATIC_IF
DHDCFLAGS += -DDHD_LB -DDHD_LB_RXP -DDHD_LB_STATS -DDHD_LB_TXP
DHDCFLAGS += -DDHD_PKTID_AUDIT_ENABLED
DHDCFLAGS += -DINSMOD_FW_LOAD
-DHDCFLAGS += -DCONFIG_HAS_WAKELOCK
+DHDCFLAGS += -DCONFIG_HAS_WAKELOCK #-DDHD_DEBUG_WAKE_LOCK
+DHDCFLAGS += -DDHD_PACKET_TIMEOUT_MS=50 -DMAX_TX_TIMEOUT=50
DHDCFLAGS :=$(filter-out -DENABLE_INSMOD_NO_FW_LOAD,$(DHDCFLAGS))
#DHDCFLAGS += -DDHD_PCIE_RUNTIMEPM -DMAX_IDLE_COUNT=11 -DCUSTOM_DHD_RUNTIME_MS=100
ifeq ($(CONFIG_BCMDHD_OOB),y)
DHDCFLAGS += -DINSMOD_FW_LOAD
DHDCFLAGS += -DBCM_REQUEST_FW
DHDCFLAGS += -DSHOW_LOGTRACE
+DHDCFLAGS += -DWL_EXT_WOWL
ifneq ($(CONFIG_BCMDHD_REQUEST_FW),y)
DHDCFLAGS += -DEXTERNAL_FW_PATH
endif
ifneq ($(CONFIG_CFG80211),)
DHDCFLAGS += -DWL_EXT_RECONNECT -DWL_REASSOC_BCAST
DHDCFLAGS += -DWL_EXT_DISCONNECT_RECONNECT
-endif
+endif
endif
# For TPUT_IMPROVE
endif
endif
+ifeq ($(CONFIG_BCMDHD),y)
+ DHDCFLAGS += -DUSE_LATE_INITCALL_SYNC
+ DHDCFLAGS += -DBCM_USE_PLATFORM_STRLCPY
+endif
ifeq ($(CONFIG_BCMDHD),m)
DHDCFLAGS += -DBCMDHD_MODULAR
endif
+++ /dev/null
-#
-# Broadcom Proprietary and Confidential. Copyright (C) 2020,
-# All Rights Reserved.
-#
-# This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
-# the contents of this file may not be disclosed to third parties,
-# copied or duplicated in any form, in whole or in part, without
-# the prior written permission of Broadcom.
-#
-#
-# <<Broadcom-WL-IPTag/Secret:>>
-
-# This file should be seen only by internal builds because it will
-# be mentioned only in internal filelists like brcm.flist.
-# See extended comment bcminternal.mk for details.
-
-BCMINTERNAL := 1
-
-BCMINTERNAL_DFLAGS += -DDHD_NO_MOG
-
-ifneq ($(CONFIG_BCMDHD_PCIE),)
- # Enable Register access via dhd IOVAR
- BCMINTERNAL_DFLAGS += -DDHD_PCIE_REG_ACCESS
- # latency timestamping
- BCMINTERNAL_DFLAGS += -DDHD_PKTTS
- # Traffic Pattern Analysis on Socket Flow
- BCMINTERNAL_DFLAGS += -DDHD_QOS_ON_SOCK_FLOW
- # QoS unit testing support
- BCMINTERNAL_DFLAGS += -DDHD_QOS_ON_SOCK_FLOW_UT
- # Auto QOS
- BCMINTERNAL_DFLAGS += -DWL_AUTO_QOS
-
- ifneq ($(filter -DCUSTOMER_HW4, $(DHDCFLAGS)),)
- # These will be moved to hw4 Makefile for 4389b0
- BCMINTERNAL_DFLAGS += -DWBRC
- BCMINTERNAL_DFLAGS += -DWLAN_ACCEL_BOOT
- BCMINTERNAL_DFLAGS += -DDHD_HTPUT_TUNABLES
- # BCMINTERNAL_DFLAGS += -DDHD_FIS_DUMP
- # SCAN TYPES, if kernel < 4.17 ..back port support required
- ifneq ($(CONFIG_CFG80211_SCANTYPE_BKPORT),)
- DHDCFLAGS += -DWL_SCAN_TYPE
- endif
- # Jig builds
- # No reset during dhd attach
- BCMINTERNAL_DFLAGS += -DDHD_SKIP_DONGLE_RESET_IN_ATTACH
- # Dongle Isolation will ensure no resets devreset ON/OFF
- BCMINTERNAL_DFLAGS += -DDONGLE_ENABLE_ISOLATION
- # Quiesce dongle using DB7 trap
- BCMINTERNAL_DFLAGS += -DDHD_DONGLE_TRAP_IN_DETACH
- # Collect socram during dongle init failurs for internal builds
- BCMINTERNAL_DFLAGS += -DDEBUG_DNGL_INIT_FAIL
- # Dongle reset during Wifi ON to keep in sane state
- BCMINTERNAL_DFLAGS += -DFORCE_DONGLE_RESET_IN_DEVRESET_ON
- # Perform Backplane Reset else FLR will happen
- # BCMINTERNAL_DFLAGS += -DDHD_USE_BP_RESET_SS_CTRL
- BCMINTERNAL_DFLAGS += -DWIFI_TURNOFF_DELAY=10
-
- endif
-
- # NCI_BUS support
- BCMINTERNAL_DFLAGS += -DSOCI_NCI_BUS
-endif
-
-
-BCMINTERNAL_DFLAGS += -DDHD_BUS_MEM_ACCESS
-
-# Support multiple chips
-BCMINTERNAL_DFLAGS += -DSUPPORT_MULTIPLE_CHIPS
-
-# Support unreleased chips
-BCMINTERNAL_DFLAGS += -DUNRELEASEDCHIP
-
-# Collect socram if readshared fails
-BCMINTERNAL_DFLAGS += -DDEBUG_DNGL_INIT_FAIL
-
-# Force enable memdump value to DUMP_MEMFILE if it is disabled
-BCMINTERNAL_DFLAGS += -DDHD_INIT_DEFAULT_MEMDUMP
-
-ifneq ($(filter -DDHD_QOS_ON_SOCK_FLOW,$(BCMINTERNAL_DFLAGS)),)
-BCMINTERNAL_DHDOFILES += dhd_linux_sock_qos.o
-endif
-ifneq ($(filter -DSOCI_NCI_BUS,$(BCMINTERNAL_DFLAGS)),)
-BCMINTERNAL_DHDOFILES += nciutils.o
-endif
-ifneq ($(filter -DWBRC,$(BCMINTERNAL_DFLAGS)),)
-BCMINTERNAL_DHDOFILES += wb_regon_coordinator.o
-endif
-# vim: filetype=make shiftwidth=2
+++ /dev/null
-#
-# Broadcom Proprietary and Confidential. Copyright (C) 2020,
-# All Rights Reserved.
-#
-# This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
-# the contents of this file may not be disclosed to third parties,
-# copied or duplicated in any form, in whole or in part, without
-# the prior written permission of Broadcom.
-#
-#
-# <<Broadcom-WL-IPTag/Secret:>>
-
-# This file should be seen only by internal builds because it will
-# be mentioned only in internal filelists like brcm.flist. The idea
-# is that it will be conditionally included by makefiles using the
-# "-include" syntax, with the result that internal builds will see
-# this file and set BCMINTERNAL which will eventually result in a
-# -DBCMINTERNAL option passed to the compiler along with possible
-# other effects. External builds will never see it and it will be
-# silently ignored.
-#
-# Any settings which should not be exposed to customers may be
-# placed here. For instance, if we were working on a super-secret
-# new feature in supersecret.c we could set a variable here like
-# BCMINTERNAL_OBJECTS := supersecret.o
-# and later say
-# OBJECTS += $(BCMINTERNAL_OBJECTS)
-# within the main makefile.
-#
-# The key point is that this file is never shipped to customers
-# because it's present only in internal filelists so anything
-# here is private.
-
-BCMINTERNAL := 1
-
-BCMINTERNAL_DFLAGS += -DBCMINTERNAL
-BCMINTERNAL_DFLAGS += -DDHD_NO_MOG
-
-# Support unreleased chips
-BCMINTERNAL_DFLAGS += -DUNRELEASEDCHIP
-
-ifneq ($(findstring -fwtrace,-$(TARGET)-),)
- BCMINTERNAL_DFLAGS += -DDHD_FWTRACE
- BCMINTERNAL_CFILES += dhd_fwtrace.c
-endif
-
-# support only for SDIO MFG Fedora builds
-ifneq ($(findstring -sdstd-,-$(TARGET)-),)
- ifneq ($(findstring -mfgtest-,-$(TARGET)-),)
- BCMINTERNAL_DFLAGS += -DDHD_SPROM
- BCMINTERNAL_CFILES += bcmsrom.c bcmotp.c
- endif
-endif
-
-ifneq ($(findstring -pciefd-,$(TARGET)-),)
-# NCI_BUS support
-BCMINTERNAL_DFLAGS += -DSOCI_NCI_BUS -DBOOKER_NIC400_INF
-BCMINTERNAL_CFILES += nciutils.c
-endif
-# vim: filetype=make shiftwidth=2
#endif /* !defined(OOB_INTR_ONLY) */
static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr);
#if defined(ENABLE_INSMOD_NO_FW_LOAD) && !defined(BUS_POWER_RESTORE)
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) && defined(MMC_SW_RESET)
+#if defined(MMC_SW_RESET) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
+extern int mmc_sw_reset(struct mmc_card *card);
+#else
extern int mmc_sw_reset(struct mmc_host *host);
+#endif
+#elif defined(MMC_HW_RESET) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
+extern int mmc_hw_reset(struct mmc_card *card);
+#else
+extern int mmc_hw_reset(struct mmc_host *host);
+#endif
#else
extern int sdio_reset_comm(struct mmc_card *card);
#endif
err_ret = sdio_enable_func(sd->func[1]);
sdio_release_host(sd->func[1]);
if (err_ret) {
- sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x\n", err_ret));
+ sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: %d\n", err_ret));
}
return FALSE;
if (err_ret)
#endif /* MMC_SDIO_ABORT */
{
- sd_err(("bcmsdh_sdmmc: Failed to %s word F%d:@0x%05x=%02x, Err: 0x%08x\n",
+ sd_err(("bcmsdh_sdmmc: Failed to %s word F%d:@0x%05x=%02x, Err: %d\n",
rw ? "Write" : "Read", func, addr, *word, err_ret));
}
}
#if defined(ENABLE_INSMOD_NO_FW_LOAD) && !defined(BUS_POWER_RESTORE)
static int sdio_sw_reset(sdioh_info_t *sd)
{
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) && defined(MMC_SW_RESET)
- struct mmc_host *host = sd->func[0]->card->host;
-#endif
+ struct mmc_card *card = sd->func[0]->card;
int err = 0;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) && defined(MMC_SW_RESET)
- printf("%s: Enter\n", __FUNCTION__);
+#if defined(MMC_SW_RESET) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0)
+ /* MMC_SW_RESET */
+ printf("%s: call mmc_sw_reset\n", __FUNCTION__);
sdio_claim_host(sd->func[0]);
- err = mmc_sw_reset(host);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
+ err = mmc_sw_reset(card);
+#else
+ err = mmc_sw_reset(card->host);
+#endif
+ sdio_release_host(sd->func[0]);
+#elif defined(MMC_HW_RESET) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)
+ /* MMC_HW_RESET */
+ printf("%s: call mmc_hw_reset\n", __FUNCTION__);
+ sdio_claim_host(sd->func[0]);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)
+ while (atomic_read(&card->sdio_funcs_probed) > 1) {
+ atomic_dec(&card->sdio_funcs_probed);
+ }
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
+ err = mmc_hw_reset(card);
+#else
+ err = mmc_hw_reset(card->host);
+#endif
sdio_release_host(sd->func[0]);
#else
- err = sdio_reset_comm(sd->func[0]->card);
+ /* sdio_reset_comm */
+ err = sdio_reset_comm(card);
#endif
if (err)
+++ /dev/null
-/*
- * Monitor Mode routines.
- * This header file housing the Monitor Mode routines implementation.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#include <bcmutils.h>
-#include <bcmendian.h>
-#include <hndd11.h>
-#include <bcmwifi_channels.h>
-#include <bcmwifi_radiotap.h>
-#include <bcmwifi_monitor.h>
-#include <bcmwifi_rates.h>
-#include <monitor.h>
-#include <d11_cfg.h>
-
-struct monitor_info {
- ratespec_t ampdu_rspec; /* spec value for AMPDU sniffing */
- uint16 ampdu_counter;
- uint16 amsdu_len;
- uint8* amsdu_pkt;
- int8 headroom;
- d11_info_t *d11_info;
- uint8 ampdu_plcp[D11_PHY_HDR_LEN];
-};
-
-struct he_ltf_gi_info {
- uint8 gi;
- uint8 ltf_size;
- uint8 num_ltf;
-};
-
-struct he_mu_ltf_mp_info {
- uint8 num_ltf;
- uint8 mid_per;
-};
-
-/*
- * su ppdu - mapping of ltf and gi values from plcp to rtap data format
- * https://www.radiotap.org/fields/HE.html
- */
-static const struct he_ltf_gi_info he_plcp2ltf_gi[4] = {
- {3, 0, 7}, /* reserved, reserved, reserved */
- {0, 2, 1}, /* 0.8us, 2x, 2x */
- {1, 2, 1}, /* 1.6us, 2x, 2x */
- {2, 3, 2} /* 3.2us, 4x, 4x */
-};
-
-/*
- * mu ppdu - mapping of ru type value from phy rxstatus to rtap data format
- * https://www.radiotap.org/fields/HE.html
- */
-static const uint8 he_mu_phyrxs2ru_type[7] = {
- 4, /* 26-tone RU */
- 5, /* 52-tone RU */
- 6, /* 106-tone RU */
- 7, /* 242-tone RU */
- 8, /* 484-tone RU */
- 9, /* 996-tone RU */
- 10 /* 2x996-tone RU */
-};
-
-/*
- * mu ppdu - doppler:1, mapping of ltf and midamble periodicity values from plcp to rtap data format
- * https://www.radiotap.org/fields/HE.html
- */
-static const struct he_mu_ltf_mp_info he_mu_plcp2ltf_mp[8] = {
- {0, 0}, /* 1x, 10 */
- {1, 0}, /* 2x, 10 */
- {2, 0}, /* 4x, 10 */
- {7, 0}, /* reserved, reserved */
- {0, 1}, /* 1x, 20 */
- {1, 1}, /* 2x, 20 */
- {2, 1}, /* 4x, 20 */
- {7, 0} /* reserved, reserved */
-};
-
-/*
- * mu ppdu - doppler:0, mapping of ltf value from plcp to rtap data format
- * https://www.radiotap.org/fields/HE.html
- */
-static const uint8 he_mu_plcp2ltf[8] = {
- 0, /* 1x */
- 1, /* 2x */
- 2, /* 4x */
- 3, /* 6x */
- 4, /* 8x */
- 7, /* reserved */
- 7, /* reserved */
- 7 /* reserved */
-};
-
-/** Calculate the rate of a received frame and return it as a ratespec (monitor mode) */
-static ratespec_t
-BCMFASTPATH(wlc_recv_mon_compute_rspec)(monitor_info_t* info, wlc_d11rxhdr_t *wrxh, uint8 *plcp)
-{
- d11rxhdr_t *rxh = &wrxh->rxhdr;
- ratespec_t rspec = 0;
- uint16 phy_ft;
- uint corerev = info->d11_info->major_revid;
- uint corerev_minor = info->d11_info->minor_revid;
- BCM_REFERENCE(corerev_minor);
-
- phy_ft = D11PPDU_FT(rxh, corerev);
- switch (phy_ft) {
- case FT_CCK:
- rspec = CCK_RSPEC(CCK_PHY2MAC_RATE(((cck_phy_hdr_t *)plcp)->signal));
- rspec |= WL_RSPEC_BW_20MHZ;
- break;
- case FT_OFDM:
- rspec = OFDM_RSPEC(OFDM_PHY2MAC_RATE(((ofdm_phy_hdr_t *)plcp)->rlpt[0]));
- rspec |= WL_RSPEC_BW_20MHZ;
- break;
- case FT_HT: {
- uint ht_sig1, ht_sig2;
- uint8 stbc;
-
- ht_sig1 = plcp[0]; /* only interested in low 8 bits */
- ht_sig2 = plcp[3] | (plcp[4] << 8); /* only interested in low 10 bits */
-
- rspec = HT_RSPEC((ht_sig1 & HT_SIG1_MCS_MASK));
- if (ht_sig1 & HT_SIG1_CBW) {
- /* indicate rspec is for 40 MHz mode */
- rspec |= WL_RSPEC_BW_40MHZ;
- } else {
- /* indicate rspec is for 20 MHz mode */
- rspec |= WL_RSPEC_BW_20MHZ;
- }
- if (ht_sig2 & HT_SIG2_SHORT_GI)
- rspec |= WL_RSPEC_SGI;
- if (ht_sig2 & HT_SIG2_FEC_CODING)
- rspec |= WL_RSPEC_LDPC;
- stbc = ((ht_sig2 & HT_SIG2_STBC_MASK) >> HT_SIG2_STBC_SHIFT);
- if (stbc != 0) {
- rspec |= WL_RSPEC_STBC;
- }
- break;
- }
- case FT_VHT:
- rspec = wf_vht_plcp_to_rspec(plcp);
- break;
-#ifdef WL11AX
- case FT_HE:
- rspec = wf_he_plcp_to_rspec(plcp);
- break;
-#endif /* WL11AX */
-#ifdef WL11BE
- case FT_EHT:
- rspec = wf_eht_plcp_to_rspec(plcp);
- break;
-#endif
- default:
- /* return a valid rspec if not a debug/assert build */
- rspec = OFDM_RSPEC(6) | WL_RSPEC_BW_20MHZ;
- break;
- }
-
- return rspec;
-} /* wlc_recv_compute_rspec */
-
-static void
-wlc_he_su_fill_rtap_data(struct wl_rxsts *sts, uint8 *plcp)
-{
- ASSERT(plcp);
-
- /* he ppdu format */
- sts->data1 |= WL_RXS_HEF_SIGA_PPDU_SU;
-
- /* bss color */
- sts->data1 |= WL_RXS_HEF_SIGA_BSS_COLOR;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, BSS_COLOR);
-
- /* beam change */
- sts->data1 |= WL_RXS_HEF_SIGA_BEAM_CHANGE;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, BEAM_CHANGE);
-
- /* ul/dl */
- sts->data1 |= WL_RXS_HEF_SIGA_DL_UL;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, DL_UL);
-
- /* data mcs */
- sts->data1 |= WL_RXS_HEF_SIGA_MCS;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, MCS);
-
- /* data dcm */
- sts->data1 |= WL_RXS_HEF_SIGA_DCM;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, DCM);
-
- /* coding */
- sts->data1 |= WL_RXS_HEF_SIGA_CODING;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, CODING);
-
- /* ldpc extra symbol segment */
- sts->data1 |= WL_RXS_HEF_SIGA_LDPC;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, LDPC);
-
- /* stbc */
- sts->data1 |= WL_RXS_HEF_SIGA_STBC;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, STBC);
-
- /* spatial reuse */
- sts->data1 |= WL_RXS_HEF_SIGA_SPATIAL_REUSE;
- sts->data4 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, SR);
-
- /* data bw */
- sts->data1 |= WL_RXS_HEF_SIGA_BW;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, BW);
-
- /* gi */
- sts->data2 |= WL_RXS_HEF_SIGA_GI;
- sts->data5 |= HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, SU, GI, gi);
-
- /* ltf symbol size */
- sts->data2 |= WL_RXS_HEF_SIGA_LTF_SIZE;
- sts->data5 |= HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, SU, LTF_SIZE, ltf_size);
-
- /* number of ltf symbols */
- sts->data2 |= WL_RXS_HEF_SIGA_NUM_LTF;
- sts->data5 |= HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, SU, NUM_LTF, num_ltf);
-
- /* pre-fec padding factor */
- sts->data2 |= WL_RXS_HEF_SIGA_PADDING;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, PADDING);
-
- /* txbf */
- sts->data2 |= WL_RXS_HEF_SIGA_TXBF;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, TXBF);
-
- /* pe disambiguity */
- sts->data2 |= WL_RXS_HEF_SIGA_PE;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, PE);
-
- /*
- * if doppler (bit:41) is set in plcp to 1 then,
- * - bit:25 indicates 'midamble periodicity'
- * - bit:23-24 indicate 'nsts'
- *
- * if doppler (bit:41) is set to 0 then,
- * - bit:23-25 indicate 'nsts'
- */
- if (HE_EXTRACT_FROM_PLCP(plcp, SU, DOPPLER)) {
- /* doppler */
- sts->data1 |= WL_RXS_HEF_SIGA_DOPPLER;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, DOPPLER);
-
- /* midamble periodicity */
- sts->data2 |= WL_RXS_HEF_SIGA_MIDAMBLE;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, MIDAMBLE);
-
- /* nsts */
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, DOPPLER_SET_NSTS);
- } else {
- /* nsts */
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, DOPPLER_NOTSET_NSTS);
- }
-
- /* txop */
- sts->data2 |= WL_RXS_HEF_SIGA_TXOP;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, SU, TXOP);
-}
-
-static void
-wlc_he_dl_ofdma_fill_rtap_data(struct wl_rxsts *sts, d11rxhdr_t *rxh,
- uint8 *plcp, uint32 corerev, uint32 corerev_minor)
-{
- uint8 doppler, midamble, val;
- ASSERT(rxh);
- ASSERT(plcp);
-
- /* he ppdu format */
- sts->data1 |= WL_RXS_HEF_SIGA_PPDU_MU;
-
- /* bss color */
- sts->data1 |= WL_RXS_HEF_SIGA_BSS_COLOR;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, BSS_COLOR);
-
- /* beam change (doesn't apply to mu ppdu) */
- sts->data1 &= ~WL_RXS_HEF_SIGA_BEAM_CHANGE;
-
- /* ul/dl */
- sts->data1 |= WL_RXS_HEF_SIGA_DL_UL;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, DL_UL);
-
- /* data mcs */
- sts->data1 |= WL_RXS_HEF_SIGA_MCS;
- sts->data3 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, MCS);
-
- /* data dcm */
- sts->data1 |= WL_RXS_HEF_SIGA_DCM;
- sts->data3 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, DCM);
-
- /* coding */
- sts->data1 |= WL_RXS_HEF_SIGA_CODING;
- sts->data3 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, CODING);
-
- /* ldpc extra symbol segment */
- sts->data1 |= WL_RXS_HEF_SIGA_LDPC;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, LDPC);
-
- /* stbc */
- sts->data1 |= WL_RXS_HEF_SIGA_STBC;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, STBC);
-
- /* spatial reuse */
- sts->data1 |= WL_RXS_HEF_SIGA_SPATIAL_REUSE;
- sts->data4 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, SR);
-
- /* sta-id */
- sts->data1 |= WL_RXS_HEF_SIGA_STA_ID;
- sts->data4 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, STAID);
-
- /* ru allocation */
- val = he_mu_phyrxs2ru_type[D11PPDU_RU_TYPE(rxh, corerev, corerev_minor)];
- sts->data1 |= WL_RXS_HEF_SIGA_RU_ALLOC;
- sts->data5 |= HE_PACK_RTAP_FROM_VAL(val, RU_ALLOC);
-
- /* doppler */
- sts->data1 |= WL_RXS_HEF_SIGA_DOPPLER;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, DOPPLER);
-
- doppler = HE_EXTRACT_FROM_PLCP(plcp, MU, DOPPLER);
- midamble = HE_EXTRACT_FROM_PLCP(plcp, MU, MIDAMBLE);
- if (doppler) {
- /* number of ltf symbols */
- val = he_mu_plcp2ltf_mp[midamble].num_ltf;
- sts->data2 |= WL_RXS_HEF_SIGA_NUM_LTF;
- sts->data5 |= HE_PACK_RTAP_FROM_VAL(val, NUM_LTF);
-
- /* midamble periodicity */
- val = he_mu_plcp2ltf_mp[midamble].mid_per;
- sts->data2 |= WL_RXS_HEF_SIGA_MIDAMBLE;
- sts->data6 |= HE_PACK_RTAP_FROM_VAL(val, MIDAMBLE);
- } else {
- /* number of ltf symbols */
- val = he_mu_plcp2ltf[midamble];
- sts->data2 |= WL_RXS_HEF_SIGA_NUM_LTF;
- sts->data5 |= HE_PACK_RTAP_FROM_VAL(val, NUM_LTF);
- }
-
- /* nsts */
- sts->data6 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, NSTS);
-
- /* gi */
- sts->data2 |= WL_RXS_HEF_SIGA_GI;
- sts->data5 |= HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, MU, GI, gi);
-
- /* ltf symbol size */
- sts->data2 |= WL_RXS_HEF_SIGA_LTF_SIZE;
- sts->data5 |= HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, MU, LTF_SIZE, ltf_size);
-
- /* pre-fec padding factor */
- sts->data2 |= WL_RXS_HEF_SIGA_PADDING;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, PADDING);
-
- /* txbf */
- sts->data2 |= WL_RXS_HEF_SIGA_TXBF;
- sts->data5 |= HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, TXBF);
-
- /* pe disambiguity */
- sts->data2 |= WL_RXS_HEF_SIGA_PE;
- sts->data5 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, PE);
-
- /* txop */
- sts->data2 |= WL_RXS_HEF_SIGA_TXOP;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, TXOP);
-}
-
-static void
-wlc_he_dl_ofdma_fill_rtap_flag(struct wl_rxsts *sts, uint8 *plcp, uint32 corerev)
-{
- ASSERT(plcp);
-
- /* sig-b mcs */
- sts->flag1 |= WL_RXS_HEF_SIGB_MCS_KNOWN;
- sts->flag1 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, SIGB_MCS);
-
- /* sig-b dcm */
- sts->flag1 |= WL_RXS_HEF_SIGB_DCM_KNOWN;
- sts->flag1 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, SIGB_DCM);
-
- /* sig-b compression */
- sts->flag1 |= WL_RXS_HEF_SIGB_COMP_KNOWN;
- sts->flag2 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, SIGB_COMP);
-
- /* # of he-sig-b symbols/mu-mimo users */
- sts->flag1 |= WL_RXS_HEF_NUM_SIGB_SYMB_KNOWN;
- sts->flag2 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, SIGB_SYM_MU_MIMO_USER);
-
- /* bandwidth from bandwidth field in he-sig-a */
- sts->flag2 |= WL_RXS_HEF_BW_SIGA_KNOWN;
- sts->flag2 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, BW_SIGA);
-
- /* preamble puncturing from bandwidth field in he-sig-a */
- sts->flag2 |= WL_RXS_HEF_PREPUNCR_SIGA_KNOWN;
- sts->flag2 |= HE_PACK_RTAP_FROM_PLCP(plcp, MU, PRE_PUNCR_SIGA);
-}
-
-static void
-wlc_he_ul_ofdma_fill_rtap_data(struct wl_rxsts *sts, d11rxhdr_t *rxh, uint8 *plcp,
- uint32 corerev)
-{
- ASSERT(rxh);
- ASSERT(plcp);
-
- BCM_REFERENCE(rxh);
-
- /* he ppdu format */
- sts->data1 |= WL_RXS_HEF_SIGA_PPDU_TRIG;
-
- /* bss color */
- sts->data1 |= WL_RXS_HEF_SIGA_BSS_COLOR;
- sts->data3 |= HE_PACK_RTAP_FROM_PLCP(plcp, TRIG, BSS_COLOR);
-
- /* beam change (doesn't apply to mu ppdu) */
- sts->data1 &= ~WL_RXS_HEF_SIGA_BEAM_CHANGE;
-
- /* ul/dl */
- sts->data1 |= WL_RXS_HEF_SIGA_DL_UL;
- sts->data3 |= HE_PACK_RTAP_FROM_VAL(1, DL_UL);
-
- /* txop */
- sts->data2 |= WL_RXS_HEF_SIGA_TXOP;
- sts->data6 |= HE_PACK_RTAP_FROM_PLCP(plcp, TRIG, TXOP);
-}
-
-/* recover 32bit TSF value from the 16bit TSF value */
-/* assumption is time in rxh is within 65ms of the current tsf */
-/* local TSF inserted in the rxh is at RxStart which is before 802.11 header */
-static uint32
-wlc_recover_tsf32(uint16 rxh_tsf, uint32 ts_tsf)
-{
- uint16 rfdly;
-
- /* adjust rx dly added in RxTSFTime */
- /* comment in d11.h:
- * BWL_PRE_PACKED_STRUCT struct d11rxhdr {
- * ...
- * uint16 RxTSFTime; RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY
- * ...
- * }
- */
-
- /* TODO: add PHY type specific value here... */
- rfdly = M_BPHY_PLCPRX_DLY;
-
- rxh_tsf -= rfdly;
-
- return (((ts_tsf - rxh_tsf) & 0xFFFF0000) | rxh_tsf);
-}
-
-static uint8
-wlc_vht_get_gid(uint8 *plcp)
-{
- uint32 plcp0 = plcp[0] | (plcp[1] << 8);
- return (plcp0 & VHT_SIGA1_GID_MASK) >> VHT_SIGA1_GID_SHIFT;
-}
-
-static uint16
-wlc_vht_get_aid(uint8 *plcp)
-{
- uint32 plcp0 = plcp[0] | (plcp[1] << 8) | (plcp[2] << 16);
- return (plcp0 & VHT_SIGA1_PARTIAL_AID_MASK) >> VHT_SIGA1_PARTIAL_AID_SHIFT;
-}
-
-static bool
-wlc_vht_get_txop_ps_not_allowed(uint8 *plcp)
-{
- return !!(plcp[2] & (VHT_SIGA1_TXOP_PS_NOT_ALLOWED >> 16));
-}
-
-static bool
-wlc_vht_get_sgi_nsym_da(uint8 *plcp)
-{
- return !!(plcp[3] & VHT_SIGA2_GI_W_MOD10);
-}
-
-static bool
-wlc_vht_get_ldpc_extra_symbol(uint8 *plcp)
-{
- return !!(plcp[3] & VHT_SIGA2_LDPC_EXTRA_OFDM_SYM);
-}
-
-static bool
-wlc_vht_get_beamformed(uint8 *plcp)
-{
- return !!(plcp[4] & (VHT_SIGA2_BEAMFORM_ENABLE >> 8));
-}
-/* Convert htflags and mcs values to
-* rate in units of 500kbps
-*/
-static uint16
-wlc_ht_phy_get_rate(uint8 htflags, uint8 mcs)
-{
-
- ratespec_t rspec = HT_RSPEC(mcs);
-
- if (htflags & WL_RXS_HTF_40)
- rspec |= WL_RSPEC_BW_40MHZ;
-
- if (htflags & WL_RXS_HTF_SGI)
- rspec |= WL_RSPEC_SGI;
-
- return RSPEC2KBPS(rspec)/500;
-}
-
-static void
-bcmwifi_update_rxpwr_per_ant(monitor_pkt_rxsts_t *pkt_rxsts, wlc_d11rxhdr_t *wrxh)
-{
- int i = 0;
- wlc_d11rxhdr_ext_t *wrxh_ext = (wlc_d11rxhdr_ext_t *)((uint8 *)wrxh - WLC_SWRXHDR_EXT_LEN);
-
- BCM_REFERENCE(wrxh_ext);
-
- pkt_rxsts->corenum = 0;
-
- for (i = 0; i < WL_RSSI_ANT_MAX; i++) {
-#ifdef BCM_MON_QDBM_RSSI
- pkt_rxsts->rxpwr[i].dBm = wrxh_ext->rxpwr[i].dBm;
- pkt_rxsts->rxpwr[i].decidBm = wrxh_ext->rxpwr[i].decidBm;
-#else
- pkt_rxsts->rxpwr[i].dBm = wrxh->rxpwr[i];
- pkt_rxsts->rxpwr[i].decidBm = 0;
-#endif
- if (pkt_rxsts->rxpwr[i].dBm == 0) {
- break;
- }
- pkt_rxsts->corenum ++;
- }
-}
-
-static void
-bcmwifi_parse_ampdu(monitor_info_t *info, d11rxhdr_t *rxh, uint16 subtype, ratespec_t rspec,
- uint8 *plcp, struct wl_rxsts *sts)
-{
- uint32 corerev = info->d11_info->major_revid;
- uint32 corerev_minor = info->d11_info->minor_revid;
- uint32 ft = D11PPDU_FT(rxh, corerev);
- uint8 plcp_len = D11_PHY_RXPLCP_LEN(corerev);
- BCM_REFERENCE(corerev_minor);
- if ((subtype == FC_SUBTYPE_QOS_DATA) || (subtype == FC_SUBTYPE_QOS_NULL)) {
- /* A-MPDU parsing */
- switch (ft) {
- case FT_HT:
- if (WLC_IS_MIMO_PLCP_AMPDU(plcp)) {
- sts->nfrmtype |= WL_RXS_NFRM_AMPDU_FIRST;
- /* Save the rspec & plcp for later */
- info->ampdu_rspec = rspec;
- /* src & dst len are same */
- (void)memcpy_s(info->ampdu_plcp, plcp_len, plcp, plcp_len);
- } else if (!PLCP_VALID(plcp)) {
- sts->nfrmtype |= WL_RXS_NFRM_AMPDU_SUB;
- /* Use the saved rspec & plcp */
- rspec = info->ampdu_rspec;
- /* src & dst len are same */
- (void)memcpy_s(plcp, plcp_len, info->ampdu_plcp, plcp_len);
- }
- break;
-
- case FT_VHT:
- case FT_HE:
- case FT_EHT:
- if (PLCP_VALID(plcp) &&
- !IS_PHYRXHDR_VALID(rxh, corerev, corerev_minor)) {
- /* First MPDU:
- * PLCP header is valid, Phy RxStatus is not valid
- */
- sts->nfrmtype |= WL_RXS_NFRM_AMPDU_FIRST;
- /* Save the rspec & plcp for later */
- info->ampdu_rspec = rspec;
- /* src & dst len are same */
- (void)memcpy_s(info->ampdu_plcp, plcp_len, plcp, plcp_len);
- info->ampdu_counter++;
- } else if (!PLCP_VALID(plcp) &&
- !IS_PHYRXHDR_VALID(rxh, corerev, corerev_minor)) {
- /* Sub MPDU: * PLCP header is not valid,
- * Phy RxStatus is not valid
- */
- sts->nfrmtype |= WL_RXS_NFRM_AMPDU_SUB;
- /* Use the saved rspec & plcp */
- rspec = info->ampdu_rspec;
- /* src & dst len are same */
- (void)memcpy_s(plcp, plcp_len, info->ampdu_plcp, plcp_len);
- } else if (PLCP_VALID(plcp) &&
- IS_PHYRXHDR_VALID(rxh, corerev, corerev_minor)) {
- /* MPDU is not a part of A-MPDU:
- * PLCP header is valid and Phy RxStatus is valid
- */
- info->ampdu_counter++;
- } else {
- /* Last MPDU */
- /* done to take care of the last MPDU in A-mpdu
- * VHT packets are considered A-mpdu
- * Use the saved rspec
- */
- rspec = info->ampdu_rspec;
- /* src & dst len are same */
- (void)memcpy_s(plcp, plcp_len, info->ampdu_plcp, plcp_len);
- }
-
- sts->ampdu_counter = info->ampdu_counter;
- break;
-
- case FT_OFDM:
- break;
- default:
- printf("invalid frame type: %d\n", ft);
- break;
- }
- }
-}
-
-static void
-bcmwifi_update_rate_modulation_info(monitor_info_t *info, d11rxhdr_t *rxh, d11rxhdr_t *rxh_last,
- ratespec_t rspec, uint8* plcp, struct wl_rxsts *sts)
-{
- uint32 corerev = info->d11_info->major_revid;
- uint32 corerev_minor = info->d11_info->minor_revid;
-
- /* prepare rate/modulation info */
- if (RSPEC_ISVHT(rspec)) {
- uint32 bw = RSPEC_BW(rspec);
- /* prepare VHT rate/modulation info */
- sts->nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
- sts->mcs = (rspec & WL_RSPEC_VHT_MCS_MASK);
-
- if (CHSPEC_IS80(sts->chanspec)) {
- if (bw == WL_RSPEC_BW_20MHZ) {
- switch (CHSPEC_CTL_SB(sts->chanspec)) {
- default:
- case WL_CHANSPEC_CTL_SB_LL:
- sts->bw = WL_RXS_VHT_BW_20LL;
- break;
- case WL_CHANSPEC_CTL_SB_LU:
- sts->bw = WL_RXS_VHT_BW_20LU;
- break;
- case WL_CHANSPEC_CTL_SB_UL:
- sts->bw = WL_RXS_VHT_BW_20UL;
- break;
- case WL_CHANSPEC_CTL_SB_UU:
- sts->bw = WL_RXS_VHT_BW_20UU;
- break;
- }
- } else if (bw == WL_RSPEC_BW_40MHZ) {
- switch (CHSPEC_CTL_SB(sts->chanspec)) {
- default:
- case WL_CHANSPEC_CTL_SB_L:
- sts->bw = WL_RXS_VHT_BW_40L;
- break;
- case WL_CHANSPEC_CTL_SB_U:
- sts->bw = WL_RXS_VHT_BW_40U;
- break;
- }
- } else {
- sts->bw = WL_RXS_VHT_BW_80;
- }
- } else if (CHSPEC_IS40(sts->chanspec)) {
- if (bw == WL_RSPEC_BW_20MHZ) {
- switch (CHSPEC_CTL_SB(sts->chanspec)) {
- default:
- case WL_CHANSPEC_CTL_SB_L:
- sts->bw = WL_RXS_VHT_BW_20L;
- break;
- case WL_CHANSPEC_CTL_SB_U:
- sts->bw = WL_RXS_VHT_BW_20U;
- break;
- }
- } else if (bw == WL_RSPEC_BW_40MHZ) {
- sts->bw = WL_RXS_VHT_BW_40;
- }
- } else {
- sts->bw = WL_RXS_VHT_BW_20;
- }
-
- if (RSPEC_ISSTBC(rspec))
- sts->vhtflags |= WL_RXS_VHTF_STBC;
- if (wlc_vht_get_txop_ps_not_allowed(plcp))
- sts->vhtflags |= WL_RXS_VHTF_TXOP_PS;
- if (RSPEC_ISSGI(rspec)) {
- sts->vhtflags |= WL_RXS_VHTF_SGI;
- if (wlc_vht_get_sgi_nsym_da(plcp))
- sts->vhtflags |= WL_RXS_VHTF_SGI_NSYM_DA;
- }
- if (RSPEC_ISLDPC(rspec)) {
- sts->coding = WL_RXS_VHTF_CODING_LDCP;
- if (wlc_vht_get_ldpc_extra_symbol(plcp)) {
- /* need to un-set for MU-MIMO */
- sts->vhtflags |= WL_RXS_VHTF_LDPC_EXTRA;
- }
- }
- if (wlc_vht_get_beamformed(plcp))
- sts->vhtflags |= WL_RXS_VHTF_BF;
-
- sts->gid = wlc_vht_get_gid(plcp);
- sts->aid = wlc_vht_get_aid(plcp);
- sts->datarate = RSPEC2KBPS(rspec)/500;
- } else if (RSPEC_ISHT(rspec)) {
- /* prepare HT rate/modulation info */
- sts->mcs = (rspec & WL_RSPEC_HT_MCS_MASK);
-
- if (CHSPEC_IS40(sts->chanspec) || CHSPEC_IS80(sts->chanspec)) {
- uint32 bw = RSPEC_BW(rspec);
-
- if (bw == WL_RSPEC_BW_20MHZ) {
- if (CHSPEC_CTL_SB(sts->chanspec) == WL_CHANSPEC_CTL_SB_L) {
- sts->htflags = WL_RXS_HTF_20L;
- } else {
- sts->htflags = WL_RXS_HTF_20U;
- }
- } else if (bw == WL_RSPEC_BW_40MHZ) {
- sts->htflags = WL_RXS_HTF_40;
- }
- }
-
- if (RSPEC_ISSGI(rspec))
- sts->htflags |= WL_RXS_HTF_SGI;
- if (RSPEC_ISLDPC(rspec))
- sts->htflags |= WL_RXS_HTF_LDPC;
- if (RSPEC_ISSTBC(rspec))
- sts->htflags |= (1 << WL_RXS_HTF_STBC_SHIFT);
-
- sts->datarate = wlc_ht_phy_get_rate(sts->htflags, sts->mcs);
- } else if (FALSE ||
-#ifdef WL11BE
- RSPEC_ISHEEXT(rspec) ||
-#else
- RSPEC_ISHE(rspec) ||
-#endif
- FALSE) {
- sts->nss = (rspec & WL_RSPEC_NSS_MASK) >> WL_RSPEC_NSS_SHIFT;
- sts->mcs = (rspec & WL_RSPEC_MCS_MASK);
-
- if (D11PPDU_ISMU_REV80(rxh_last, corerev, corerev_minor)) {
- if (IS_PHYRXHDR_VALID(rxh_last, corerev, corerev_minor)) {
- uint16 ff_type = D11PPDU_FF_TYPE(rxh_last,
- corerev, corerev_minor);
-
- switch (ff_type) {
- case HE_MU_PPDU:
- wlc_he_dl_ofdma_fill_rtap_data(sts, rxh_last,
- plcp, corerev, corerev_minor);
- wlc_he_dl_ofdma_fill_rtap_flag(sts, plcp, corerev);
- break;
- case HE_TRIG_PPDU:
- wlc_he_ul_ofdma_fill_rtap_data(sts, rxh_last,
- plcp, corerev);
- break;
- default:
- /* should not have come here */
- ASSERT(0);
- break;
- }
- }
- } else {
- /* frame format is either SU or SU_RE (assumption only SU is supported) */
- wlc_he_su_fill_rtap_data(sts, plcp);
- }
- } else {
- /* round non-HT data rate to nearest 500bkps unit */
- sts->datarate = RSPEC2KBPS(rspec)/500;
- }
-}
-
-/* Convert RX hardware status to standard format and send to wl_monitor
- * assume p points to plcp header
- */
-static uint16
-wl_d11rx_to_rxsts(monitor_info_t* info, monitor_pkt_info_t* pkt_info, wlc_d11rxhdr_t *wrxh,
- wlc_d11rxhdr_t *wrxh_last, void *pkt, uint16 len, void* pout, uint16 pad_req)
-{
- struct wl_rxsts sts;
- monitor_pkt_rxsts_t pkt_rxsts;
- ratespec_t rspec;
- uint16 chan_num;
- uint8 *plcp;
- uint8 *p = (uint8*)pkt;
- uint8 hwrxoff = 0;
- uint32 corerev = 0;
- uint32 corerev_minor = 0;
- struct dot11_header *h;
- uint16 subtype;
- d11rxhdr_t *rxh = &(wrxh->rxhdr);
- d11rxhdr_t *rxh_last = &(wrxh_last->rxhdr);
- d11_info_t* d11i = info->d11_info;
- uint8 plcp_len = 0;
-
- BCM_REFERENCE(chan_num);
-
- ASSERT(p);
- ASSERT(info);
- pkt_rxsts.rxsts = &sts;
-
- hwrxoff = (pkt_info->marker >> 16) & 0xff;
- corerev = d11i->major_revid;
- corerev_minor = d11i->minor_revid;
- BCM_REFERENCE(corerev_minor);
-
- plcp = (uint8*)p + hwrxoff;
- plcp_len = D11_PHY_RXPLCP_LEN(corerev);
-
- /* only non short rxstatus is expected */
- if (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor)) {
- printf("short rxstatus is not expected here!\n");
- ASSERT(0);
- return 0;
- }
-
- if (RXHDR_GET_PAD_PRES(rxh, corerev, corerev_minor)) {
- plcp += 2;
- }
-
- bzero((void *)&sts, sizeof(wl_rxsts_t));
-
- sts.mactime = wlc_recover_tsf32(pkt_info->ts.ts_high, pkt_info->ts.ts_low);
-
- /* update rxpwr per antenna */
- bcmwifi_update_rxpwr_per_ant(&pkt_rxsts, wrxh);
-
- /* calculate rspec based on ppdu frame type */
- rspec = wlc_recv_mon_compute_rspec(info, wrxh, plcp);
-
- h = (struct dot11_header *)(plcp + plcp_len);
- subtype = (ltoh16(h->fc) & FC_SUBTYPE_MASK) >> FC_SUBTYPE_SHIFT;
-
- /* parse & cache respec for ampdu */
- bcmwifi_parse_ampdu(info, rxh, subtype, rspec, plcp, &sts);
-
- /* A-MSDU parsing */
- if (RXHDR_GET_AMSDU(rxh, corerev, corerev_minor)) {
- /* it's chained buffer, break it if necessary */
- sts.nfrmtype |= WL_RXS_NFRM_AMSDU_FIRST | WL_RXS_NFRM_AMSDU_SUB;
- }
-
- sts.signal = (pkt_info->marker >> 8) & 0xff;
- sts.noise = (int8)pkt_info->marker;
- sts.chanspec = D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxChan);
-
- if (wf_chspec_malformed(sts.chanspec)) {
- printf("Malformed chspec, %x\n", sts.chanspec);
- return 0;
- }
-
- /* 4360: is chan_num supposed to be primary or CF channel? */
- chan_num = CHSPEC_CHANNEL(sts.chanspec);
-
- if (PRXS5_ACPHY_DYNBWINNONHT(rxh))
- sts.vhtflags |= WL_RXS_VHTF_DYN_BW_NONHT;
- else
- sts.vhtflags &= ~WL_RXS_VHTF_DYN_BW_NONHT;
-
- switch (PRXS5_ACPHY_CHBWINNONHT(rxh)) {
- default: case PRXS5_ACPHY_CHBWINNONHT_20MHZ:
- sts.bw_nonht = WLC_20_MHZ;
- break;
- case PRXS5_ACPHY_CHBWINNONHT_40MHZ:
- sts.bw_nonht = WLC_40_MHZ;
- break;
- case PRXS5_ACPHY_CHBWINNONHT_80MHZ:
- sts.bw_nonht = WLC_80_MHZ;
- break;
- case PRXS5_ACPHY_CHBWINNONHT_160MHZ:
- sts.bw_nonht = WLC_160_MHZ;
- break;
- }
-
- /* update rate and modulation info */
- bcmwifi_update_rate_modulation_info(info, rxh, rxh_last, rspec, plcp, &sts);
-
- sts.pktlength = FRAMELEN(corerev, corerev_minor, rxh) - plcp_len;
-
- sts.phytype = WL_RXS_PHY_N;
-
- if (RSPEC_ISCCK(rspec)) {
- sts.encoding = WL_RXS_ENCODING_DSSS_CCK;
- sts.preamble = (PRXS_SHORTH(rxh, corerev, corerev_minor) ?
- WL_RXS_PREAMBLE_SHORT : WL_RXS_PREAMBLE_LONG);
- } else if (RSPEC_ISOFDM(rspec)) {
- sts.encoding = WL_RXS_ENCODING_OFDM;
- sts.preamble = WL_RXS_PREAMBLE_SHORT;
- } if (RSPEC_ISVHT(rspec)) {
- sts.encoding = WL_RXS_ENCODING_VHT;
- } else if (RSPEC_ISHE(rspec)) {
- sts.encoding = WL_RXS_ENCODING_HE;
- } else if (RSPEC_ISEHT(rspec)) {
- sts.encoding = WL_RXS_ENCODING_EHT;
- } else { /* MCS rate */
- sts.encoding = WL_RXS_ENCODING_HT;
- sts.preamble = (uint32)((D11HT_MMPLCPLen(rxh) != 0) ?
- WL_RXS_PREAMBLE_HT_MM : WL_RXS_PREAMBLE_HT_GF);
- }
-
- /* translate error code */
- if (D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxStatus1) & RXS_DECERR)
- sts.pkterror |= WL_RXS_DECRYPT_ERR;
- if (D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxStatus1) & RXS_FCSERR)
- sts.pkterror |= WL_RXS_CRC_ERROR;
-
- if (RXHDR_GET_PAD_PRES(rxh, corerev, corerev_minor)) {
- p += 2; len -= 2;
- }
-
- p += (hwrxoff + D11_PHY_RXPLCP_LEN(corerev));
- len -= (hwrxoff + D11_PHY_RXPLCP_LEN(corerev));
- return (wl_rxsts_to_rtap(&pkt_rxsts, p, len, pout, pad_req));
-}
-
-#ifndef MONITOR_DNGL_CONV
-/* Collect AMSDU subframe packets */
-static uint16
-wl_monitor_amsdu(monitor_info_t* info, monitor_pkt_info_t* pkt_info, wlc_d11rxhdr_t *wrxh,
- wlc_d11rxhdr_t *wrxh_last, void *pkt, uint16 len, void* pout, uint16* offset)
-{
- uint8 *p = pkt;
- uint8 hwrxoff = (pkt_info->marker >> 16) & 0xff;
- uint16 frame_len = 0;
- uint16 aggtype = (wrxh->rxhdr.lt80.RxStatus2 & RXS_AGGTYPE_MASK) >> RXS_AGGTYPE_SHIFT;
-
- switch (aggtype) {
- case RXS_AMSDU_FIRST:
- case RXS_AMSDU_N_ONE:
- /* Flush any previously collected */
- if (info->amsdu_len) {
- info->amsdu_len = 0;
- }
-
- info->headroom = MAX_RADIOTAP_SIZE - D11_PHY_RXPLCP_LEN(corerev) - hwrxoff;
- info->headroom -= (wrxh->rxhdr.lt80.RxStatus1 & RXS_PBPRES) ? 2 : 0;
-
- /* Save the new starting AMSDU subframe */
- info->amsdu_len = len;
- info->amsdu_pkt = (uint8*)pout + (info->headroom > 0 ?
- info->headroom : 0);
-
- memcpy(info->amsdu_pkt, p, len);
-
- if (aggtype == RXS_AMSDU_N_ONE) {
- /* all-in-one AMSDU subframe */
- frame_len = wl_d11rx_to_rxsts(info, pkt_info, wrxh, wrxh, p,
- len, info->amsdu_pkt - info->headroom, 0);
-
- *offset = ABS(info->headroom);
- frame_len += *offset;
-
- info->amsdu_len = 0;
- }
- break;
-
- case RXS_AMSDU_INTERMEDIATE:
- case RXS_AMSDU_LAST:
- default:
- /* Check for previously collected */
- if (info->amsdu_len) {
- /* Append next AMSDU subframe */
- p += hwrxoff; len -= hwrxoff;
-
- if (wrxh->rxhdr.lt80.RxStatus1 & RXS_PBPRES) {
- p += 2; len -= 2;
- }
-
- memcpy(info->amsdu_pkt + info->amsdu_len, p, len);
- info->amsdu_len += len;
-
- /* complete AMSDU frame */
- if (aggtype == RXS_AMSDU_LAST) {
- frame_len = wl_d11rx_to_rxsts(info, pkt_info, wrxh, wrxh,
- info->amsdu_pkt, info->amsdu_len,
- info->amsdu_pkt - info->headroom, 0);
-
- *offset = ABS(info->headroom);
- frame_len += *offset;
-
- info->amsdu_len = 0;
- }
- }
- break;
- }
-
- return frame_len;
-}
-#endif /* MONITOR_DNGL_CONV */
-
-uint16 bcmwifi_monitor_create(monitor_info_t** info)
-{
- *info = MALLOCZ(NULL, sizeof(struct monitor_info));
- if ((*info) == NULL) {
- return FALSE;
- }
-
- (*info)->d11_info = MALLOCZ(NULL, sizeof(struct d11_info));
- if ((*info)->d11_info == NULL) {
- goto fail;
- }
-
- return TRUE;
-
-fail:
- bcmwifi_monitor_delete(*info);
-
- return FALSE;
-}
-
-void
-bcmwifi_set_corerev_major(monitor_info_t* info, int8 corerev)
-{
- d11_info_t* d11i = info->d11_info;
- d11i->major_revid = corerev;
-}
-
-void
-bcmwifi_set_corerev_minor(monitor_info_t* info, int8 corerev)
-{
- d11_info_t* d11i = info->d11_info;
- d11i->minor_revid = corerev;
-}
-
-void
-bcmwifi_monitor_delete(monitor_info_t* info)
-{
- if (info == NULL) {
- return;
- }
-
- if (info->d11_info != NULL) {
- MFREE(NULL, info->d11_info, sizeof(struct d11_info));
- }
-
- MFREE(NULL, info, sizeof(struct monitor_info));
-}
-
-uint16
-bcmwifi_monitor(monitor_info_t* info, monitor_pkt_info_t* pkt_info, void *pkt, uint16 len,
- void* pout, uint16* offset, uint16 pad_req, void *wrxh_in, void *wrxh_last)
-{
- wlc_d11rxhdr_t *wrxh;
- int hdr_ext_offset = 0;
-
-#ifdef MONITOR_DNGL_CONV
- wrxh = (wlc_d11rxhdr_t *)wrxh_in;
- if (info == NULL) {
- return 0;
- }
-#else
-
-#ifdef BCM_MON_QDBM_RSSI
- hdr_ext_offset = WLC_SWRXHDR_EXT_LEN;
-#endif
- /* move beyond the extension, if any */
- pkt = (void *)((uint8 *)pkt + hdr_ext_offset);
- wrxh = (wlc_d11rxhdr_t *)pkt;
-
- if ((wrxh->rxhdr.lt80.RxStatus2 & htol16(RXS_AMSDU_MASK))) {
- /* Need to add support for AMSDU */
- return wl_monitor_amsdu(info, pkt_info, wrxh, wrxh_last, pkt, len, pout, offset);
- } else
-#endif /* NO MONITOR_DNGL_CONV */
- {
- info->amsdu_len = 0; /* reset amsdu */
- *offset = 0;
- return wl_d11rx_to_rxsts(info, pkt_info, wrxh, wrxh_last,
- pkt, len - hdr_ext_offset, pout, pad_req);
- }
-}
+++ /dev/null
-/*
- * Common [OS-independent] rate management
- * 802.11 Networking Adapter Device Driver.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#include <typedefs.h>
-#ifdef BCMDRIVER
-#include <osl.h>
-#else
-#include <assert.h>
-#ifndef ASSERT
-#define ASSERT(e) assert(e)
-#endif
-#ifndef ASSERT_FP
-#define ASSERT_FP(e) assert(e)
-#endif
-#endif /* BCMDRIVER */
-#include <802.11.h>
-#include <802.11ax.h>
-#include <bcmutils.h>
-
-#include <bcmwifi_rspec.h>
-#include <bcmwifi_rates.h>
-
-/* TODO: Consolidate rate utility functions from wlc_rate.c and bcmwifi_monitor.c
- * into here if they're shared by non wl layer as well...
- */
-
-/* ============================================ */
-/* Moved from wlc_rate.c */
-/* ============================================ */
-
-/* HE mcs info */
-struct ieee_80211_mcs_rate_info {
- uint8 constellation_bits;
- uint8 coding_q;
- uint8 coding_d;
- uint8 dcm_capable; /* 1 if dcm capable */
-};
-
-static const struct ieee_80211_mcs_rate_info wlc_mcs_info[] = {
- { 1, 1, 2, 1 }, /* MCS 0: MOD: BPSK, CR 1/2, dcm capable */
- { 2, 1, 2, 1 }, /* MCS 1: MOD: QPSK, CR 1/2, dcm capable */
- { 2, 3, 4, 0 }, /* MCS 2: MOD: QPSK, CR 3/4, NOT dcm capable */
- { 4, 1, 2, 1 }, /* MCS 3: MOD: 16QAM, CR 1/2, dcm capable */
- { 4, 3, 4, 1 }, /* MCS 4: MOD: 16QAM, CR 3/4, dcm capable */
- { 6, 2, 3, 0 }, /* MCS 5: MOD: 64QAM, CR 2/3, NOT dcm capable */
- { 6, 3, 4, 0 }, /* MCS 6: MOD: 64QAM, CR 3/4, NOT dcm capable */
- { 6, 5, 6, 0 }, /* MCS 7: MOD: 64QAM, CR 5/6, NOT dcm capable */
- { 8, 3, 4, 0 }, /* MCS 8: MOD: 256QAM, CR 3/4, NOT dcm capable */
- { 8, 5, 6, 0 }, /* MCS 9: MOD: 256QAM, CR 5/6, NOT dcm capable */
- { 10, 3, 4, 0 }, /* MCS 10: MOD: 1024QAM, CR 3/4, NOT dcm capable */
- { 10, 5, 6, 0 }, /* MCS 11: MOD: 1024QAM, CR 5/6, NOT dcm capable */
-#ifdef WL11BE
- /* TODO: for now EHT shares this table with HE,
- * create a new table if needed once we know more
- * about EHT rate calculation...
- */
- { 12, 3, 4, 0 }, /* MCS 12: MOD: 4096QAM, CR 3/4, NOT dcm capable */
- { 12, 5, 6, 0 }, /* MCS 13: MOD: 4096QAM, CR 5/6, NOT dcm capable */
-#endif
-};
-
-/* Nsd values Draft0.4 Table 26.63 onwards */
-static const uint wlc_he_nsd[] = {
- 234, /* BW20 */
- 468, /* BW40 */
- 980, /* BW80 */
- 1960, /* BW160 */
-#ifdef WL11BE
- /* TODO: for now EHT shares this table with HE,
- * create a new table if needed once we know more
- * about EHT rate calculation...
- */
- 2940, /* BW240 */
- 3920 /* BW320 */
-#endif
-};
-
-/* Nsd values Draft3.3 Table 28-15 */
-static const uint wlc_he_ru_nsd[] = {
- 24, /* 26T */
- 48, /* 52T */
- 102, /* 106T */
- 234, /* 242T/BW20 */
- 468, /* 484T/BW40 */
- 980, /* 996T/BW80 */
- 1960, /* 2*996T/BW160 */
-#ifdef WL11BE
- /* TODO: for now EHT shares this table with HE,
- * create a new table if needed once we know more
- * about EHT rate calculation...
- */
- 2940, /* 3*996T/BW240 */
- 3920 /* 4*996T/BW320 */
-#endif
-};
-
-#define HE_RU_TO_NSD(ru_idx) \
- (ru_idx < ARRAYSIZE(wlc_he_ru_nsd)) ? \
- wlc_he_ru_nsd[ru_idx] : 0
-
-/* sym_len = 12.8 us. For calculation purpose, *10 */
-#define HE_SYM_LEN_FACTOR (128)
-
-/* GI values = 0.8 , 1.6 or 3.2 us. For calculation purpose, *10 */
-#define HE_GI_800us_FACTOR (8)
-#define HE_GI_1600us_FACTOR (16)
-#define HE_GI_3200us_FACTOR (32)
-
-/* To avoid ROM invalidation use the old macro as is... */
-#ifdef WL11BE
-#define HE_BW_TO_NSD(bwi) \
- ((bwi) > 0u && (bwi) <= ARRAYSIZE(wlc_he_nsd)) ? \
- wlc_he_nsd[(bwi) - 1u] : 0u
-#else
-#define HE_BW_TO_NSD(bwi) \
- ((bwi) > 0 && ((bwi) << WL_RSPEC_BW_SHIFT) <= WL_RSPEC_BW_160MHZ) ? \
- wlc_he_nsd[(bwi)-1] : 0
-#endif /* WL11BE */
-
-#define ksps 250 /* kilo symbols per sec, 4 us sym */
-
-#ifdef WL11BE
-/* Table "wlc_nsd" is derived from HT and VHT #defines below, but extended for HE
- * for rate calculation purpose at a given NSS and bandwidth combination.
- *
- * It should and can only be used in where it wants to know the relative rate in kbps
- * for a different NSS and bandwidth combination at a given mcs e.g. in fallback rate
- * search. It shouldn not and can not be used in where it calculates the absolute rate
- * i.e. the result doesn't agree with what the spec says otherwise.
- *
- * See Std 802.11-2016 "Table 21-61 VHT-MCSs for optional 160 MHz and 80+80 MHz, NSS = 8"
- * for VHT, and P802.11ax/D6.0 "Table 27-111 HE-MCSs for 2x996-tone RU, NSS = 8" for HE,
- * for 160Mhz bandwidth for resulting rate comparison.
- *
- * It's again extended for EHT 240/320Mhz bandwidth, for the same purpose.
- */
-static const uint16 wlc_nsd[] = {
- 52, /* 20MHz */
- 108, /* 40MHz */
- 234, /* 80Mhz */
- 468, /* 160MHz */
- 702, /* 240MHz */
- 936, /* 320MHz */
-};
-
-#define BW_TO_NSD(bwi) \
- ((bwi) > 0u && (bwi) <= ARRAYSIZE(wlc_nsd)) ? \
- wlc_nsd[(bwi) - 1u] : 0u
-
-static uint
-wf_nsd2ndbps(uint mcs, uint nss, uint nsd, bool dcm)
-{
- uint Ndbps;
-
- /* multiply number of spatial streams,
- * bits per number from the constellation,
- * and coding quotient
- */
- Ndbps = nsd * nss *
- wlc_mcs_info[mcs].coding_q * wlc_mcs_info[mcs].constellation_bits;
-
- /* adjust for the coding rate divisor */
- Ndbps = Ndbps / wlc_mcs_info[mcs].coding_d;
-
- /* take care of dcm: dcm divides R by 2. If not dcm mcs, ignore */
- if (dcm) {
- if (wlc_mcs_info[mcs].dcm_capable) {
- Ndbps >>= 1u;
- }
- }
-
- return Ndbps;
-}
-#else
-/* for HT and VHT? */
-#define Nsd_20MHz 52
-#define Nsd_40MHz 108
-#define Nsd_80MHz 234
-#define Nsd_160MHz 468
-#endif /* WL11BE */
-
-uint
-wf_he_mcs_to_Ndbps(uint mcs, uint nss, uint bw, bool dcm)
-{
- uint Nsd;
- uint Ndbps;
-
- /* find the number of complex numbers per symbol */
- Nsd = HE_BW_TO_NSD(bw >> WL_RSPEC_BW_SHIFT);
-
-#ifdef WL11BE
- Ndbps = wf_nsd2ndbps(mcs, nss, Nsd, dcm);
-#else
- /* multiply number of spatial streams,
- * bits per number from the constellation,
- * and coding quotient
- */
- Ndbps = Nsd * nss *
- wlc_mcs_info[mcs].coding_q * wlc_mcs_info[mcs].constellation_bits;
-
- /* adjust for the coding rate divisor */
- Ndbps = Ndbps / wlc_mcs_info[mcs].coding_d;
-
- /* take care of dcm: dcm divides R by 2. If not dcm mcs, ignore */
- if (dcm) {
- if (wlc_mcs_info[mcs].dcm_capable) {
- Ndbps >>= 1;
- }
- }
-#endif /* WL11BE */
-
- return Ndbps;
-}
-
-uint32
-wf_he_mcs_ru_to_ndbps(uint8 mcs, uint8 nss, bool dcm, uint8 ru_index)
-{
- uint32 nsd;
- uint32 ndbps;
-
- /* find the number of complex numbers per symbol */
- nsd = HE_RU_TO_NSD(ru_index);
-
-#ifdef WL11BE
- ndbps = wf_nsd2ndbps(mcs, nss, nsd, dcm);
-#else
- /* multiply number of spatial streams,
- * bits per number from the constellation,
- * and coding quotient
- * Ndbps = Nss x Nsd x (Nbpscs x R) x (DCM/2)
- */
- ndbps = nsd * nss *
- wlc_mcs_info[mcs].coding_q * wlc_mcs_info[mcs].constellation_bits;
-
- /* adjust for the coding rate divisor */
- ndbps = ndbps / wlc_mcs_info[mcs].coding_d;
-
- /* take care of dcm: dcm divides R by 2. If not dcm mcs, ignore */
- if (dcm && wlc_mcs_info[mcs].dcm_capable) {
- ndbps >>= 1;
- }
-#endif /* WL11BE */
- return ndbps;
-}
-
-/**
- * Returns the rate in [Kbps] units for a caller supplied MCS/bandwidth/Nss/Sgi/dcm combination.
- * 'mcs' : a *single* spatial stream MCS (11ax)
- * formula as per http:
- * WLAN&preview=/323036249/344457953/11ax_rate_table.xlsx
- * Symbol length = 12.8 usec [given as sym_len/10 below]
- * GI value = 0.8 or 1.6 or 3.2 usec [given as GI_value/10 below]
- * rate (Kbps) = (Nsd * Nbpscs * nss * (coding_q/coding_d) * 1000) / ((sym_len/10) + (GI_value/10))
- * Note that, for calculation purpose, following is used. [to be careful with overflows]
- * rate (Kbps) = (Nsd * Nbpscs * nss * (coding_q/coding_d) * 1000) / ((sym_len + GI_value) / 10)
- * rate (Kbps) = (Nsd * Nbpscs * nss * (coding_q/coding_d) * 1000) / (sym_len + GI_value) * 10
- */
-uint
-wf_he_mcs_to_rate(uint mcs, uint nss, uint bw, uint gi, bool dcm)
-{
- uint rate;
- uint rate_deno;
-
- rate = HE_BW_TO_NSD(bw >> WL_RSPEC_BW_SHIFT);
-
-#ifdef WL11BE
- rate = wf_nsd2ndbps(mcs, nss, rate, dcm);
-#else
- /* Nbpscs: multiply by bits per number from the constellation in use */
- rate = rate * wlc_mcs_info[mcs].constellation_bits;
-
- /* Nss: adjust for the number of spatial streams */
- rate = rate * nss;
-
- /* R: adjust for the coding rate given as a quotient and divisor */
- rate = (rate * wlc_mcs_info[mcs].coding_q) / wlc_mcs_info[mcs].coding_d;
-
- /* take care of dcm: dcm divides R by 2. If not dcm mcs, ignore */
- if (dcm) {
- if (wlc_mcs_info[mcs].dcm_capable) {
- rate >>= 1;
- }
- }
-#endif /* WL11BE */
-
- /* add sym len factor */
- rate_deno = HE_SYM_LEN_FACTOR;
-
- /* get GI for denominator */
- if (HE_IS_GI_3_2us(gi)) {
- rate_deno += HE_GI_3200us_FACTOR;
- } else if (HE_IS_GI_1_6us(gi)) {
- rate_deno += HE_GI_1600us_FACTOR;
- } else {
- /* assuming HE_GI_0_8us */
- rate_deno += HE_GI_800us_FACTOR;
- }
-
- /* as per above formula */
- rate *= 1000; /* factor of 10. *100 to accommodate 2 places */
- rate /= rate_deno;
- rate *= 10; /* *100 was already done above. Splitting is done to avoid overflow. */
-
- return rate;
-}
-
-uint
-wf_mcs_to_Ndbps(uint mcs, uint nss, uint bw)
-{
- uint Nsd;
- uint Ndbps;
-
- /* This calculation works for 11n HT and 11ac VHT if the HT mcs values
- * are decomposed into a base MCS = MCS % 8, and Nss = 1 + MCS / 8.
- * That is, HT MCS 23 is a base MCS = 7, Nss = 3
- */
-
- /* find the number of complex numbers per symbol */
-#ifdef WL11BE
- Nsd = BW_TO_NSD(bw >> WL_RSPEC_BW_SHIFT);
-
- Ndbps = wf_nsd2ndbps(mcs, nss, Nsd, FALSE);
-#else
- if (bw == WL_RSPEC_BW_20MHZ) {
- Nsd = Nsd_20MHz;
- } else if (bw == WL_RSPEC_BW_40MHZ) {
- Nsd = Nsd_40MHz;
- } else if (bw == WL_RSPEC_BW_80MHZ) {
- Nsd = Nsd_80MHz;
- } else if (bw == WL_RSPEC_BW_160MHZ) {
- Nsd = Nsd_160MHz;
- } else {
- Nsd = 0;
- }
-
- /* multiply number of spatial streams,
- * bits per number from the constellation,
- * and coding quotient
- */
- Ndbps = Nsd * nss *
- wlc_mcs_info[mcs].coding_q * wlc_mcs_info[mcs].constellation_bits;
-
- /* adjust for the coding rate divisor */
- Ndbps = Ndbps / wlc_mcs_info[mcs].coding_d;
-#endif /* WL11BE */
-
- return Ndbps;
-}
-
-/**
- * Returns the rate in [Kbps] units for a caller supplied MCS/bandwidth/Nss/Sgi combination.
- * 'mcs' : a *single* spatial stream MCS (11n or 11ac)
- */
-uint
-wf_mcs_to_rate(uint mcs, uint nss, uint bw, int sgi)
-{
- uint rate;
-
- if (mcs == 32) {
- /* just return fixed values for mcs32 instead of trying to parametrize */
- rate = (sgi == 0) ? 6000 : 6778;
- } else {
- /* This calculation works for 11n HT, 11ac VHT and 11ax HE if the HT mcs values
- * are decomposed into a base MCS = MCS % 8, and Nss = 1 + MCS / 8.
- * That is, HT MCS 23 is a base MCS = 7, Nss = 3
- */
-
-#if defined(WLPROPRIETARY_11N_RATES)
- switch (mcs) {
- case 87:
- mcs = 8; /* MCS 8: MOD: 256QAM, CR 3/4 */
- break;
- case 88:
- mcs = 9; /* MCS 9: MOD: 256QAM, CR 5/6 */
- break;
- default:
- break;
- }
-#endif /* WLPROPRIETARY_11N_RATES */
-
-#ifdef WL11BE
- rate = wf_mcs_to_Ndbps(mcs, nss, bw);
-#else
- /* find the number of complex numbers per symbol */
- if (RSPEC_IS20MHZ(bw)) {
- /* 4360 TODO: eliminate Phy const in rspec bw, then just compare
- * as in 80 and 160 case below instead of RSPEC_IS20MHZ(bw)
- */
- rate = Nsd_20MHz;
- } else if (RSPEC_IS40MHZ(bw)) {
- /* 4360 TODO: eliminate Phy const in rspec bw, then just compare
- * as in 80 and 160 case below instead of RSPEC_IS40MHZ(bw)
- */
- rate = Nsd_40MHz;
- } else if (bw == WL_RSPEC_BW_80MHZ) {
- rate = Nsd_80MHz;
- } else if (bw == WL_RSPEC_BW_160MHZ) {
- rate = Nsd_160MHz;
- } else {
- rate = 0;
- }
-
- /* multiply by bits per number from the constellation in use */
- rate = rate * wlc_mcs_info[mcs].constellation_bits;
-
- /* adjust for the number of spatial streams */
- rate = rate * nss;
-
- /* adjust for the coding rate given as a quotient and divisor */
- rate = (rate * wlc_mcs_info[mcs].coding_q) / wlc_mcs_info[mcs].coding_d;
-#endif /* WL11BE */
-
- /* multiply by Kilo symbols per sec to get Kbps */
- rate = rate * ksps;
-
- /* adjust the symbols per sec for SGI
- * symbol duration is 4 us without SGI, and 3.6 us with SGI,
- * so ratio is 10 / 9
- */
- if (sgi) {
- /* add 4 for rounding of division by 9 */
- rate = ((rate * 10) + 4) / 9;
- }
- }
-
- return rate;
-} /* wf_mcs_to_rate */
-
-/* This function needs update to handle MU frame PLCP as well (MCS is conveyed via VHT-SIGB
- * field in case of MU frames). Currently this support needs to be added in uCode to communicate
- * MCS information for an MU frame
- *
- * For VHT frame:
- * bit 0-3 mcs index
- * bit 6-4 nsts for VHT
- * bit 7: 1 for VHT
- * Note: bit 7 is used to indicate to the rate sel the mcs is a non HT mcs!
- *
- * Essentially it's the NSS:MCS portions of the rspec
- */
-uint8
-wf_vht_plcp_to_rate(uint8 *plcp)
-{
- uint8 rate, gid;
- uint nss;
- uint32 plcp0 = plcp[0] + (plcp[1] << 8); /* don't need plcp[2] */
-
- gid = (plcp0 & VHT_SIGA1_GID_MASK) >> VHT_SIGA1_GID_SHIFT;
- if (gid > VHT_SIGA1_GID_TO_AP && gid < VHT_SIGA1_GID_NOT_TO_AP) {
- /* for MU packet we hacked Signal Tail field in VHT-SIG-A2 to save nss and mcs,
- * copy from murate in d11 rx header.
- * nss = bit 18:19 (for 11ac 2 bits to indicate maximum 4 nss)
- * mcs = 20:23
- */
- rate = (plcp[5] & 0xF0) >> 4;
- nss = ((plcp[5] & 0x0C) >> 2) + 1;
- } else {
- rate = (plcp[3] >> VHT_SIGA2_MCS_SHIFT);
- nss = ((plcp0 & VHT_SIGA1_NSTS_SHIFT_MASK_USER0) >>
- VHT_SIGA1_NSTS_SHIFT) + 1;
- if (plcp0 & VHT_SIGA1_STBC)
- nss = nss >> 1;
- }
- rate |= ((nss << WL_RSPEC_VHT_NSS_SHIFT) | WF_NON_HT_MCS);
-
- return rate;
-}
-
-/**
- * Function for computing NSS:MCS from HE SU PLCP or
- * MCS:LTF-GI from HE MU PLCP
- *
- * based on rev3.10 :
- * https://docs.google.com/spreadsheets/d/
- * 1eP6ZCRrtnF924ds1R-XmbcH0IdQ0WNJpS1-FHmWeb9g/edit#gid=1492656555
- *
- * For HE SU frame:
- * bit 0-3 mcs index
- * bit 6-4 nsts for HE
- * bit 7: 1 for HE
- * Note: bit 7 is used to indicate to the rate sel the mcs is a non HT mcs!
- * Essentially it's the NSS:MCS portions of the rspec
- *
- * For HE MU frame:
- * bit 0-3 mcs index
- * bit 4-5 LTF-GI value
- * bit 6 STBC
- * Essentially it's the MCS and LTF-GI portion of the rspec
- */
-/* Macros to be used for calculating rate from PLCP */
-#define HE_SU_PLCP2RATE_MCS_MASK 0x0F
-#define HE_SU_PLCP2RATE_MCS_SHIFT 0
-#define HE_SU_PLCP2RATE_NSS_MASK 0x70
-#define HE_SU_PLCP2RATE_NSS_SHIFT 4
-#define HE_MU_PLCP2RATE_LTF_GI_MASK 0x30
-#define HE_MU_PLCP2RATE_LTF_GI_SHIFT 4
-#define HE_MU_PLCP2RATE_STBC_MASK 0x40
-#define HE_MU_PLCP2RATE_STBC_SHIFT 6
-
-uint8
-wf_he_plcp_to_rate(uint8 *plcp, bool is_mu)
-{
- uint8 rate = 0;
- uint8 nss = 0;
- uint32 plcp0 = 0;
- uint32 plcp1 = 0;
- uint8 he_ltf_gi;
- uint8 stbc;
-
- ASSERT(plcp);
-
- BCM_REFERENCE(nss);
- BCM_REFERENCE(he_ltf_gi);
-
- plcp0 = ((plcp[3] << 24) | (plcp[2] << 16) | (plcp[1] << 8) | plcp[0]);
- plcp1 = ((plcp[5] << 8) | plcp[4]);
-
- if (!is_mu) {
- /* For SU frames return rate in MCS:NSS format */
- rate = ((plcp0 & HE_SU_RE_SIGA_MCS_MASK) >> HE_SU_RE_SIGA_MCS_SHIFT);
- nss = ((plcp0 & HE_SU_RE_SIGA_NSTS_MASK) >> HE_SU_RE_SIGA_NSTS_SHIFT) + 1;
- rate |= ((nss << HE_SU_PLCP2RATE_NSS_SHIFT) | WF_NON_HT_MCS);
- } else {
- /* For MU frames return rate in MCS:LTF-GI format */
- rate = (plcp0 & HE_MU_SIGA_SIGB_MCS_MASK) >> HE_MU_SIGA_SIGB_MCS_SHIFT;
- he_ltf_gi = (plcp0 & HE_MU_SIGA_GI_LTF_MASK) >> HE_MU_SIGA_GI_LTF_SHIFT;
- stbc = (plcp1 & HE_MU_SIGA_STBC_MASK) >> HE_MU_SIGA_STBC_SHIFT;
-
- /* LTF-GI shall take the same position as NSS */
- rate |= (he_ltf_gi << HE_MU_PLCP2RATE_LTF_GI_SHIFT);
-
- /* STBC needs to be filled in bit 6 */
- rate |= (stbc << HE_MU_PLCP2RATE_STBC_SHIFT);
- }
-
- return rate;
-}
-
-/**
- * Function for computing NSS:MCS from EHT SU PLCP or
- * MCS:LTF-GI from EHT MU PLCP
- *
- * TODO: add link to the HW spec.
- * FIXME: do we really need to support mu?
- */
-uint8
-wf_eht_plcp_to_rate(uint8 *plcp, bool is_mu)
-{
- BCM_REFERENCE(plcp);
- BCM_REFERENCE(is_mu);
- ASSERT(!"wf_eht_plcp_to_rate: not implemented!");
- return 0;
-}
-
-/* ============================================ */
-/* Moved from wlc_rate_def.c */
-/* ============================================ */
-
-/**
- * Some functions require a single stream MCS as an input parameter. Given an MCS, this function
- * returns the single spatial stream MCS equivalent.
- */
-uint8
-wf_get_single_stream_mcs(uint mcs)
-{
- if (mcs < 32) {
- return mcs % 8;
- }
- switch (mcs) {
- case 32:
- return 32;
- case 87:
- case 99:
- case 101:
- return 87; /* MCS 87: SS 1, MOD: 256QAM, CR 3/4 */
- default:
- return 88; /* MCS 88: SS 1, MOD: 256QAM, CR 5/6 */
- }
-}
-
-/* ============================================ */
-/* Moved from wlc_phy_iovar.c */
-/* ============================================ */
-
-const uint8 plcp_ofdm_rate_tbl[] = {
- DOT11_RATE_48M, /* 8: 48Mbps */
- DOT11_RATE_24M, /* 9: 24Mbps */
- DOT11_RATE_12M, /* A: 12Mbps */
- DOT11_RATE_6M, /* B: 6Mbps */
- DOT11_RATE_54M, /* C: 54Mbps */
- DOT11_RATE_36M, /* D: 36Mbps */
- DOT11_RATE_18M, /* E: 18Mbps */
- DOT11_RATE_9M /* F: 9Mbps */
-};
+++ /dev/null
-/*
- * Common [OS-independent] rate management
- * 802.11 Networking Adapter Device Driver.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#include <typedefs.h>
-#include <osl.h>
-#include <d11.h>
-#include <802.11ax.h>
-
-#include <bcmwifi_rspec.h>
-#include <bcmwifi_rates.h>
-
-/* TODO: Consolidate rspec utility functions from wlc_rate.c and bcmwifi_monitor.c
- * into here if they're shared by non wl layer as well...
- */
-
-/* ============================================ */
-/* Moved from wlc_rate.c */
-/* ============================================ */
-
-/**
- * Returns the rate in [Kbps] units.
- */
-static uint
-wf_he_rspec_to_rate(ratespec_t rspec, uint max_mcs, uint max_nss)
-{
- uint mcs = (rspec & WL_RSPEC_HE_MCS_MASK);
- uint nss = (rspec & WL_RSPEC_HE_NSS_MASK) >> WL_RSPEC_HE_NSS_SHIFT;
- bool dcm = (rspec & WL_RSPEC_DCM) != 0;
- uint bw = RSPEC_BW(rspec);
- uint gi = RSPEC_HE_LTF_GI(rspec);
-
- ASSERT(mcs <= max_mcs);
- ASSERT(nss <= max_nss);
-
- if (mcs > max_mcs) {
- return 0;
- }
- BCM_REFERENCE(max_nss);
-
- return wf_he_mcs_to_rate(mcs, nss, bw, gi, dcm);
-} /* wf_he_rspec_to_rate */
-
-/* take a well formed ratespec_t arg and return phy rate in [Kbps] units.
- * 'rsel' indicates if the call comes from rate selection.
- */
-static uint
-_wf_rspec_to_rate(ratespec_t rspec, bool rsel)
-{
- uint rate = (uint)(-1);
-
- if (RSPEC_ISLEGACY(rspec)) {
- rate = 500 * RSPEC2RATE(rspec);
- } else if (RSPEC_ISHT(rspec)) {
- uint mcs = (rspec & WL_RSPEC_HT_MCS_MASK);
-
- ASSERT_FP(mcs <= 32 || IS_PROPRIETARY_11N_MCS(mcs));
-
- if (mcs == 32) {
- rate = wf_mcs_to_rate(mcs, 1, WL_RSPEC_BW_40MHZ, RSPEC_ISSGI(rspec));
- } else {
-#if defined(WLPROPRIETARY_11N_RATES)
- uint nss = GET_11N_MCS_NSS(mcs);
- mcs = wf_get_single_stream_mcs(mcs);
-#else /* this ifdef prevents ROM abandons */
- uint nss = 1 + (mcs / 8);
- mcs = mcs % 8;
-#endif /* WLPROPRIETARY_11N_RATES */
-
- rate = wf_mcs_to_rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
- }
- } else if (RSPEC_ISVHT(rspec)) {
- uint mcs = (rspec & WL_RSPEC_VHT_MCS_MASK);
- uint nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
-
- if (rsel) {
- rate = wf_mcs_to_rate(mcs, nss, RSPEC_BW(rspec), 0);
- } else {
- ASSERT_FP(mcs <= WLC_MAX_VHT_MCS);
- ASSERT_FP(nss <= 8);
-
- rate = wf_mcs_to_rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
- }
- } else if (RSPEC_ISHE(rspec)) {
- rate = wf_he_rspec_to_rate(rspec, WLC_MAX_HE_MCS, 8);
- } else if (RSPEC_ISEHT(rspec)) {
- rate = wf_he_rspec_to_rate(rspec, WLC_MAX_EHT_MCS, 16);
- } else {
- ASSERT(0);
- }
-
- return (rate == 0) ? (uint)(-1) : rate;
-}
-
-/* take a well formed ratespec_t 'rspec' and return phy rate in [Kbps] units */
-uint
-wf_rspec_to_rate(ratespec_t rspec)
-{
- return _wf_rspec_to_rate(rspec, FALSE);
-}
-
-/* take a well formed ratespec_t 'rspec' and return phy rate in [Kbps] units,
- * FOR RATE SELECTION ONLY, WHICH USES LEGACY, HT, AND VHT RATES, AND VHT MCS
- * COULD BE BIGGER THAN WLC_MAX_VHT_MCS!
- */
-uint
-wf_rspec_to_rate_rsel(ratespec_t rspec)
-{
- return _wf_rspec_to_rate(rspec, TRUE);
-}
-
-#ifdef BCMDBG
-/* Return the rate in 500Kbps units if the rspec is legacy rate, assert otherwise */
-uint
-wf_rspec_to_rate_legacy(ratespec_t rspec)
-{
- ASSERT(RSPEC_ISLEGACY(rspec));
-
- return rspec & WL_RSPEC_LEGACY_RATE_MASK;
-}
-#endif
-
-/**
- * Function for computing RSPEC from EHT PLCP
- *
- * TODO: add link to the HW spec.
- */
-ratespec_t
-wf_eht_plcp_to_rspec(uint8 *plcp)
-{
- ASSERT(!"wf_eht_plcp_to_rspec: not implemented!");
- return 0;
-}
-
-/**
- * Function for computing RSPEC from HE PLCP
- *
- * based on rev3.10 :
- * https://docs.google.com/spreadsheets/d/
- * 1eP6ZCRrtnF924ds1R-XmbcH0IdQ0WNJpS1-FHmWeb9g/edit#gid=1492656555
- */
-ratespec_t
-wf_he_plcp_to_rspec(uint8 *plcp)
-{
- uint8 rate;
- uint8 nss;
- uint8 bw;
- uint8 gi;
- ratespec_t rspec;
-
- /* HE plcp - 6 B */
- uint32 plcp0;
- uint16 plcp1;
-
- ASSERT(plcp);
-
- plcp0 = ((plcp[3] << 24) | (plcp[2] << 16) | (plcp[1] << 8) | plcp[0]);
- plcp1 = ((plcp[5] << 8) | plcp[4]);
-
- /* TBD: only SU supported now */
- rate = (plcp0 & HE_SU_RE_SIGA_MCS_MASK) >> HE_SU_RE_SIGA_MCS_SHIFT;
- /* PLCP contains (NSTS - 1) while RSPEC stores NSTS */
- nss = ((plcp0 & HE_SU_RE_SIGA_NSTS_MASK) >> HE_SU_RE_SIGA_NSTS_SHIFT) + 1;
- rspec = HE_RSPEC(rate, nss);
-
- /* GI info comes from CP/LTF */
- gi = (plcp0 & HE_SU_RE_SIGA_GI_LTF_MASK) >> HE_SU_RE_SIGA_GI_LTF_SHIFT;
- rspec |= HE_GI_TO_RSPEC(gi);
-
- /* b19-b20 of plcp indicate bandwidth in the format (2-bit):
- * 0 for 20M, 1 for 40M, 2 for 80M, and 3 for 80p80/160M
- * SW store this BW in rspec format (3-bit):
- * 1 for 20M, 2 for 40M, 3 for 80M, and 4 for 80p80/160M
- */
- bw = ((plcp0 & HE_SU_SIGA_BW_MASK) >> HE_SU_SIGA_BW_SHIFT) + 1;
- rspec |= (bw << WL_RSPEC_BW_SHIFT);
-
- if (plcp1 & HE_SU_RE_SIGA_BEAMFORM_MASK)
- rspec |= WL_RSPEC_TXBF;
- if (plcp1 & HE_SU_RE_SIGA_CODING_MASK)
- rspec |= WL_RSPEC_LDPC;
- if (plcp1 & HE_SU_RE_SIGA_STBC_MASK)
- rspec |= WL_RSPEC_STBC;
- if (plcp0 & HE_SU_RE_SIGA_DCM_MASK)
- rspec |= WL_RSPEC_DCM;
-
- return rspec;
-}
-
-ratespec_t
-wf_vht_plcp_to_rspec(uint8 *plcp)
-{
- uint8 rate;
- uint vht_sig_a1, vht_sig_a2;
- ratespec_t rspec;
-
- ASSERT(plcp);
-
- rate = wf_vht_plcp_to_rate(plcp) & ~WF_NON_HT_MCS;
-
- vht_sig_a1 = plcp[0] | (plcp[1] << 8);
- vht_sig_a2 = plcp[3] | (plcp[4] << 8);
-
- rspec = VHT_RSPEC((rate & WL_RSPEC_VHT_MCS_MASK),
- (rate >> WL_RSPEC_VHT_NSS_SHIFT));
-#if ((((VHT_SIGA1_20MHZ_VAL + 1) << WL_RSPEC_BW_SHIFT) != WL_RSPEC_BW_20MHZ) || \
- (((VHT_SIGA1_40MHZ_VAL + 1) << WL_RSPEC_BW_SHIFT) != WL_RSPEC_BW_40MHZ) || \
- (((VHT_SIGA1_80MHZ_VAL + 1) << WL_RSPEC_BW_SHIFT) != WL_RSPEC_BW_80MHZ) || \
- (((VHT_SIGA1_160MHZ_VAL + 1) << WL_RSPEC_BW_SHIFT) != WL_RSPEC_BW_160MHZ))
-#error "VHT SIGA BW mapping to RSPEC BW needs correction"
-#endif
- rspec |= ((vht_sig_a1 & VHT_SIGA1_160MHZ_VAL) + 1) << WL_RSPEC_BW_SHIFT;
- if (vht_sig_a1 & VHT_SIGA1_STBC)
- rspec |= WL_RSPEC_STBC;
- if (vht_sig_a2 & VHT_SIGA2_GI_SHORT)
- rspec |= WL_RSPEC_SGI;
- if (vht_sig_a2 & VHT_SIGA2_CODING_LDPC)
- rspec |= WL_RSPEC_LDPC;
-
- return rspec;
-}
-
-ratespec_t
-wf_ht_plcp_to_rspec(uint8 *plcp)
-{
- return HT_RSPEC(plcp[0] & MIMO_PLCP_MCS_MASK);
-}
-
-/* ============================================ */
-/* Moved from wlc_rate_def.c */
-/* ============================================ */
-
-/**
- * Rate info per rate: tells for *pre* 802.11n rates whether a given rate is OFDM or not and its
- * phy_rate value. Table index is a rate in [500Kbps] units, from 0 to 54Mbps.
- * Contents of a table element:
- * d[7] : 1=OFDM rate, 0=DSSS/CCK rate
- * d[3:0] if DSSS/CCK rate:
- * index into the 'M_RATE_TABLE_B' table maintained by ucode in shm
- * d[3:0] if OFDM rate: encode rate per 802.11a-1999 sec 17.3.4.1, with lsb transmitted first.
- * index into the 'M_RATE_TABLE_A' table maintained by ucode in shm
- */
-/* Note: make this table 128 elements so the result of (rspec & 0x7f) can be safely
- * used as the index into this table...
- */
-const uint8 rate_info[128] = {
- /* 0 1 2 3 4 5 6 7 8 9 */
-/* 0 */ 0x00, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 10 */ 0x00, 0x37, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x00,
-/* 20 */ 0x00, 0x00, 0x6e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00,
-/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00,
-/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 70 */ 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00,
-/* 100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c,
-/* ------------- guard ------------ */ 0x00,
-/* 110 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 120 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
+++ /dev/null
-/*
- * bcmwpa.c - shared WPA-related functions
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-/* include wl driver config file if this file is compiled for driver */
-#ifdef BCMDRIVER
-#include <osl.h>
-/* HACK: this case for external supplicant use */
-#else
-#include <string.h>
-#if defined(BCMEXTSUP)
-#include <bcm_osl.h>
-#else
-#ifndef ASSERT
-#define ASSERT(exp)
-#endif
-#endif /* BCMEXTSUP */
-#endif /* BCMDRIVER */
-
-#include <ethernet.h>
-#include <eapol.h>
-#include <802.11.h>
-#include <wpa.h>
-#include <802.11r.h>
-
-#include <bcmutils.h>
-#include <bcmendian.h>
-#include <bcmwpa.h>
-#include <aeskeywrap.h>
-
-#include <bcmstdlib_s.h>
-
-#include <wlioctl.h>
-
-#include <bcmutils.h>
-#include <bcmwpa.h>
-#ifdef WL_OCV
-#include <bcm_ocv.h>
-#endif /* WL_OCV */
-
-#if defined(BCMSUP_PSK) || defined(WLFBT) || defined(BCMAUTH_PSK) || \
- defined(WL_OKC) || defined(WLTDLS) || defined(GTKOE) || defined(WLHOSTFBT)
-#ifdef WLHOSTFBT
-#include <string.h>
-#endif
-#endif /* defined(BCMSUP_PSK) || defined(WLFBT) || defined(BCMAUTH_PSK) ||
- * defined(WL_OKC) || defined(WLTDLS) || defined(GTKOE) || defined(WLHOSTFBT)
- */
-
-/* prefix strings */
-#define PMK_NAME_PFX "PMK Name"
-#define FT_PTK_PFX "FT-PTK"
-#define FT_R0_PFX "FT-R0"
-#define FT_R0N_PFX "FT-R0N"
-#define FT_R1_PFX "FT-R1"
-#define FT_R1N_PFX "FT-R1N"
-#define WPA_PTK_PFX "Pairwise key expansion"
-#define TDLS_PMK_PFX "TDLS PMK"
-/* end prefix strings */
-
-#ifndef BIT
-#define BIT(x) (1 << (x))
-#endif
-
-#define PRF_PREFIXES_NUM 5u
-
-typedef struct key_length_entry {
- uint8 suite;
- uint8 len;
-} key_length_entry_t;
-
-/* EAPOL key(PMK/KCK/KEK/TK) length lookup tables */
-static const key_length_entry_t eapol_pmk_len[] = {
- {RSN_AKM_SUITEB_SHA384_1X, EAPOL_WPA_PMK_SHA384_LEN},
- {RSN_AKM_FBT_SHA384_1X, EAPOL_WPA_PMK_SHA384_LEN},
- {RSN_AKM_FBT_SHA384_PSK, EAPOL_WPA_PMK_SHA384_LEN},
- {0u, EAPOL_WPA_PMK_DEFAULT_LEN} /* default */
-};
-
-static const key_length_entry_t eapol_kck_mic_len[] = {
- {RSN_AKM_SUITEB_SHA384_1X, EAPOL_WPA_KCK_MIC_SHA384_LEN},
- {RSN_AKM_FILS_SHA256, 0u},
- {RSN_AKM_FILS_SHA384, 0u},
- {RSN_AKM_FBT_SHA256_FILS, EAPOL_WPA_KCK_MIC_DEFAULT_LEN},
- {RSN_AKM_FBT_SHA384_FILS, EAPOL_WPA_KCK2_SHA384_LEN},
- {RSN_AKM_OWE, EAPOL_WPA_KCK_MIC_DEFAULT_LEN},
- {RSN_AKM_FBT_SHA384_1X, EAPOL_WPA_KCK_MIC_SHA384_LEN},
- {RSN_AKM_FBT_SHA384_PSK, EAPOL_WPA_KCK_MIC_SHA384_LEN},
- {0u, EAPOL_WPA_KCK_MIC_DEFAULT_LEN} /* default */
-};
-
-static const key_length_entry_t eapol_kck_len[] = {
- {RSN_AKM_SUITEB_SHA384_1X, EAPOL_WPA_KCK_SHA384_LEN},
- {RSN_AKM_FILS_SHA256, 0u},
- {RSN_AKM_FILS_SHA384, 0u},
- {RSN_AKM_FBT_SHA256_FILS, 0u},
- {RSN_AKM_FBT_SHA384_FILS, 0u},
- {RSN_AKM_OWE, EAPOL_WPA_KCK_DEFAULT_LEN},
- {RSN_AKM_FBT_SHA384_1X, EAPOL_WPA_KCK_SHA384_LEN},
- {RSN_AKM_FBT_SHA384_PSK, EAPOL_WPA_KCK_SHA384_LEN},
- {0u, EAPOL_WPA_KCK_DEFAULT_LEN} /* default */
-};
-
-static const key_length_entry_t eapol_kek_len[] = {
- {RSN_AKM_FILS_SHA384, EAPOL_WPA_ENCR_KEY_MAX_LEN},
- {RSN_AKM_FBT_SHA384_FILS, EAPOL_WPA_ENCR_KEY_MAX_LEN},
- {RSN_AKM_SUITEB_SHA384_1X, EAPOL_WPA_ENCR_KEY_MAX_LEN / 2},
- {RSN_AKM_FILS_SHA256, EAPOL_WPA_ENCR_KEY_MAX_LEN / 2},
- {RSN_AKM_FBT_SHA256_FILS, EAPOL_WPA_ENCR_KEY_MAX_LEN / 2},
- {RSN_AKM_OWE, EAPOL_WPA_ENCR_KEY_DEFAULT_LEN},
- {RSN_AKM_FBT_SHA384_1X, EAPOL_WPA_ENCR_KEY_MAX_LEN / 2},
- {RSN_AKM_FBT_SHA384_PSK, EAPOL_WPA_ENCR_KEY_MAX_LEN / 2},
- {0u, EAPOL_WPA_ENCR_KEY_DEFAULT_LEN} /* default */
-};
-
-static const key_length_entry_t eapol_tk_len[] = {
- {WPA_CIPHER_CCMP_256, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN},
- {WPA_CIPHER_AES_GCM256, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN},
- {WPA_CIPHER_BIP_GMAC_256, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN},
- {WPA_CIPHER_BIP_CMAC_256, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN},
- {WPA_CIPHER_AES_CCM, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN / 2},
- {WPA_CIPHER_AES_GCM, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN / 2},
- {WPA_CIPHER_BIP_GMAC_128, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN / 2},
- {WPA_CIPHER_TKIP, EAPOL_WPA_TEMP_ENCR_KEY_MAX_LEN},
- {0u, 0u} /* default */
-};
-
-#if defined(WL_FILS) && defined(WLFBT)
-static const key_length_entry_t eapol_kck2_len[] = {
- {RSN_AKM_FBT_SHA256_FILS, EAPOL_WPA_KCK2_SHA256_LEN},
- {RSN_AKM_FBT_SHA384_FILS, EAPOL_WPA_KCK2_SHA384_LEN},
- {0u, 0u} /* default */
-};
-
-static const key_length_entry_t eapol_kek2_len[] = {
- {RSN_AKM_FBT_SHA256_FILS, EAPOL_WPA_KEK2_SHA256_LEN},
- {RSN_AKM_FBT_SHA384_FILS, EAPOL_WPA_KEK2_SHA384_LEN},
- {0u, 0u} /* default */
-};
-#endif /* WL_FILS && WLFBT */
-
-typedef struct key_length_lookup {
- const eapol_key_type_t key;
- const key_length_entry_t *key_entry;
-} key_length_lookup_t;
-
-static const key_length_lookup_t eapol_key_lookup_tbl[] = {
- {EAPOL_KEY_PMK, eapol_pmk_len},
- {EAPOL_KEY_KCK_MIC, eapol_kck_mic_len},
- {EAPOL_KEY_KCK, eapol_kck_len},
- {EAPOL_KEY_KEK, eapol_kek_len},
- {EAPOL_KEY_TK, eapol_tk_len},
-#if defined(WL_FILS) && defined(WLFBT)
- {EAPOL_KEY_KCK2, eapol_kck2_len},
- {EAPOL_KEY_KEK2, eapol_kek2_len},
-#endif /* WL_FILS && WLFBT */
-};
-
-typedef struct rsn_akm_lookup_entry {
- const rsn_akm_t rsn_akm;
- const sha2_hash_type_t hash_type;
-} rsn_akm_lookup_entry_t;
-
-static const rsn_akm_lookup_entry_t rsn_akm_lookup_tbl[] = {
- {RSN_AKM_NONE, HASH_SHA1},
- {RSN_AKM_UNSPECIFIED, HASH_SHA1},
- {RSN_AKM_PSK, HASH_SHA1},
- {RSN_AKM_FBT_1X, HASH_SHA256},
- {RSN_AKM_FBT_PSK, HASH_SHA256},
- {RSN_AKM_MFP_1X, HASH_SHA256},
- {RSN_AKM_MFP_PSK, HASH_SHA256},
- {RSN_AKM_SHA256_1X, HASH_SHA256},
- {RSN_AKM_SHA256_PSK, HASH_SHA256},
- {RSN_AKM_TPK, HASH_SHA256},
- {RSN_AKM_SAE_PSK, HASH_SHA256},
- {RSN_AKM_SAE_FBT, HASH_SHA256},
- {RSN_AKM_SUITEB_SHA256_1X, HASH_SHA256},
- {RSN_AKM_SUITEB_SHA384_1X, HASH_SHA384},
- {RSN_AKM_FBT_SHA384_1X, HASH_SHA384},
- {RSN_AKM_FILS_SHA256, HASH_SHA256},
- {RSN_AKM_FILS_SHA384, HASH_SHA384},
- {RSN_AKM_FBT_SHA256_FILS, HASH_SHA256},
- {RSN_AKM_FBT_SHA384_FILS, HASH_SHA384},
- {RSN_AKM_OWE, HASH_SHA256},
- {RSN_AKM_FBT_SHA384_PSK, HASH_SHA384},
- {RSN_AKM_PSK_SHA384, HASH_SHA384},
-};
-
-typedef struct rsn_akm_cipher_match_entry {
- uint16 akm_type;
- uint32 u_cast; /* BITMAP */
- uint32 m_cast; /* BITMAP */
- uint32 g_mgmt; /* BITMAP */
-} rsn_akm_cipher_match_entry_t;
-
-/* list only explicit cipher restriction for given AKM (e.g SuiteB)
- * refer to 802.11 spec 9.4.2.24.3
- * If not listed here, it means no restriction in using any ciphers.
- */
-static const rsn_akm_cipher_match_entry_t rsn_akm_cipher_match_table[] = {
- {RSN_AKM_SUITEB_SHA256_1X,
- BCM_BIT(WPA_CIPHER_AES_GCM),
- BCM_BIT(WPA_CIPHER_AES_GCM),
- BCM_BIT(WPA_CIPHER_BIP_GMAC_128)},
- {RSN_AKM_SUITEB_SHA384_1X,
- BCM_BIT(WPA_CIPHER_AES_GCM256) | BCM_BIT(WPA_CIPHER_CCMP_256),
- BCM_BIT(WPA_CIPHER_AES_GCM256) | BCM_BIT(WPA_CIPHER_AES_GCM256),
- BCM_BIT(WPA_CIPHER_BIP_GMAC_256) | BCM_BIT(WPA_CIPHER_BIP_CMAC_256)},
- {RSN_AKM_FBT_SHA384_1X,
- BCM_BIT(WPA_CIPHER_AES_GCM256) | BCM_BIT(WPA_CIPHER_CCMP_256),
- BCM_BIT(WPA_CIPHER_AES_GCM256) | BCM_BIT(WPA_CIPHER_AES_GCM256),
- BCM_BIT(WPA_CIPHER_BIP_GMAC_256) | BCM_BIT(WPA_CIPHER_BIP_CMAC_256)}
-};
-
-#if defined(WL_BAND6G)
-static const rsn_akm_mask_t rsn_akm_6g_inval_mask =
- BCM_BIT(RSN_AKM_PSK) |
- BCM_BIT(RSN_AKM_FBT_PSK) |
- BCM_BIT(RSN_AKM_SHA256_PSK) |
- BCM_BIT(RSN_AKM_FBT_SHA384_PSK) |
- BCM_BIT(RSN_AKM_PSK_SHA384);
-
-static const rsn_ciphers_t cipher_6g_inval_mask =
- BCM_BIT(WPA_CIPHER_NONE) |
- BCM_BIT(WPA_CIPHER_WEP_40) |
- BCM_BIT(WPA_CIPHER_TKIP) |
- BCM_BIT(WPA_CIPHER_WEP_104);
-#endif /* WL_BAND6G */
-
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL)
-typedef struct group_cipher_algo_entry {
- rsn_cipher_t g_mgmt_cipher;
- uint8 bip_algo;
-} group_cipher_algo_entry_t;
-
-static const group_cipher_algo_entry_t group_mgmt_cipher_algo[] = {
- {WPA_CIPHER_BIP_GMAC_256, CRYPTO_ALGO_BIP_GMAC256},
- {WPA_CIPHER_BIP_CMAC_256, CRYPTO_ALGO_BIP_CMAC256},
- {WPA_CIPHER_BIP_GMAC_128, CRYPTO_ALGO_BIP_GMAC},
- {WPA_CIPHER_BIP, CRYPTO_ALGO_BIP},
-};
-#endif /* defined(BCMSUP_PSK) || defined(BCMSUPPL) */
-
-static uint16 wlc_calc_rsn_desc_version(const rsn_ie_info_t *rsn_info);
-static int bcmwpa_is_valid_akm(const rsn_akm_t akm);
-#if defined(BCMSUP_PSK) || defined(BCMAUTH_PSK) || defined(WLFBT) || defined(GTKOE)
-static sha2_hash_type_t bcmwpa_rsn_akm_to_hash(const rsn_akm_t akm);
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-static int bcmwpa_decode_cipher_suite(rsn_ie_info_t *info, const uint8 **ptr, uint ie_len, uint
- *remain_len, uint16 *p_count);
-#endif
-#endif /* defined(BCMSUP_PSK) || defined(BCMAUTH_PSK) || defined(WLFBT) || defined(GTKOE) */
-#if defined(BCMSUP_PSK) || defined(WLFBT) || defined(WL_OKC) || defined(WLHOSTFBT)
-#include <rc4.h>
-
-/* calculate wpa PMKID: HMAC-SHA1-128(PMK, "PMK Name" | AA | SPA) */
-static void
-wpa_calc_pmkid_impl(sha2_hash_type_t hash_type,
- const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *pmk, uint pmk_len, uint8 *pmkid)
-{
- int err;
- hmac_sha2_ctx_t ctx;
-
- err = hmac_sha2_init(&ctx, hash_type, pmk, pmk_len);
- if (err != BCME_OK)
- goto done;
- hmac_sha2_update(&ctx, (const uint8 *)PMK_NAME_PFX, sizeof(PMK_NAME_PFX) - 1);
- hmac_sha2_update(&ctx, (const uint8 *)auth_ea, ETHER_ADDR_LEN);
- hmac_sha2_update(&ctx, (const uint8 *)sta_ea, ETHER_ADDR_LEN);
- hmac_sha2_final(&ctx, pmkid, WPA2_PMKID_LEN);
-done:;
-}
-
-void
-wpa_calc_pmkid(const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *pmk, uint pmk_len, uint8 *pmkid)
-{
- wpa_calc_pmkid_impl(HASH_SHA1, auth_ea, sta_ea, pmk, pmk_len, pmkid);
-}
-
-void
-kdf_calc_pmkid(const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *key, uint key_len, uint8 *pmkid, rsn_ie_info_t *rsn_info)
-{
- sha2_hash_type_t hash_type;
-
- if (rsn_info->sta_akm == RSN_AKM_SUITEB_SHA384_1X) {
- hash_type = HASH_SHA384;
- } else {
- hash_type = HASH_SHA256;
- }
-
- wpa_calc_pmkid_impl(hash_type, auth_ea, sta_ea, key, key_len, pmkid);
-}
-
-#if defined(WLFBT) || defined(WLHOSTFBT)
-void
-wpa_calc_pmkR0(sha2_hash_type_t hash_type, const uint8 *ssid, uint ssid_len,
- uint16 mdid, const uint8 *r0kh, uint r0kh_len, const struct ether_addr *sta_ea,
- const uint8 *pmk, uint pmk_len, uint8 *pmkr0, uint8 *pmkr0name)
-{
- uint8 out[FBT_R0KH_ID_LEN + WPA2_PMKID_LEN - 1];
- int out_len = FBT_R0KH_ID_LEN - 1;
- bcm_const_xlvp_t pfx[7];
- bcm_const_xlvp_t pfx2[2];
- int npfx = 0;
- int npfx2 = 0;
- uint8 mdid_le[2];
- uint8 pfx_ssid_len;
- uint8 pfx_r0kh_len;
-
- if (hash_type == HASH_SHA384) {
- out_len += WPA2_PMKID_LEN;
- }
-
- /* create prefixes for pmkr0 */
- pfx[npfx].len = sizeof(FT_R0_PFX) - 1;
- pfx[npfx++].data = (uint8 *)FT_R0_PFX;
-
- /* ssid length and ssid */
- pfx_ssid_len = ssid_len & 0xff;
- pfx[npfx].len = (uint16)sizeof(pfx_ssid_len);
- pfx[npfx++].data = &pfx_ssid_len;
-
- pfx[npfx].len = (uint16)(ssid_len & 0xffff);
- pfx[npfx++].data = ssid;
-
- /* mdid */
- htol16_ua_store(mdid, mdid_le);
- pfx[npfx].len = sizeof(mdid_le);
- pfx[npfx++].data = mdid_le;
-
- /* r0kh len and r0kh */
- pfx_r0kh_len = r0kh_len & 0xff;
- pfx[npfx].len = sizeof(pfx_r0kh_len);
- pfx[npfx++].data = &pfx_r0kh_len;
-
- pfx[npfx].len = (uint16)(r0kh_len & 0xffff);
- pfx[npfx++].data = r0kh;
-
- /* sta addr */
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *)sta_ea;
-
- hmac_sha2_n(hash_type, pmk, pmk_len, pfx, npfx, NULL, 0, out, out_len);
- (void)memcpy_s(pmkr0, pmk_len, out, pmk_len);
-
- /* coverity checks overflow if pfx size changes */
-
- /* create prefixes for pmkr0 name */
- pfx2[npfx2].len = sizeof(FT_R0N_PFX) - 1;
- pfx2[npfx2++].data = (uint8 *)FT_R0N_PFX;
- pfx2[npfx2].len = WPA2_PMKID_LEN;
- pfx2[npfx2++].data = &out[pmk_len];
-
- (void)sha2(hash_type, pfx2, npfx2, NULL, 0, pmkr0name, WPA2_PMKID_LEN);
-}
-
-void
-wpa_calc_pmkR1(sha2_hash_type_t hash_type, const struct ether_addr *r1kh,
- const struct ether_addr *sta_ea, const uint8 *pmk, uint pmk_len, const uint8 *pmkr0name,
- uint8 *pmkr1, uint8 *pmkr1name)
-{
- bcm_const_xlvp_t pfx[3];
- bcm_const_xlvp_t pfx2[4];
- int npfx = 0;
- int npfx2 = 0;
-
- if (!pmkr1 && !pmkr1name)
- goto done;
- else if (!pmkr1)
- goto calc_r1name;
-
- /* create prefixes for pmkr1 */
- pfx[npfx].len = sizeof(FT_R1_PFX) - 1;
- pfx[npfx++].data = (uint8 *)FT_R1_PFX;
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *)r1kh;
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *)sta_ea;
-
- hmac_sha2_n(hash_type, pmk, pmk_len, pfx, npfx, NULL, 0,
- pmkr1, sha2_digest_len(hash_type));
-
-calc_r1name:
- /* create prefixes for pmkr1 name */
- pfx2[npfx2].len = sizeof(FT_R1N_PFX) - 1;
- pfx2[npfx2++].data = (uint8 *)FT_R1N_PFX;
-
- pfx2[npfx2].len = WPA2_PMKID_LEN;
- pfx2[npfx2++].data = pmkr0name;
-
- pfx2[npfx2].len = ETHER_ADDR_LEN;
- pfx2[npfx2++].data = (const uint8 *)r1kh;
-
- pfx2[npfx2].len = ETHER_ADDR_LEN;
- pfx2[npfx2++].data = (const uint8 *)sta_ea;
-
- sha2(hash_type, pfx2, npfx2, NULL, 0, pmkr1name, WPA2_PMKID_LEN);
-done:;
-}
-
-void
-wpa_calc_ft_ptk(sha2_hash_type_t hash_type,
- const struct ether_addr *bssid, const struct ether_addr *sta_ea,
- const uint8 *anonce, const uint8* snonce,
- const uint8 *pmk, uint pmk_len, uint8 *ptk, uint ptk_len)
-{
- bcm_const_xlvp_t pfx[5];
- int npfx = 0;
-
- /* FT-PTK||SNONCE||ANONCE||BSSID||STA Addr */
-
- pfx[npfx].len = sizeof(FT_PTK_PFX) - 1;
- pfx[npfx++].data = (uint8 *)FT_PTK_PFX;
-
- pfx[npfx].len = EAPOL_WPA_KEY_NONCE_LEN;
- pfx[npfx++].data = snonce;
-
- pfx[npfx].len = EAPOL_WPA_KEY_NONCE_LEN;
- pfx[npfx++].data = anonce;
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *)bssid;
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *)sta_ea;
-
- hmac_sha2_n(hash_type, pmk, pmk_len, pfx, npfx, NULL, 0, ptk, ptk_len);
-}
-
-void
-wpa_derive_pmkR1_name(sha2_hash_type_t hash_type,
- struct ether_addr *r1kh, struct ether_addr *sta_ea,
- uint8 *pmkr0name, uint8 *pmkr1name)
-{
- wpa_calc_pmkR1(hash_type, r1kh, sta_ea, NULL /* pmk */, 0,
- pmkr0name, NULL /* pmkr1 */, pmkr1name);
-}
-#endif /* WLFBT || WLHOSTFBT */
-#endif /* BCMSUP_PSK || WLFBT || WL_OKC */
-
-#if defined(BCMSUP_PSK) || defined(GTKOE) || defined(BCMAUTH_PSK) || defined(WLFBT)
-/* Decrypt a key data from a WPA key message */
-int
-wpa_decr_key_data(eapol_wpa_key_header_t *body, uint16 key_info, uint8 *ekey,
- uint8 *encrkey, rc4_ks_t *rc4key, const rsn_ie_info_t *rsn_info, uint16 *dec_len)
-{
- uint16 len;
- int err = BCME_OK;
- uint8 *key_data;
-
- switch (key_info & (WPA_KEY_DESC_V1 | WPA_KEY_DESC_V2)) {
- case WPA_KEY_DESC_V1:
- err = memcpy_s(encrkey, EAPOL_WPA_KEY_IV_LEN + EAPOL_WPA_ENCR_KEY_MAX_LEN,
- body->iv, EAPOL_WPA_KEY_IV_LEN);
- if (err) {
- ASSERT(0);
- return err;
- }
- err = memcpy_s(&encrkey[EAPOL_WPA_KEY_IV_LEN], EAPOL_WPA_ENCR_KEY_MAX_LEN,
- ekey, rsn_info->kek_len);
- if (err) {
- ASSERT(0);
- return err;
- }
- /* decrypt the key data */
- prepare_key(encrkey, EAPOL_WPA_KEY_IV_LEN + rsn_info->kek_len, rc4key);
- rc4(NULL, WPA_KEY_DATA_LEN_256, rc4key); /* dump 256 bytes */
- len = ntoh16_ua(EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body, rsn_info->kck_mic_len));
- key_data = EAPOL_WPA_KEY_HDR_DATA_PTR(body, rsn_info->kck_mic_len);
- rc4(key_data, len, rc4key);
- break;
-
- case WPA_KEY_DESC_V2:
- case WPA_KEY_DESC_V3:
- case WPA_KEY_DESC_V0:
- /* fallthrough */
- len = ntoh16_ua(EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body, rsn_info->kck_mic_len));
- if (!len) {
- *dec_len = 0;
- break; /* ignore zero length */
- }
- key_data = EAPOL_WPA_KEY_HDR_DATA_PTR(body, rsn_info->kck_mic_len);
- if (aes_unwrap(rsn_info->kek_len, ekey, len, key_data, key_data)) {
- *dec_len = 0;
- err = BCME_DECERR;
- break;
- }
- *dec_len = (len > AKW_BLOCK_LEN) ? (len - AKW_BLOCK_LEN) : 0;
- break;
-
- default:
- *dec_len = 0;
- err = BCME_UNSUPPORTED; /* may need revisiting - see 802.11-2016 */
- break;
- }
-
- return err;
-}
-
-/* internal function - assumes enouch space allocated, retuns written number */
-static int
-wpa_calc_ptk_prefixes(const uint8 *prefix, uint prefix_len,
- const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *anonce, uint8 anonce_len, const uint8 *snonce, uint8 snonce_len,
- bcm_const_xlvp_t *pfx)
-{
- int npfx = 0;
- const uint8 *nonce;
-
- /* prefix || min ea || max ea || min nonce || max nonce */
- pfx[npfx].len = (uint16)(prefix_len & 0xffff);
- pfx[npfx++].data = prefix;
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *) wpa_array_cmp(MIN_ARRAY,
- (const uint8 *)auth_ea, (const uint8 *)sta_ea, ETHER_ADDR_LEN);
-
- pfx[npfx].len = ETHER_ADDR_LEN;
- pfx[npfx++].data = (const uint8 *) wpa_array_cmp(MAX_ARRAY,
- (const uint8 *)auth_ea, (const uint8 *)sta_ea, ETHER_ADDR_LEN);
-
- nonce = (const uint8 *)wpa_array_cmp(MIN_ARRAY, snonce, anonce, snonce_len);
-
- if (nonce == snonce) {
- pfx[npfx].len = snonce_len;
- pfx[npfx++].data = snonce;
- pfx[npfx].len = anonce_len;
- pfx[npfx++].data = anonce;
- } else {
- pfx[npfx].len = anonce_len;
- pfx[npfx++].data = anonce;
- pfx[npfx].len = snonce_len;
- pfx[npfx++].data = snonce;
- }
-
- return npfx;
-}
-
-void
-kdf_calc_ptk(const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *anonce, const uint8* snonce,
- const uint8 *pmk, uint pmk_len, uint8 *ptk, uint ptk_len)
-{
- bcm_const_xlvp_t pfx[5];
- int npfx;
-
- /* note: kdf omits trailing NULL in prefix */
- npfx = wpa_calc_ptk_prefixes((uint8 *)WPA_PTK_PFX, sizeof(WPA_PTK_PFX) - 1,
- auth_ea, sta_ea, anonce, EAPOL_WPA_KEY_NONCE_LEN, snonce,
- EAPOL_WPA_KEY_NONCE_LEN, pfx);
- hmac_sha2_n(HASH_SHA256, pmk, pmk_len, pfx, npfx, NULL, 0, ptk, ptk_len);
-}
-#endif /* BCMSUP_PSK || GTKOE || BCMAUTH_PSK || WLFBT */
-
-#if defined(BCMSUP_PSK) || defined(BCMAUTH_PSK) || defined(WLFBT) || defined(GTKOE)
-/* Compute Message Integrity Code (MIC) over EAPOL message */
-int
-wpa_make_mic(eapol_header_t *eapol, uint key_desc, uint8 *mic_key,
- rsn_ie_info_t *rsn_info, uchar *mic, uint mic_len)
-{
- uint data_len;
- int err = BCME_OK;
- sha2_hash_type_t type = HASH_NONE;
-
- /* length of eapol pkt from the version field on */
- data_len = 4 + ntoh16_ua((uint8 *)&eapol->length);
-
- /* Create the MIC for the pkt */
- switch (key_desc) {
- case WPA_KEY_DESC_V1:
- type = HASH_MD5;
- break;
- case WPA_KEY_DESC_V2:
- /* note: transparent truncation to mic_len */
- type = HASH_SHA1;
- break;
- case WPA_KEY_DESC_V3:
- aes_cmac_calc(NULL, 0, &eapol->version, data_len, mic_key,
- mic_len, mic, AES_BLOCK_SZ);
- goto exit;
- case WPA_KEY_DESC_V0:
- ASSERT(rsn_info != NULL);
- if (rsn_info == NULL) {
- return BCME_BADARG;
- }
- if (IS_SAE_AKM(rsn_info->sta_akm)) {
- aes_cmac_calc(NULL, 0, &eapol->version, data_len, mic_key,
- mic_len, mic, AES_BLOCK_SZ);
- goto exit;
- }
- type = bcmwpa_rsn_akm_to_hash(rsn_info->sta_akm);
- break;
- default:
- /* 11mc D8.0 some AKMs use descriptor version 0 */
- err = BCME_UNSUPPORTED;
- goto exit;
- }
-
- if (type) {
- err = hmac_sha2(type, mic_key, mic_len, NULL, 0, (uint8 *)&eapol->version, data_len,
- mic, mic_len);
- }
-exit:
- return err;
-}
-
-int
-wpa_calc_ptk(rsn_akm_t akm, const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *anonce, uint8 anon_len, const uint8 *snonce, uint8 snon_len, const uint8 *pmk,
- uint pmk_len, uint8 *ptk, uint ptk_len)
-{
- bcm_const_xlvp_t pfx[PRF_PREFIXES_NUM];
- int npfx;
- int ret = BCME_OK;
- sha2_hash_type_t hash_type;
- uint label_len;
-
- if (RSN_AKM_USE_KDF(akm)) {
- label_len = sizeof(WPA_PTK_PFX) - 1u;
- } else { //WPA AKMS
- label_len = sizeof(WPA_PTK_PFX); /* note: wpa needs trailing NULL in prefix */
- }
-
- hash_type = bcmwpa_rsn_akm_to_hash(akm);
-
- npfx = wpa_calc_ptk_prefixes((uint8 *)WPA_PTK_PFX, label_len,
- auth_ea, sta_ea, anonce, anon_len, snonce, snon_len, pfx);
- ret = hmac_sha2_n(hash_type, pmk, pmk_len, pfx, npfx, NULL, 0, ptk, ptk_len);
- return ret;
-}
-
-bool
-wpa_encr_key_data(eapol_wpa_key_header_t *body, uint16 key_info, uint8 *ekey,
- uint8 *gtk, uint8 *data, uint8 *encrkey, rc4_ks_t *rc4key, const rsn_ie_info_t *rsn_info)
-{
- uint16 len;
- uint8 *key_data;
-
- switch (key_info & (WPA_KEY_DESC_V1 | WPA_KEY_DESC_V2)) {
- case WPA_KEY_DESC_V1:
- if (gtk) {
- len = ntoh16_ua((uint8 *)&body->key_len);
- } else {
- len = ntoh16_ua(EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body,
- rsn_info->kck_mic_len));
- }
-
- /* create the iv/ptk key */
- if (memcpy_s(encrkey, EAPOL_WPA_KEY_IV_LEN, body->iv, sizeof(body->iv))) {
- return FALSE;
- }
- if (memcpy_s(&encrkey[EAPOL_WPA_KEY_IV_LEN], EAPOL_WPA_ENCR_KEY_DEFAULT_LEN,
- ekey, EAPOL_WPA_ENCR_KEY_DEFAULT_LEN)) {
- return FALSE;
- }
- /* encrypt the key data */
- prepare_key(encrkey, EAPOL_WPA_KEY_IV_LEN + EAPOL_WPA_ENCR_KEY_DEFAULT_LEN,
- rc4key);
- rc4(data, WPA_KEY_DATA_LEN_256, rc4key); /* dump 256 bytes */
- key_data = EAPOL_WPA_KEY_HDR_DATA_PTR(body, rsn_info->kck_mic_len);
- rc4(key_data, len, rc4key);
- break;
- case WPA_KEY_DESC_V2: /* fall through */
- case WPA_KEY_DESC_V3:
- case WPA_KEY_DESC_V0:
- len = ntoh16_ua(EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body,
- rsn_info->kck_mic_len));
- /* FIXME: data_len is length to encrypt, but need to make sure
- * buffer is big enought
- * for expansion. how? problem for caller?
- */
- key_data = EAPOL_WPA_KEY_HDR_DATA_PTR(body, rsn_info->kck_mic_len);
- /* pad if needed - min. 16 bytes, 8 byte aligned */
- /* padding is 0xdd followed by 0's */
- if (len < 2u *AKW_BLOCK_LEN) {
- key_data[len] = WPA2_KEY_DATA_PAD;
- bzero(&key_data[len + 1u], 2u * AKW_BLOCK_LEN - (len + 1u));
- len = 2u *AKW_BLOCK_LEN;
- } else if (len % AKW_BLOCK_LEN) {
- key_data[len] = WPA2_KEY_DATA_PAD;
- bzero(&key_data[len + 1u],
- AKW_BLOCK_LEN - ((len + 1u) % AKW_BLOCK_LEN));
- len += AKW_BLOCK_LEN - (len % AKW_BLOCK_LEN);
- }
- if (aes_wrap(rsn_info->kek_len, ekey, len, key_data, key_data)) {
- return FALSE;
- }
- len += AKW_BLOCK_LEN;
- hton16_ua_store(len,
- (uint8 *)EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body,
- rsn_info->kck_mic_len));
- break;
- default:
- /* 11mc D8.0 key descriptor version 0 used */
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* Check MIC of EAPOL message */
-bool
-wpa_check_mic(eapol_header_t *eapol, uint key_desc, uint8 *mic_key, rsn_ie_info_t *rsn_info)
-{
- eapol_wpa_key_header_t *body = NULL;
- uchar digest[SHA2_MAX_DIGEST_LEN];
- uchar mic[EAPOL_WPA_KEY_MAX_MIC_LEN];
-
- if (!mic_key || !rsn_info || !eapol) {
- return FALSE;
- }
-
- body = (eapol_wpa_key_header_t *)eapol->body;
-
-#ifndef EAPOL_KEY_HDR_VER_V2
- if (rsn_info->kck_mic_len != EAPOL_WPA_KCK_DEFAULT_LEN)
-#else
- if (rsn_info->kck_mic_len > EAPOL_WPA_KEY_MAX_MIC_LEN)
-#endif /* EAPOL_KEY_HDR_VER_V2 */
- {
- ASSERT(0);
- return FALSE;
- }
- /* save MIC and clear its space in message */
- if (memcpy_s(mic, sizeof(mic), EAPOL_WPA_KEY_HDR_MIC_PTR(body),
- rsn_info->kck_mic_len)) {
- return FALSE;
- }
- bzero(EAPOL_WPA_KEY_HDR_MIC_PTR(body), rsn_info->kck_mic_len);
- if (wpa_make_mic(eapol, key_desc, mic_key, rsn_info, digest, rsn_info->kck_mic_len)
- != BCME_OK) {
- return FALSE;
- }
- return !memcmp(digest, mic, rsn_info->kck_mic_len);
-}
-
-static sha2_hash_type_t bcmwpa_rsn_akm_to_hash(const rsn_akm_t akm)
-{
- uint i = 0;
- sha2_hash_type_t type = HASH_NONE;
-
- for (i = 0; i < ARRAYSIZE(rsn_akm_lookup_tbl); i++) {
- if (akm == rsn_akm_lookup_tbl[i].rsn_akm) {
- type = rsn_akm_lookup_tbl[i].hash_type;
- break;
- }
- }
- return type;
-}
-#endif /* BCMSUP_PSK || BCMAUTH_PSK || WLFBT || GTKOE */
-
-#ifdef WLTDLS
-void
-wpa_calc_tpk(const struct ether_addr *init_ea, const struct ether_addr *resp_ea,
- const struct ether_addr *bssid, const uint8 *anonce, const uint8* snonce,
- uint8 *tpk, uint tpk_len)
-{
- uint8 pmk[SHA2_MAX_DIGEST_LEN];
- uint pmk_len;
- bcm_const_xlvp_t ikpfx[2];
- int nikpfx = 0;
- bcm_const_xlvp_t tpkpfx[4];
- int ntpkpfx = 0;
-
- pmk_len = sha2_digest_len(HASH_SHA256);
-
- /* compute pmk to use - using anonce and snonce - min and then max */
- ikpfx[nikpfx].len = EAPOL_WPA_KEY_NONCE_LEN;
- ikpfx[nikpfx++].data = wpa_array_cmp(MIN_ARRAY, snonce, anonce,
- EAPOL_WPA_KEY_NONCE_LEN),
-
- ikpfx[nikpfx].len = EAPOL_WPA_KEY_NONCE_LEN;
- ikpfx[nikpfx++].data = wpa_array_cmp(MAX_ARRAY, snonce, anonce,
- EAPOL_WPA_KEY_NONCE_LEN),
-
- (void)sha2(HASH_SHA256, ikpfx, nikpfx, NULL, 0, pmk, SHA2_SHA256_DIGEST_LEN);
-
- /* compute the tpk - using prefix, min ea, max ea, bssid */
- tpkpfx[ntpkpfx].len = sizeof(TDLS_PMK_PFX) - 1;
- tpkpfx[ntpkpfx++].data = (const uint8 *)TDLS_PMK_PFX;
-
- tpkpfx[ntpkpfx].len = ETHER_ADDR_LEN;
- tpkpfx[ntpkpfx++].data = wpa_array_cmp(MIN_ARRAY, (const uint8 *)init_ea,
- (const uint8 *)resp_ea, ETHER_ADDR_LEN),
-
- tpkpfx[ntpkpfx].len = ETHER_ADDR_LEN;
- tpkpfx[ntpkpfx++].data = wpa_array_cmp(MAX_ARRAY, (const uint8 *)init_ea,
- (const uint8 *)resp_ea, ETHER_ADDR_LEN),
-
- tpkpfx[ntpkpfx].len = ETHER_ADDR_LEN;
- tpkpfx[ntpkpfx++].data = (const uint8 *)bssid;
-
- (void)hmac_sha2_n(HASH_SHA256, pmk, pmk_len, tpkpfx, ntpkpfx, NULL, 0, tpk, tpk_len);
-}
-#endif /* WLTDLS */
-
-/* Convert WPA/WPA2 IE cipher suite to locally used value */
-static bool
-rsn_cipher(wpa_suite_t *suite, ushort *cipher, const uint8 *std_oui, bool wep_ok)
-{
- bool ret = TRUE;
-
- if (!memcmp((const char *)suite->oui, std_oui, DOT11_OUI_LEN)) {
- switch (suite->type) {
- case WPA_CIPHER_TKIP:
- *cipher = CRYPTO_ALGO_TKIP;
- break;
- case WPA_CIPHER_AES_CCM:
- *cipher = CRYPTO_ALGO_AES_CCM;
- break;
- case WPA_CIPHER_AES_GCM:
- *cipher = CRYPTO_ALGO_AES_GCM;
- break;
- case WPA_CIPHER_AES_GCM256:
- *cipher = CRYPTO_ALGO_AES_GCM256;
- break;
- case WPA_CIPHER_WEP_40:
- if (wep_ok)
- *cipher = CRYPTO_ALGO_WEP1;
- else
- ret = FALSE;
- break;
- case WPA_CIPHER_WEP_104:
- if (wep_ok)
- *cipher = CRYPTO_ALGO_WEP128;
- else
- ret = FALSE;
- break;
- default:
- ret = FALSE;
- break;
- }
- return ret;
- }
-
- return FALSE;
-}
-
-bool
-wpa_cipher(wpa_suite_t *suite, ushort *cipher, bool wep_ok)
-{
- return rsn_cipher(suite, cipher, (const uchar*)WPA_OUI, wep_ok);
-}
-
-bool
-wpa2_cipher(wpa_suite_t *suite, ushort *cipher, bool wep_ok)
-{
- return rsn_cipher(suite, cipher, (const uchar*)WPA2_OUI, wep_ok);
-}
-
-/* Is any of the tlvs the expected entry? If
- * not update the tlvs buffer pointer/length.
- */
-bool
-bcm_has_ie(uint8 *ie, uint8 **tlvs, uint *tlvs_len, const uint8 *oui, uint oui_len, uint8 type)
-{
- /* If the contents match the OUI and the type */
- if (ie[TLV_LEN_OFF] >= oui_len + 1 &&
- !memcmp(&ie[TLV_BODY_OFF], oui, oui_len) &&
- type == ie[TLV_BODY_OFF + oui_len]) {
- return TRUE;
- }
-
- /* point to the next ie */
- ie += ie[TLV_LEN_OFF] + TLV_HDR_LEN;
- /* calculate the length of the rest of the buffer */
- *tlvs_len -= (uint)(ie - *tlvs);
- /* update the pointer to the start of the buffer */
- *tlvs = ie;
-
- return FALSE;
-}
-
-wpa_ie_fixed_t *
-bcm_find_wpaie(uint8 *parse, uint len)
-{
- return (wpa_ie_fixed_t *) bcm_find_ie(parse, len, DOT11_MNG_VS_ID,
- WPA_OUI_LEN, (const char*) WPA_OUI, WPA_OUI_TYPE);
-}
-
-int
-bcm_find_security_ies(uint8 *buf, uint buflen, void **wpa_ie,
- void **rsn_ie)
-{
- bcm_tlv_t *tlv = NULL;
- uint totlen = 0;
- uint8 *end = NULL;
- uint len = 0;
- uint tlvs_len = 0;
- uint8 *tlvs = NULL;
-
- if ((tlv = (bcm_tlv_t*)buf) == NULL ||
- !wpa_ie || !rsn_ie || buflen == 0) {
- return BCME_BADARG;
- }
-
- totlen = buflen;
- *rsn_ie = *wpa_ie = NULL;
- end = buf;
- end += buflen;
-
- /* find rsn ie and wpa ie */
- while (totlen >= TLV_HDR_LEN) {
- len = tlv->len;
- tlvs_len = buflen;
- tlvs = buf;
-
- /* check if tlv overruns buffer */
- if (totlen < (len + TLV_HDR_LEN)) {
- return BCME_BUFTOOSHORT;
- }
-
- /* validate remaining totlen */
- if (totlen >= (len + TLV_HDR_LEN)) {
- if ((*rsn_ie == NULL) && (tlv->id == DOT11_MNG_RSN_ID)) {
- *rsn_ie = tlv;
- } else if ((*wpa_ie == NULL) && (tlv->id == DOT11_MNG_VS_ID)) {
- /* if vendor ie, check if its wpa ie */
- if (bcm_is_wpa_ie((uint8 *)tlv, &tlvs, &tlvs_len))
- *wpa_ie = tlv;
- }
- }
-
- if (*rsn_ie && *wpa_ie)
- break;
-
- tlv = (bcm_tlv_t*)((uint8*)tlv + (len + TLV_HDR_LEN));
- totlen -= (len + TLV_HDR_LEN);
-
- if (totlen > buflen) {
- return BCME_BUFTOOLONG;
- }
-
- if ((uint8 *)tlv > end) {
- return BCME_BUFTOOSHORT;
- }
-
- }
-
- if (*wpa_ie || *rsn_ie)
- return BCME_OK;
- else
- return BCME_NOTFOUND;
-}
-
-bcm_tlv_t *
-bcm_find_wmeie(uint8 *parse, uint len, uint8 subtype, uint8 subtype_len)
-{
- bcm_tlv_t *ie;
- if ((ie = bcm_find_ie(parse, len, DOT11_MNG_VS_ID, WME_OUI_LEN,
- (const char*) WME_OUI, WME_OUI_TYPE))) {
- uint ie_len = TLV_HDR_LEN + ie->len;
- wme_ie_t *ie_data = (wme_ie_t *)ie->data;
- /* the subtype_len must include OUI+type+subtype */
- if (subtype_len > WME_OUI_LEN + 1 &&
- ie_len == (uint)TLV_HDR_LEN + subtype_len &&
- ie_data->subtype == subtype) {
- return ie;
- }
- /* move to next IE */
- len -= (uint)((uint8 *)ie + ie_len - parse);
- parse = (uint8 *)ie + ie_len;
- }
- return NULL;
-}
-
-wps_ie_fixed_t *
-bcm_find_wpsie(const uint8 *parse, uint len)
-{
- uint8 type = WPS_OUI_TYPE;
-
- return (wps_ie_fixed_t *)bcm_find_vendor_ie(parse, len, WPS_OUI, &type, sizeof(type));
-}
-
-/* locate the Attribute in the WPS IE */
-/* assume the caller has validated the WPS IE tag and length */
-wps_at_fixed_t *
-bcm_wps_find_at(wps_at_fixed_t *at, uint len, uint16 id)
-{
- while ((int)len >= WPS_AT_FIXED_LEN) {
- uint alen = WPS_AT_FIXED_LEN + ntoh16_ua(((wps_at_fixed_t *)at)->len);
- if (ntoh16_ua(((wps_at_fixed_t *)at)->at) == id && alen <= len)
- return at;
- at = (wps_at_fixed_t *)((uint8 *)at + alen);
- len -= alen;
- }
- return NULL;
-}
-
-#ifdef WLP2P
-wifi_p2p_ie_t *
-bcm_find_p2pie(const uint8 *parse, uint len)
-{
- uint8 type = P2P_OUI_TYPE;
-
- return (wifi_p2p_ie_t *)bcm_find_vendor_ie(parse, len, P2P_OUI, &type, sizeof(type));
-}
-#endif
-
-bcm_tlv_t *
-bcm_find_hs20ie(uint8 *parse, uint len)
-{
- return bcm_find_ie(parse, len, DOT11_MNG_VS_ID, WFA_OUI_LEN,
- (const char *)WFA_OUI, WFA_OUI_TYPE_HS20);
-}
-
-bcm_tlv_t *
-bcm_find_osenie(uint8 *parse, uint len)
-{
- return bcm_find_ie(parse, len, DOT11_MNG_VS_ID, WFA_OUI_LEN,
- (const char *) WFA_OUI, WFA_OUI_TYPE_OSEN);
-}
-
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL) || defined(GTKOE) || defined(WL_FILS)
-#define wpa_is_kde(ie, tlvs, len, type) bcm_has_ie(ie, tlvs, len, \
- (const uint8 *)WPA2_OUI, WPA2_OUI_LEN, type)
-
-eapol_wpa2_encap_data_t *
-wpa_find_kde(const uint8 *parse, uint len, uint8 type)
-{
- return (eapol_wpa2_encap_data_t *) bcm_find_ie(parse, len,
- DOT11_MNG_PROPR_ID, WPA2_OUI_LEN, (const char *) WPA2_OUI, type);
-}
-
-bool
-wpa_is_gtk_encap(uint8 *ie, uint8 **tlvs, uint *tlvs_len)
-{
- return wpa_is_kde(ie, tlvs, tlvs_len, WPA2_KEY_DATA_SUBTYPE_GTK);
-}
-
-eapol_wpa2_encap_data_t *
-wpa_find_gtk_encap(uint8 *parse, uint len)
-{
- eapol_wpa2_encap_data_t *data;
-
- /* minimum length includes kde upto gtk field in eapol_wpa2_key_gtk_encap_t */
- data = wpa_find_kde(parse, len, WPA2_KEY_DATA_SUBTYPE_GTK);
- if (data && (data->length < EAPOL_WPA2_GTK_ENCAP_MIN_LEN)) {
- data = NULL;
- }
-
- return data;
-}
-
-int
-wpa_find_eapol_kde_data(eapol_header_t* eapol, uint8 eapol_mic_len,
- uint8 subtype, eapol_wpa2_encap_data_t **out_data)
-{
- eapol_wpa_key_header_t *body;
- uint8 *parse;
- uint16 body_len;
- uint16 data_len;
-
- if (!eapol) {
- return BCME_BADARG;
- }
-
- body = (eapol_wpa_key_header_t *)eapol->body;
- body_len = ntoh16_ua(&eapol->length);
-
- data_len = ntoh16_ua(EAPOL_WPA_KEY_HDR_DATA_LEN_PTR(body,
- eapol_mic_len));
-
- parse = EAPOL_WPA_KEY_HDR_DATA_PTR(body, eapol_mic_len);
-
- if (((uint8 *)body + body_len) < ((uint8 *)parse + data_len)) {
- return BCME_BUFTOOSHORT;
- }
-
- return wpa_find_kde_data(parse, data_len, subtype, out_data);
-}
-
-int
-wpa_find_kde_data(const uint8 *kde_buf, uint16 buf_len,
- uint8 subtype, eapol_wpa2_encap_data_t **out_data)
-{
- eapol_wpa2_encap_data_t *data;
- uint8 min_len;
-
- if (!kde_buf) {
- return BCME_BADARG;
- }
-
- /* minimum length includes kde upto gtk field in eapol_wpa2_key_gtk_encap_t */
- data = wpa_find_kde(kde_buf, buf_len, subtype);
- if (!data) {
- return BCME_IE_NOTFOUND;
- }
-
- switch (subtype) {
- case WPA2_KEY_DATA_SUBTYPE_GTK:
- min_len = EAPOL_WPA2_GTK_ENCAP_MIN_LEN;
- break;
- case WPA2_KEY_DATA_SUBTYPE_IGTK:
- min_len = EAPOL_WPA2_BIGTK_ENCAP_MIN_LEN;
- break;
- case WPA2_KEY_DATA_SUBTYPE_BIGTK:
- min_len = EAPOL_WPA2_IGTK_ENCAP_MIN_LEN;
- break;
-#ifdef WL_OCV
- case WPA2_KEY_DATA_SUBTYPE_OCI:
- min_len = EAPOL_WPA2_OCI_ENCAP_MIN_LEN;
- break;
-#endif /* WL_OCV */
- default:
- return BCME_UNSUPPORTED;
- }
-
- if (data->length < min_len) {
- return BCME_BADLEN;
- }
-
- *out_data = data;
-
- return BCME_OK;
-}
-
-#ifdef WL_OCV
-bool
-wpa_check_ocv_caps(uint16 local_caps, uint16 peer_caps)
-{
- bool ocv_enabled =
- ((local_caps & RSN_CAP_OCVC) &&
- (peer_caps & RSN_CAP_OCVC));
- bool mfp_enabled =
- ((peer_caps & RSN_CAP_MFPC) ||
- (peer_caps & RSN_CAP_MFPR));
-
- return (ocv_enabled && mfp_enabled);
-}
-
-int
-wpa_add_oci_encap(chanspec_t chspec, uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- eapol_wpa2_encap_data_t* oci_kde;
- uint len = buf_len;
-
- if (buf_len < WPA_OCV_OCI_KDE_SIZE) {
- retval = BCME_BUFTOOSHORT;
- goto done;
- }
-
- oci_kde = (eapol_wpa2_encap_data_t*)buf;
-
- oci_kde->type = DOT11_MNG_WPA_ID;
- oci_kde->subtype = WPA2_KEY_DATA_SUBTYPE_OCI;
- oci_kde->length = (WPA_OCV_OCI_KDE_SIZE - TLV_HDR_LEN);
-
- oci_kde->oui[0u] = WPA2_OUI[0u];
- oci_kde->oui[1u] = WPA2_OUI[1u];
- oci_kde->oui[2u] = WPA2_OUI[2u];
-
- buf += EAPOL_WPA2_ENCAP_DATA_HDR_LEN;
- len -= EAPOL_WPA2_ENCAP_DATA_HDR_LEN;
-
- retval = bcm_ocv_write_oci(chspec, buf, len);
- if (retval != BCME_OK) {
- goto done;
- }
-
-done:
- return retval;
-}
-
-int
-wpa_add_oci_ie(chanspec_t chspec, uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- uint8* oci_buf = buf + BCM_TLV_EXT_HDR_SIZE;
-
- if (buf_len < (bcm_ocv_get_oci_len() + BCM_TLV_EXT_HDR_SIZE)) {
- retval = BCME_BUFTOOSHORT;
- goto done;
- }
-
- retval = bcm_ocv_write_oci(chspec, oci_buf, bcm_ocv_get_oci_len());
- if (retval != BCME_OK) {
- goto done;
- }
-
- (void)bcm_write_tlv_ext(DOT11_MNG_ID_EXT_ID,
- OCV_EXTID_MNG_OCI_ID, oci_buf, bcm_ocv_get_oci_len(), buf);
-
-done:
- return retval;
-}
-
-int
-wpa_add_oci_ft_subelem(chanspec_t chspec, uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- uint8* oci_buf = buf + BCM_TLV_HDR_SIZE;
-
- if (buf_len < (bcm_ocv_get_oci_len() + BCM_TLV_HDR_SIZE)) {
- retval = BCME_BUFTOOSHORT;
- goto done;
- }
-
- retval = bcm_ocv_write_oci(chspec, oci_buf, bcm_ocv_get_oci_len());
- if (retval != BCME_OK) {
- goto done;
- }
-
- bcm_write_tlv_safe(DOT11_FBT_SUBELEM_ID_OCI,
- oci_buf, bcm_ocv_get_oci_len(), buf, buf_len);
-
-done:
- return retval;
-}
-
-int wpa_validate_oci_encap(chanspec_t chspec, const uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- eapol_wpa2_encap_data_t *encap = NULL;
-
- retval = wpa_find_kde_data(buf, buf_len, WPA2_KEY_DATA_SUBTYPE_OCI, &encap);
- if (retval != BCME_OK) {
- retval = BCME_NOTFOUND;
- goto done;
- }
-
- retval = bcm_ocv_validate_oci(chspec,
- encap->data, encap->length);
- if (retval != BCME_OK) {
- goto done;
- }
-
-done:
- return retval;
-}
-
-int wpa_validate_oci_ie(chanspec_t chspec, const uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- bcm_tlv_ext_t *oci_ie;
-
- oci_ie = (bcm_tlv_ext_t *)bcm_parse_tlvs_dot11(buf, buf_len,
- OCV_EXTID_MNG_OCI_ID, TRUE);
-
- if (!oci_ie) {
- retval = BCME_NOTFOUND;
- goto done;
- }
-
- retval = bcm_ocv_validate_oci(chspec, oci_ie->data, oci_ie->len);
- if (retval != BCME_OK) {
- goto done;
- }
-
-done:
- return retval;
-}
-
-int wpa_validate_oci_ft_subelem(chanspec_t chspec, const uint8* buf, uint buf_len)
-{
- int retval = BCME_OK;
- bcm_tlv_t *oci_ie;
-
- oci_ie = (bcm_tlv_t *)bcm_parse_tlvs_dot11(buf, buf_len,
- DOT11_FBT_SUBELEM_ID_OCI, FALSE);
-
- if (!oci_ie) {
- retval = BCME_NOTFOUND;
- goto done;
- }
-
- retval = bcm_ocv_validate_oci(chspec, oci_ie->data, oci_ie->len);
- if (retval != BCME_OK) {
- goto done;
- }
-
-done:
- return retval;
-}
-#endif /* WL_OCV */
-#endif /* defined(BCMSUP_PSK) || defined(BCMSUPPL) || defined(GTKOE) || defined(WL_FILS) */
-
-const uint8 *
-wpa_array_cmp(int max_array, const uint8 *x, const uint8 *y, uint len)
-{
- uint i;
- const uint8 *ret = x;
-
- for (i = 0; i < len; i++)
- if (x[i] != y[i])
- break;
-
- if (i == len) {
- /* returning null will cause crash, return value used for copying */
- /* return first param in this case to close security loophole */
- return x;
- }
- if (max_array && (y[i] > x[i]))
- ret = y;
- if (!max_array && (y[i] < x[i]))
- ret = y;
-
- return (ret);
-}
-
-void
-wpa_incr_array(uint8 *array, uint len)
-{
- int i;
-
- for (i = (len-1); i >= 0; i--)
- if (array[i]++ != 0xff) {
- break;
- }
-}
-
-bool
-bcmwpa_akm2WPAauth(uint8 *akm, uint32 *auth, bool sta_iswpa)
-{
- uint i;
- oui_akm_wpa_tbl_t wpa_auth_tbl_match[] = {
- {WPA2_OUI, RSN_AKM_NONE, WPA_AUTH_NONE},
- {WPA2_OUI, RSN_AKM_UNSPECIFIED, WPA2_AUTH_UNSPECIFIED},
- {WPA2_OUI, RSN_AKM_PSK, WPA2_AUTH_PSK},
- {WPA2_OUI, RSN_AKM_FBT_1X, WPA2_AUTH_UNSPECIFIED | WPA2_AUTH_FT},
- {WPA2_OUI, RSN_AKM_FBT_PSK, WPA2_AUTH_PSK | WPA2_AUTH_FT},
- {WPA2_OUI, RSN_AKM_SHA256_1X, WPA2_AUTH_1X_SHA256},
- {WPA2_OUI, RSN_AKM_SHA256_PSK, WPA2_AUTH_PSK_SHA256},
- {WPA2_OUI, RSN_AKM_FILS_SHA256, WPA2_AUTH_FILS_SHA256},
- {WPA2_OUI, RSN_AKM_FILS_SHA384, WPA2_AUTH_FILS_SHA384},
- {WPA2_OUI, RSN_AKM_FBT_SHA256_FILS, WPA2_AUTH_FILS_SHA256 | WPA2_AUTH_FT},
- {WPA2_OUI, RSN_AKM_FBT_SHA384_FILS, WPA2_AUTH_FILS_SHA384 | WPA2_AUTH_FT},
- {WPA2_OUI, RSN_AKM_SAE_PSK, WPA3_AUTH_SAE_PSK},
- {WPA2_OUI, RSN_AKM_SAE_FBT, WPA3_AUTH_SAE_PSK | WPA2_AUTH_FT},
- {WPA2_OUI, RSN_AKM_OWE, WPA3_AUTH_OWE},
- {WPA2_OUI, RSN_AKM_SUITEB_SHA256_1X, WPA3_AUTH_1X_SUITE_B_SHA256},
- {WPA2_OUI, RSN_AKM_SUITEB_SHA384_1X, WPA3_AUTH_1X_SUITE_B_SHA384},
- {WFA_OUI, OSEN_AKM_UNSPECIFIED, WPA2_AUTH_UNSPECIFIED},
- {WFA_OUI, RSN_AKM_FBT_SHA256_FILS, WPA2_AUTH_FILS_SHA256 | WPA2_AUTH_FT},
- {WFA_OUI, RSN_AKM_FBT_SHA384_FILS, WPA2_AUTH_FILS_SHA384 | WPA2_AUTH_FT},
- {WFA_OUI, RSN_AKM_DPP, WPA3_AUTH_DPP_AKM},
-
-#ifdef BCMWAPI_WAI
- {WAPI_OUI, RSN_AKM_NONE, WAPI_AUTH_NONE},
- {WAPI_OUI, RSN_AKM_UNSPECIFIED, WAPI_AUTH_UNSPECIFIED},
- {WAPI_OUI, RSN_AKM_PSK, WAPI_AUTH_PSK},
-#endif /* BCMWAPI_WAI */
-
- {WPA_OUI, RSN_AKM_NONE, WPA_AUTH_NONE},
- {WPA_OUI, RSN_AKM_UNSPECIFIED, WPA_AUTH_UNSPECIFIED},
- {WPA_OUI, RSN_AKM_PSK, WPA_AUTH_PSK},
- };
-
- BCM_REFERENCE(sta_iswpa);
-
- for (i = 0; i < ARRAYSIZE(wpa_auth_tbl_match); i++) {
- if (!memcmp(akm, wpa_auth_tbl_match[i].oui, DOT11_OUI_LEN)) {
- if (wpa_auth_tbl_match[i].rsn_akm == akm[DOT11_OUI_LEN]) {
- *auth = wpa_auth_tbl_match[i].wpa_auth;
- return TRUE;
- }
- }
- }
- return FALSE;
-}
-
-/* map cipher suite to internal WSEC_XXXX */
-/* cs points 4 byte cipher suite, and only the type is used for non CCX ciphers */
-bool
-bcmwpa_cipher2wsec(uint8 *cipher, uint32 *wsec)
-{
-
-#ifdef BCMWAPI_WAI
- if (!memcmp(cipher, WAPI_OUI, DOT11_OUI_LEN)) {
- switch (WAPI_CSE_WPI_2_CIPHER(cipher[DOT11_OUI_LEN])) {
- case WAPI_CIPHER_NONE:
- *wsec = 0;
- break;
- case WAPI_CIPHER_SMS4:
- *wsec = SMS4_ENABLED;
- break;
- default:
- return FALSE;
- }
- return TRUE;
- }
-#endif /* BCMWAPI_WAI */
-
- switch (cipher[DOT11_OUI_LEN]) {
- case WPA_CIPHER_NONE:
- *wsec = 0;
- break;
- case WPA_CIPHER_WEP_40:
- case WPA_CIPHER_WEP_104:
- *wsec = WEP_ENABLED;
- break;
- case WPA_CIPHER_TKIP:
- *wsec = TKIP_ENABLED;
- break;
- case WPA_CIPHER_AES_CCM:
- /* fall through */
- case WPA_CIPHER_AES_GCM:
- /* fall through */
- case WPA_CIPHER_AES_GCM256:
- *wsec = AES_ENABLED;
- break;
-
-#ifdef BCMWAPI_WAI
- case WAPI_CIPHER_SMS4:
- *wsec = SMS4_ENABLED;
- break;
-#endif /* BCMWAPI_WAI */
-
- default:
- return FALSE;
- }
- return TRUE;
-}
-
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-/* map WPA/RSN cipher to internal WSEC */
-uint32
-bcmwpa_wpaciphers2wsec(uint32 wpacipher)
-{
- uint32 wsec = 0;
-
- switch (wpacipher) {
- case BCM_BIT(WPA_CIPHER_WEP_40):
- case BCM_BIT(WPA_CIPHER_WEP_104):
- wsec = WEP_ENABLED;
- break;
- case BCM_BIT(WPA_CIPHER_TKIP):
- wsec = TKIP_ENABLED;
- break;
- case BCM_BIT(WPA_CIPHER_AES_OCB):
- /* fall through */
- case BCM_BIT(WPA_CIPHER_AES_CCM):
- wsec = AES_ENABLED;
- break;
- case BCM_BIT(WPA_CIPHER_AES_GCM):
- /* fall through */
- case BCM_BIT(WPA_CIPHER_AES_GCM256):
- wsec = AES_ENABLED;
- break;
-
-#ifdef BCMWAPI_WAI
- case BCM_BIT(WAPI_CIPHER_SMS4):
- wsec = SMS4_ENABLED;
- break;
-#endif /* BCMWAPI_WAI */
-
- default:
- break;
- }
-
- return wsec;
-}
-
-uint32
-wlc_convert_rsn_to_wsec_bitmap(uint32 ap_cipher_mask)
-{
-
- uint32 ap_wsec = 0;
- uint32 tmp_mask = ap_cipher_mask;
- uint32 c;
-
- FOREACH_BIT(c, tmp_mask) {
- ap_wsec |= bcmwpa_wpaciphers2wsec(c);
- }
-
- return ap_wsec;
-}
-
-#else /* Not RSN_IE_INFO_STRUCT_RELOCATED */
-uint32
-bcmwpa_wpaciphers2wsec(uint8 wpacipher)
-{
- uint32 wsec = 0;
-
- switch (wpacipher) {
- case WPA_CIPHER_NONE:
- break;
- case WPA_CIPHER_WEP_40:
- case WPA_CIPHER_WEP_104:
- wsec = WEP_ENABLED;
- break;
- case WPA_CIPHER_TKIP:
- wsec = TKIP_ENABLED;
- break;
- case WPA_CIPHER_AES_OCB:
- /* fall through */
- case WPA_CIPHER_AES_CCM:
- wsec = AES_ENABLED;
- break;
- case WPA_CIPHER_AES_GCM:
- /* fall through */
- case WPA_CIPHER_AES_GCM256:
- wsec = AES_ENABLED;
- break;
-
-#ifdef BCMWAPI_WAI
- case WAPI_CIPHER_SMS4:
- wsec = SMS4_ENABLED;
- break;
-#endif /* BCMWAPI_WAI */
-
- default:
- break;
- }
-
- return wsec;
-}
-#endif /* RSN_IE_INFO_STRUCT_RELOCATED */
-
-bool
-bcmwpa_is_wpa_auth(uint32 auth)
-{
- if ((auth == WPA_AUTH_NONE) ||
- (auth == WPA_AUTH_UNSPECIFIED) ||
- (auth == WPA_AUTH_PSK))
- return TRUE;
- else
- return FALSE;
-}
-
-bool
-bcmwpa_includes_wpa_auth(uint32 auth)
-{
- if (auth & (WPA_AUTH_NONE |
- WPA_AUTH_UNSPECIFIED |
- WPA_AUTH_PSK))
- return TRUE;
- else
- return FALSE;
-}
-
-bool
-bcmwpa_is_rsn_auth(uint32 auth)
-{
- auth = auth & ~WPA2_AUTH_FT;
-
- if ((auth == WPA2_AUTH_UNSPECIFIED) ||
- (auth == WPA2_AUTH_PSK) ||
- (auth == BRCM_AUTH_PSK) ||
- (auth == WPA2_AUTH_1X_SHA256) ||
- (auth == WPA2_AUTH_PSK_SHA256) ||
- (auth == WPA3_AUTH_SAE_PSK) ||
- (auth == WPA3_AUTH_OWE) ||
- WPA2_AUTH_IS_FILS(auth) ||
- (auth == WPA3_AUTH_1X_SUITE_B_SHA256) ||
- (auth == WPA3_AUTH_1X_SUITE_B_SHA384) ||
- (auth == WPA3_AUTH_PSK_SHA384) ||
- (auth == WPA3_AUTH_DPP_AKM)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-bool
-bcmwpa_includes_rsn_auth(uint32 auth)
-{
- if (auth & (WPA2_AUTH_UNSPECIFIED |
- WPA2_AUTH_PSK |
- BRCM_AUTH_PSK | WPA2_AUTH_1X_SHA256 | WPA2_AUTH_PSK_SHA256 |
- WPA2_AUTH_IS_FILS(auth) | WPA3_AUTH_SAE_PSK | WPA3_AUTH_OWE |
- WPA3_AUTH_1X_SUITE_B_SHA256 | WPA3_AUTH_1X_SUITE_B_SHA384 |
- WPA3_AUTH_PSK_SHA384 | WPA3_AUTH_DPP_AKM))
- return TRUE;
- else
- return FALSE;
-}
-
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-/* decode unicast/multicast cipher in RSNIE */
-static int
-bcmwpa_decode_cipher_suite(rsn_ie_info_t *info, const uint8 **ptr_inc, uint ie_len, uint
- *remain_len, uint16 *p_count)
-{
- const wpa_suite_ucast_t *ucast;
- const wpa_suite_mcast_t *mcast;
- uint i;
-
- if (!(*remain_len)) {
- info->g_cipher = WPA_CIPHER_UNSPECIFIED;
- info->p_ciphers = WPA_P_CIPHERS_UNSPECIFIED;
- goto done; /* only have upto ver */
- }
- *ptr_inc += ie_len - *remain_len;
-
- if (*remain_len < sizeof(wpa_suite_mcast_t)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- mcast = (const wpa_suite_mcast_t *)*ptr_inc;
-
- if (IS_WPA_CIPHER(mcast->type)) {
- info->g_cipher = mcast->type;
- } else {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
-
- /* for rsn pairwise cipher suite */
- *ptr_inc += sizeof(wpa_suite_mcast_t);
- *remain_len -= sizeof(wpa_suite_mcast_t);
-
- if (!(*remain_len)) {
- info->p_ciphers = WPA_P_CIPHERS_UNSPECIFIED;
- info->sta_akm = WPA_CIPHER_UNSPECIFIED;
- goto done;
- }
-
- ucast = (const wpa_suite_ucast_t *)*ptr_inc;
-
- if ((*remain_len) < sizeof(ucast->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (!ucast->count.low && !ucast->count.high) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- *p_count = ltoh16_ua(&ucast->count);
- if (info->dev_type == DEV_STA && *p_count != 1u) {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
- if ((*remain_len) < (*p_count * WPA_SUITE_LEN + sizeof(ucast->count))) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (info->dev_type == DEV_STA) {
- if (IS_WPA_CIPHER(ucast->list[0].type)) {
- /* update the pairwise cipher */
- info->sta_cipher = ucast->list[0].type;
- } else {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
- } else {
- for (i = 0; i < *p_count; i++) {
- if (IS_WPA_CIPHER(ucast->list[i].type)) {
- info->p_ciphers |= BIT(ucast->list[i].type);
- info->rsn_p_ciphers = info->p_ciphers;
- } else {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
- }
- }
-
- /* update buffer ptr and remaining length */
- *ptr_inc += (*p_count * WPA_SUITE_LEN) + sizeof(ucast->count);
- *remain_len -= (*p_count * WPA_SUITE_LEN) + sizeof(ucast->count);
-
-done:
-
- if (info->parse_status == BCME_OK) {
- if (info->g_cipher == WPA_CIPHER_UNSPECIFIED) {
- info->g_cipher = WPA_CIPHER_AES_CCM;
- }
- if (info->p_ciphers == WPA_P_CIPHERS_UNSPECIFIED) {
- info->p_ciphers = BIT(WPA_CIPHER_AES_CCM);
- info->rsn_p_ciphers = info->p_ciphers;
- }
- }
-
- return info->parse_status;
-}
-/* sta_akm/sta_cipher must be set before this call */
-int
-bcmwpa_rsnie_eapol_key_len(rsn_ie_info_t *info)
-{
- info->pmk_len = bcmwpa_eapol_key_length(EAPOL_KEY_PMK, info->sta_akm, 0);
- info->kck_mic_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK_MIC, info->sta_akm, 0);
- info->kck_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK, info->sta_akm, 0);
- info->kek_len = bcmwpa_eapol_key_length(EAPOL_KEY_KEK, info->sta_akm, 0);
- info->tk_len = bcmwpa_eapol_key_length(EAPOL_KEY_TK, 0, info->sta_cipher);
- info->ptk_len = info->kck_len + info->kek_len + info->tk_len;
-#if defined(WL_FILS) && defined(WLFBT)
- info->kck2_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK2, info->sta_akm, 0);
- info->kek2_len = bcmwpa_eapol_key_length(EAPOL_KEY_KEK2, info->sta_akm, 0);
- if (WPA_IS_FILS_FT_AKM(info->sta_akm)) {
- info->ptk_len += (info->kck2_len + info->kek2_len);
- }
-#endif /* WL_FILS && WLFBT */
- return BCME_OK;
-}
-/* Extract and store information from WPA or RSN IEs
- *
- * called after either
- * -an association request has been built (STA),
- * - an association was received (AP)
- * - a probe request has been built (AP)
- * - a probe response was received (STA)
- *
- * All available information is extracted to be used for subsequent
- * bss pruning, association request validation, key descriptor compuation etc.
- *
- * To be expanded as needed.
- *
- * ie: RSN IE input
- * rsn_info: parsed information. Placed in either bsscfg for self, or scb for peer.
- * dev_type: STA_RSN or AP_RSN
- *
- * Return : parse status.
- * NOTE: the parse status is also saved in the the parse_status field.
- * NOTE 2 : the IE itself is copied at the end of the structure. Since there is
- * no reference to the osh available here, the allocation has to happen outside
- * and so the structure cannot be zeroed in this function.
- * For the STA, it should happen everytime.
- * For the AP, it should happen right after a new beacon/probe has been acquired.
- */
-
-int
-bcmwpa_parse_rsnie(const bcm_tlv_t *ie, rsn_ie_info_t *info, device_type_t dev_type)
-{
-
- const uint8 *ptr_inc = NULL;
- const wpa_suite_mcast_t *mcast;
- const wpa_suite_auth_key_mgmt_t *mgmt;
- const wpa_pmkid_list_t *pmkid_list;
- uint32 remain_len = 0, i;
- uint8 auth_ie_type;
- uint16 p_count = 0;
- uint16 akm_count;
-
- ASSERT(info != NULL);
-
- /* this function might be called from place where there
- * is no error detection.
- * e.g. fron the iem callback. Store status here.
- */
-
- info->parse_status = BCME_OK;
-
- if (!ie) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- /* For AP, do not zero this structure since there could be multiple
- * IEs. In that case, add to the existing
- * bits in field (ciphers, akms) as necessary.
- */
- if (dev_type == DEV_AP) {
- /* if already created, check device type */
- if (info->dev_type != DEV_NONE) {
- if (info->dev_type != DEV_AP) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
- }
- }
- info->dev_type = dev_type;
- ptr_inc = ie->data;
-
- /* decode auth IE (WPA vs RSN). Fill in the auth_ie_type and version.
- * Modify remain_len to indicate the position of the pointer.
- */
- /* NOTE the status field will be updated in this call */
- if (bcmwpa_decode_ie_type(ie, info, &remain_len, &auth_ie_type) != BCME_OK) {
- goto done;
- }
-
- /* decode multicast, unicast ciphers */
- if (bcmwpa_decode_cipher_suite(info, &ptr_inc, ie->len, &remain_len, &p_count) != BCME_OK) {
- goto done;
- }
-
- if (!(remain_len)) {
- info->akms = BIT(RSN_AKM_UNSPECIFIED);
- goto done;
- }
-
- mgmt = (const wpa_suite_auth_key_mgmt_t *)ptr_inc;
-
- if (remain_len < sizeof(mgmt->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- akm_count = ltoh16_ua(&mgmt->count);
-
- if (!akm_count) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- if (dev_type == DEV_STA && akm_count != 1) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- if ((remain_len) < (akm_count * WPA_SUITE_LEN + sizeof(mgmt->count))) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (dev_type == DEV_STA) {
- info->sta_akm = mgmt->list[0].type;
- }
- for (i = 0; i < akm_count; i++) {
- if (bcmwpa_is_valid_akm(mgmt->list[i].type) == BCME_OK) {
- ASSERT((mgmt->list[i].type) <
- (sizeof(info->akms) * NBBY));
- info->akms |= BIT(mgmt->list[i].type);
- }
- }
-
- /* save IE dependent values in their respective fields */
- if (dev_type == DEV_AP) {
- if (auth_ie_type == RSN_AUTH_IE) {
- info->rsn_akms = info->akms;
- } else if (auth_ie_type == WPA_AUTH_IE) {
- info->wpa_akms = info->akms;
- info->wpa_p_ciphers = info->p_ciphers;
- }
- }
-
- /* as a STA, at this point, we can compute the key descriptor version */
- if (dev_type == DEV_STA) {
- info->key_desc = wlc_calc_rsn_desc_version(info);
- /* For STA, we can set the auth ie */
- if (auth_ie_type == RSN_AUTH_IE) {
- info->auth_ie = info->rsn_ie;
- info->auth_ie_len = info->rsn_ie_len;
- } else {
- info->auth_ie = info->wpa_ie;
- info->auth_ie_len = info->wpa_ie_len;
- }
- }
-
- /* RSN AKM/cipher suite related EAPOL key length update */
- bcmwpa_rsnie_eapol_key_len(info);
-
- /* for rsn capabilities */
- ptr_inc += akm_count * WPA_SUITE_LEN + sizeof(mgmt->count);
- remain_len -= akm_count * WPA_SUITE_LEN + sizeof(mgmt->count);
-
- if (!(remain_len)) {
- goto done;
- }
- if (remain_len < RSN_CAP_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (ie->id == DOT11_MNG_RSN_ID) {
- info->caps = ltoh16_ua(ptr_inc);
- }
-
- /* check if AKMs require MFP capable to be set */
- if ((info->akms & RSN_MFPC_AKM_MASK) && !(info->caps & RSN_CAP_MFPC)) {
- /* NOTE: Acting as WPA3 CTT testbed device, it requires to send assoc request frame
- with user provided mfp value as is. So should not return error here.
- */
-#ifndef WPA3_CTT
- info->parse_status = BCME_EPERM;
- goto done;
-#endif /* WPA3_CTT */
- }
-
- /* for rsn PMKID */
- ptr_inc += RSN_CAP_LEN;
- remain_len -= RSN_CAP_LEN;
-
- if (!(remain_len)) {
- goto done;
- }
-
- /* here's possible cases after RSN_CAP parsed
- * a) pmkid_count 2B(00 00)
- * b) pmkid_count 2B(00 00) + BIP 4B
- * c) pmkid_count 2B(non zero) + pmkid_count * 16B
- * d) pmkid_count 2B(non zero) + pmkid_count * 16B + BIP 4B
- */
-
- /* pmkids_offset set to
- * 1) if pmkid_count field(2B) present, point to first PMKID offset in the RSN ID
- * no matter what pmkid_count value is. (true, even if pmkid_count == 00 00)
- * 2) if pmkid_count field(2B) not present, it shall be zero.
- */
-
- pmkid_list = (const wpa_pmkid_list_t*)ptr_inc;
-
- if ((remain_len) < sizeof(pmkid_list->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- info->pmkid_count = (uint8)ltoh16_ua(&pmkid_list->count);
- ptr_inc += sizeof(pmkid_list->count);
- remain_len -= sizeof(pmkid_list->count);
-
- if (remain_len < (uint32)(info->pmkid_count * WPA2_PMKID_LEN)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- info->pmkids_offset = ie->len + TLV_HDR_LEN - remain_len;
- /* for rsn group management cipher suite */
- ptr_inc += info->pmkid_count * WPA2_PMKID_LEN;
- remain_len -= info->pmkid_count * WPA2_PMKID_LEN;
-
- if (!(remain_len)) {
- goto done;
- }
- /*
- * from WPA2_Security_Improvements_Test_Plan_v1.0
- * 4.2.4 APUT RSNE bounds verification using WPA2-PSK
- * May content RSNE extensibile element ay this point
- */
- if (remain_len < sizeof(wpa_suite_mcast_t)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- mcast = (const wpa_suite_mcast_t *)ptr_inc;
- if (IS_VALID_BIP_CIPHER((rsn_cipher_t)mcast->type)) {
- info->g_mgmt_cipher = (rsn_cipher_t)mcast->type;
- }
-
-done:
- return info->parse_status;
-}
-
-/* Determine if the IE is of WPA or RSN type. Decode
- * up to version field. Modify the remaining len parameter to
- * indicate where the next field is.
- * Store and return error status.
- */
-
-int
-bcmwpa_decode_ie_type(const bcm_tlv_t *ie, rsn_ie_info_t *info, uint32 *remaining,
- uint8 *type)
-{
- const uint8 * ptr_inc = (const uint8 *)ie->data;
- uint32 remain_len = ie->len;
- uint8 version, version_len;
-
- if (ie->id == DOT11_MNG_WPA_ID) {
- /* min len check */
- if (remain_len < WPA_IE_FIXED_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- /* WPA IE */
- if (memcmp(WPA_OUI, ie->data, WPA_OUI_LEN)) {
- /* bad OUI */
- info->parse_status = BCME_BADARG;
- goto done;
- }
- ptr_inc += WPA_OUI_LEN;
- if (*ptr_inc == WPA_OUI_TYPE) {
- *type = WPA_AUTH_IE;
- } else if (*ptr_inc == WFA_OUI_TYPE_OSEN) {
- *type = OSEN_AUTH_IE;
- }
- else {
- /* wrong type */
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- ptr_inc ++;
- remain_len -= WPA_OUI_LEN + 1u;
- version_len = WPA_VERSION_LEN;
- }
- else if (ie->id == DOT11_MNG_RSN_ID) {
- if (remain_len < WPA2_VERSION_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- /* RSN IE */
- *type = RSN_AUTH_IE;
- version_len = WPA2_VERSION_LEN;
- } else {
- printf("IE ID %d\n", ie->id);
- /* TODO : add support for CCX, WAPI ? */
- info->parse_status = BCME_UNSUPPORTED;
- goto done;
- }
- info->auth_ie_type |= *type;
- /* mask down to uint8 for Windows build */
- version = 0xff & ltoh16_ua(ptr_inc);
- if (version > MAX_RSNE_SUPPORTED_VERSION) {
- info->parse_status = BCME_UNSUPPORTED;
- goto done;
- }
-
- info->version = (uint8)version;
- *remaining = remain_len - version_len;
-done:
- return info->parse_status;
-}
-
-/* rsn info allocation management.
- *
- * In some cases, the rsn ie info structures are embedded in the scan results
- * which can be shared by different lists.
- * To keep track of their allocation, we use a reference counter.
- * The counter is incremented on demand by rsn_ie_info_add_ref()
- * at the time the reference is shared.
- * It is decremented in rsn_ie_info_rel_ref
- * When ref_count gets to 0, bcmwpa_rsn_ie_info_free_mem
- * is called to free the whole structure.
- */
-
-/* free rsn_ie and wpa_ie, if any, and zero the rsn_info */
-void
-bcmwpa_rsn_ie_info_reset(rsn_ie_info_t *rsn_info, osl_t *osh)
-{
- uint8 ref_count;
- if (rsn_info == NULL) {
- return;
- }
- ref_count = rsn_info->ref_count;
- MFREE(osh, rsn_info->rsn_ie, rsn_info->rsn_ie_len);
- MFREE(osh, rsn_info->wpa_ie, rsn_info->wpa_ie_len);
- MFREE(osh, rsn_info->rsnxe, rsn_info->rsnxe_len);
- bzero(rsn_info, sizeof(*rsn_info));
- rsn_info->ref_count = ref_count;
-
-}
-
-static
-void bcmwpa_rsn_ie_info_free_mem(rsn_ie_info_t **rsn_info, osl_t *osh)
-{
- bcmwpa_rsn_ie_info_reset(*rsn_info, osh);
- MFREE(osh, *rsn_info, sizeof(**rsn_info));
- *rsn_info = NULL;
-}
-
-void bcmwpa_rsn_ie_info_rel_ref(rsn_ie_info_t **rsn_info, osl_t *osh)
-{
-
- if (rsn_info == NULL || *rsn_info == NULL) {
- return;
- }
-
- /* already freed ? */
- if ((*rsn_info)->ref_count == 0) {
- ASSERT(0);
- return;
- }
- /* decrement ref count */
- (*rsn_info)->ref_count -= 1;
- /* clear reference. */
- if ((*rsn_info)->ref_count > 0) {
- *rsn_info = NULL;
- return;
- }
- /* free memory and clear reference */
- bcmwpa_rsn_ie_info_free_mem(rsn_info, osh);
-}
-
-int
-bcmwpa_rsn_ie_info_add_ref(rsn_ie_info_t *rsn_info)
-{
- int status = BCME_OK;
- if (rsn_info == NULL) {
- goto done;
- }
- if (rsn_info->ref_count == 0) {
- /* don't increase from 0, which means this structure has been freed earlier.
- * That reference should not exist anymore.
- */
- ASSERT(0);
- status = BCME_BADARG;
- goto done;
- }
- rsn_info->ref_count++;
-done:
- return status;
-}
-
-#else /* Not RSN_IE_INFO_STRUCT_RELOCATED */
-
-int
-bcmwpa_parse_rsnie(const bcm_tlv_t *ie, rsn_ie_info_t *info, device_type_t dev_type)
-{
-
- const uint8 *ptr_inc = NULL;
- const wpa_suite_ucast_t *ucast;
- const wpa_suite_mcast_t *mcast;
- const wpa_suite_auth_key_mgmt_t *mgmt;
- const wpa_pmkid_list_t *pmkid_list;
- uint32 remain_len = 0, i;
-
- ASSERT(info != NULL);
-
- /* this function might be called from place where there
- * is no error detection.
- * e.g. fron the iem callback. Store status here.
- */
-
- info->parse_status = BCME_OK;
-
- if (!ie) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- /* For AP, do not zero this structure since there could be multiple
- * IEs. In that case, add to the existing
- * bits in field (ciphers, akms) as necessary.
- */
- if (dev_type != DEV_AP) {
- bzero(info, sizeof(*info));
- } else {
- /* if already created, check device type */
- if (info->dev_type != DEV_NONE) {
- if (info->dev_type != DEV_AP) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
- }
- }
- info->dev_type = dev_type;
- ptr_inc = ie->data;
-
- /* decode auth IE (WPA vs RSN). Fill in the auth_ie_type and version.
- * Modify remain_len to indicate the position of the pointer.
- */
- /* NOTE the status field will be updated in this call */
- if (bcmwpa_decode_ie_type(ie, info, &remain_len) != BCME_OK) {
- goto done;
- }
-
- if (!(remain_len)) {
- info->g_cipher = WPA_CIPHER_NONE;
- goto done; /* only have upto ver */
- }
- ptr_inc += ie->len - remain_len;
-
- if (remain_len < sizeof(wpa_suite_mcast_t)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- mcast = (const wpa_suite_mcast_t *)ptr_inc;
-
- if (IS_WPA_CIPHER(mcast->type)) {
- info->g_cipher = mcast->type;
- }
-
- /* for rsn pairwise cipher suite */
- ptr_inc += sizeof(wpa_suite_mcast_t);
- remain_len -= sizeof(wpa_suite_mcast_t);
-
- if (!(remain_len)) {
- goto done;
- }
-
- ucast = (const wpa_suite_ucast_t *)ptr_inc;
-
- if ((remain_len) < sizeof(ucast->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (!ucast->count.low && !ucast->count.high) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- info->p_count = (uint8)ltoh16_ua(&ucast->count);
-
- if (dev_type == DEV_STA && info->p_count != 1) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
- if ((remain_len) < (info->p_count * WPA_SUITE_LEN + sizeof(ucast->count))) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (IS_WPA_CIPHER(ucast->list[0].type)) {
- /* update the pairwise cipher */
- /* set cipher to invald value */
- if (dev_type == DEV_STA) {
- info->sta_cipher = ucast->list[0].type;
- } else {
- for (i = 0; i < info->p_count; i++) {
- if (IS_WPA_CIPHER(ucast->list[i].type)) {
- info->p_ciphers |= BIT(ucast->list[i].type);
- } else {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
- }
- }
- } else {
- info->parse_status = BCME_BAD_IE_DATA;
- goto done;
- }
-
- /* for rsn AKM authentication */
- ptr_inc += info->p_count * WPA_SUITE_LEN + sizeof(ucast->count);
- remain_len -= (info->p_count * WPA_SUITE_LEN + sizeof(ucast->count));
-
- mgmt = (const wpa_suite_auth_key_mgmt_t *)ptr_inc;
-
- if (remain_len < sizeof(mgmt->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- info->akm_count = (uint8)ltoh16_ua(&mgmt->count);
-
- if (!info->akm_count) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- if (dev_type == DEV_STA && info->akm_count != 1) {
- info->parse_status = BCME_BADARG;
- goto done;
- }
-
- if ((remain_len) < (info->akm_count * WPA_SUITE_LEN + sizeof(mgmt->count))) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (dev_type == DEV_STA) {
- info->sta_akm = mgmt->list[0].type;
- }
- for (i = 0; i < info->akm_count; i++) {
- if (bcmwpa_is_valid_akm(mgmt->list[i].type) == BCME_OK) {
- ASSERT((mgmt->list[i].type) <
- (sizeof(info->akms) * NBBY));
- info->akms |= BIT(mgmt->list[i].type);
- }
- }
-
- /* RSN AKM/cipher suite related EAPOL key length update */
- info->pmk_len = bcmwpa_eapol_key_length(EAPOL_KEY_PMK, info->sta_akm, 0);
- info->kck_mic_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK_MIC, info->sta_akm, 0);
- info->kck_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK, info->sta_akm, 0);
- info->kek_len = bcmwpa_eapol_key_length(EAPOL_KEY_KEK, info->sta_akm, 0);
- info->tk_len = bcmwpa_eapol_key_length(EAPOL_KEY_TK, 0, info->sta_cipher);
- info->ptk_len = info->kck_mic_len + info->kek_len + info->tk_len;
-#if defined(WL_FILS) && defined(WLFBT)
- info->kck2_len = bcmwpa_eapol_key_length(EAPOL_KEY_KCK2, info->sta_akm, 0);
- info->kek2_len = bcmwpa_eapol_key_length(EAPOL_KEY_KEK2, info->sta_akm, 0);
-#endif /* WL_FILS && WLFBT */
-
- /* for rsn capabilities */
- ptr_inc += info->akm_count * WPA_SUITE_LEN + sizeof(mgmt->count);
- remain_len -= info->akm_count * WPA_SUITE_LEN + sizeof(mgmt->count);
-
- /* as a STA, at this point, we can compute the key descriptor version */
- if (dev_type == DEV_STA) {
- info->key_desc = wlc_calc_rsn_desc_version(info);
- }
-
- if (!(remain_len)) {
- goto done;
- }
- if (remain_len < RSN_CAP_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- if (ie->id == DOT11_MNG_RSN_ID) {
- info->caps = ltoh16_ua(ptr_inc);
- }
-
- /* for WFA If MFP required, check that we are using a SHA256 AKM
- * or higher and nothing else.
- * In case MFP Required and MFP Capable do not enforce check of AKM.
- */
- if ((info->caps & RSN_CAP_MFPR) && !(info->akms & (1u << RSN_AKM_PSK))) {
- if ((info->akms & (AKM_SHA256_MASK | AKM_SHA384_MASK)) == 0 ||
- (info->akms & ~(AKM_SHA256_MASK | AKM_SHA384_MASK))) {
- info->parse_status = BCME_EPERM;
- goto done;
- }
- }
-
- /* check if AKMs require MFP capable to be set */
- if ((info->akms & RSN_MFPC_AKM_MASK) && !(info->caps & RSN_CAP_MFPC)) {
- info->parse_status = BCME_EPERM;
- goto done;
- }
-
- /* for rsn PMKID */
- ptr_inc += RSN_CAP_LEN;
- remain_len -= RSN_CAP_LEN;
-
- if (!(remain_len)) {
- goto done;
- }
-
- pmkid_list = (const wpa_pmkid_list_t*)ptr_inc;
-
- if ((remain_len) < sizeof(pmkid_list->count)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- info->pmkid_count = (uint8)ltoh16_ua(&pmkid_list->count);
- ptr_inc += sizeof(pmkid_list->count);
- remain_len -= sizeof(pmkid_list->count);
-
- if (info->pmkid_count) {
- if (remain_len < (uint32)(info->pmkid_count * WPA2_PMKID_LEN)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- info->pmkids_offset = ie->len + TLV_HDR_LEN - remain_len;
- /* for rsn group management cipher suite */
- ptr_inc += info->pmkid_count * WPA2_PMKID_LEN;
- remain_len -= info->pmkid_count * WPA2_PMKID_LEN;
- }
-
- if (!(remain_len)) {
- goto done;
- }
- /*
- * from WPA2_Security_Improvements_Test_Plan_v1.0
- * 4.2.4 APUT RSNE bounds verification using WPA2-PSK
- * May content RSNE extensibile element ay this point
- */
- if (remain_len < sizeof(wpa_suite_mcast_t)) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
-
- mcast = (const wpa_suite_mcast_t *)ptr_inc;
- if (IS_VALID_BIP_CIPHER((rsn_cipher_t)mcast->type)) {
- info->g_mgmt_cipher = (rsn_cipher_t)mcast->type;
- }
-
-done:
- return info->parse_status;
-}
-
-/* Determine if the IE is of WPA or RSN type. Decode
- * up to version field. Modify the remaining len parameter to
- * indicate where the next field is.
- * Store and return error status.
- */
-
-int
-bcmwpa_decode_ie_type(const bcm_tlv_t *ie, rsn_ie_info_t *info, uint32 *remaining)
-{
- const uint8 * ptr_inc = (const uint8 *)ie->data;
- uint32 remain_len = ie->len;
- uint8 version, version_len;
-
- if (ie->id == DOT11_MNG_WPA_ID) {
- /* min len check */
- if (remain_len < WPA_IE_FIXED_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- /* WPA IE */
- if (memcmp(WPA_OUI, ie->data, WPA_OUI_LEN)) {
- /* bad OUI */
- info->parse_status = BCME_BADARG;
- goto done;
- }
- ptr_inc += WPA_OUI_LEN;
- if (*ptr_inc != WPA_OUI_TYPE) {
- /* wrong type */
- info->parse_status = BCME_BADARG;
- goto done;
- }
- ptr_inc ++;
- remain_len -= WPA_OUI_LEN + 1u;
- info->auth_ie_type |= WPA_AUTH_IE;
- version_len = WPA_VERSION_LEN;
- }
- else if (ie->id == DOT11_MNG_RSN_ID) {
- if (remain_len < WPA2_VERSION_LEN) {
- info->parse_status = BCME_BADLEN;
- goto done;
- }
- /* RSN IE */
- info->auth_ie_type |= RSN_AUTH_IE;
- version_len = WPA2_VERSION_LEN;
- } else {
- /* TODO : add support for CCX, WAPI ? */
- info->parse_status = BCME_UNSUPPORTED;
- goto done;
- }
-
- /* mask down to uint8 for Windows build */
- version = 0xff & ltoh16_ua(ptr_inc);
- if (version > MAX_RSNE_SUPPORTED_VERSION) {
- info->parse_status = BCME_UNSUPPORTED;
- goto done;
- }
-
- info->version = (uint8)version;
- *remaining = remain_len - version_len;
-done:
- return info->parse_status;
-}
-
-#endif /* RSN_IE_INFO_STRUCT_RELOCATED */
-
-/* return the key descriptor version based on the AKM suite
- * applicable only for STA with RSN
- */
-static uint16
-wlc_calc_rsn_desc_version(const rsn_ie_info_t *rsn_info)
-{
- uint16 key_desc_ver = WPA_KEY_DESC_V0;
- uint8 akm;
-
- ASSERT(rsn_info != NULL);
- ASSERT(rsn_info->dev_type == DEV_STA);
- akm = rsn_info->sta_akm;
-
- /* Refer Draft 802.11REVmd_D1.0.pdf Section 12.7.2 */
- if ((akm == RSN_AKM_UNSPECIFIED) ||
- (akm == RSN_AKM_PSK)) {
- if ((rsn_info->sta_cipher == WPA_CIPHER_TKIP) ||
- (rsn_info->sta_cipher == WPA_CIPHER_NONE)) {
- key_desc_ver = WPA_KEY_DESC_V1;
- } else if ((rsn_info->sta_cipher != WPA_CIPHER_TKIP) ||
- (rsn_info->g_cipher != WPA_CIPHER_TKIP)) {
- key_desc_ver = WPA_KEY_DESC_V2;
- }
- } else if ((akm == RSN_AKM_FBT_1X) ||
- (akm == RSN_AKM_FBT_PSK) ||
- (akm == RSN_AKM_SHA256_1X) ||
- (akm == RSN_AKM_SHA256_PSK)) {
- key_desc_ver = WPA_KEY_DESC_V3;
- }
- return key_desc_ver;
-}
-
-/* get EAPOL key length based on RSN IE AKM/Cipher(unicast) suite
- * key: EAPOL key type
- * akm: RSN AKM suite selector
- * cipher: RSN unicast cipher suite selector
- * return: key length found in matching key_length_entry table
- */
-uint8
-bcmwpa_eapol_key_length(eapol_key_type_t key, rsn_akm_t akm, rsn_cipher_t cipher)
-{
- uint i;
- uint8 key_length = 0;
- uint8 suite;
- const key_length_entry_t *key_entry = NULL;
-
- if (key == EAPOL_KEY_TK) {
- suite = cipher;
- } else {
- suite = akm;
- }
- for (i = 0; i < ARRAYSIZE(eapol_key_lookup_tbl); i++) {
- if (eapol_key_lookup_tbl[i].key == key) {
- key_entry = eapol_key_lookup_tbl[i].key_entry;
- break;
- }
- }
-
- if (key_entry) {
- i = 0;
- do {
- if (key_entry[i].suite == suite || key_entry[i].suite == 0) {
- key_length = key_entry[i].len;
- break;
- }
- i++;
- } while (i > 0);
- }
-
- return key_length;
-}
-
-/* check if RSM AKM suite is valid */
-static int bcmwpa_is_valid_akm(const rsn_akm_t akm)
-{
- uint i = 0;
- for (i = 0; i < ARRAYSIZE(rsn_akm_lookup_tbl); i++) {
- if (akm == rsn_akm_lookup_tbl[i].rsn_akm) {
- return BCME_OK;
- }
- }
- return BCME_ERROR;
-}
-
-/* checking cipher suite selector restriction based on AKM */
-int
-bcmwpa_rsn_akm_cipher_match(rsn_ie_info_t *rsn_info)
-{
- uint i;
- const rsn_akm_cipher_match_entry_t *p_entry = NULL;
-
- for (i = 0; i < ARRAYSIZE(rsn_akm_cipher_match_table); i++) {
- /* akm match */
- if (rsn_info->sta_akm == rsn_akm_cipher_match_table[i].akm_type) {
- p_entry = &rsn_akm_cipher_match_table[i];
- break;
- }
- }
-
- if (p_entry) {
- /* unicast cipher match */
- if (!(rsn_info->p_ciphers & p_entry->u_cast)) {
- return BCME_UNSUPPORTED;
- }
- /* multicast cipher match */
- if (!(BCM_BIT(rsn_info->g_cipher) & p_entry->m_cast)) {
- return BCME_UNSUPPORTED;
- }
- /* group management cipher match */
- if (!(BCM_BIT(rsn_info->g_mgmt_cipher) & p_entry->g_mgmt)) {
- return BCME_UNSUPPORTED;
- }
- }
- return BCME_OK;
-}
-
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL)
-uint8 bcmwpa_find_group_mgmt_algo(rsn_cipher_t g_mgmt_cipher)
-{
- uint8 i;
- uint8 algo = CRYPTO_ALGO_BIP;
-
- for (i = 0; i < ARRAYSIZE(group_mgmt_cipher_algo); i++) {
- if ((group_mgmt_cipher_algo[i].g_mgmt_cipher == g_mgmt_cipher)) {
- algo = group_mgmt_cipher_algo[i].bip_algo;
- break;
- }
- }
-
- return algo;
-}
-#endif /* defined(BCMSUP_PSK) || defined(BCMSUPPL) */
-
-#if defined(WL_BAND6G)
-bool
-bcmwpa_is_invalid_6g_akm(const rsn_akm_mask_t akms_bmp)
-{
- if (akms_bmp & rsn_akm_6g_inval_mask) {
- return TRUE;
- }
- return FALSE;
-}
-
-bool
-bcmwpa_is_invalid_6g_cipher(const rsn_ciphers_t ciphers_bmp)
-{
- if (ciphers_bmp & cipher_6g_inval_mask) {
- return TRUE;
- }
- return FALSE;
-}
-#endif /* WL_BAND6G */
-
-/*
- * bcmwpa_get_algo_key_len returns the key_length for the algorithm.
- * API : bcm_get_algorithm key length
- * input: algo: Get the crypto algorithm.
- * km: Keymgmt information.
- * output: returns the key length and error status.
- * BCME_OK is valid else BCME_UNSUPPORTED if not supported
- */
-int
-bcmwpa_get_algo_key_len(uint8 algo, uint16 *key_len)
-{
- int err = BCME_OK;
-
- if (key_len == NULL) {
- return BCME_BADARG;
- }
-
- switch (algo) {
- case CRYPTO_ALGO_WEP1:
- *key_len = WEP1_KEY_SIZE;
- break;
-
- case CRYPTO_ALGO_TKIP:
- *key_len = TKIP_KEY_SIZE;
- break;
-
- case CRYPTO_ALGO_WEP128:
- *key_len = WEP128_KEY_SIZE;
- break;
-
- case CRYPTO_ALGO_AES_CCM: /* fall through */
- case CRYPTO_ALGO_AES_GCM: /* fall through */
- case CRYPTO_ALGO_AES_OCB_MSDU : /* fall through */
- case CRYPTO_ALGO_AES_OCB_MPDU:
- *key_len = AES_KEY_SIZE;
- break;
-
-#ifdef BCMWAPI_WPI
- /* TODO: Need to double check */
- case CRYPTO_ALGO_SMS4:
- *key_len = SMS4_KEY_LEN + SMS4_WPI_CBC_MAC_LEN;
- break;
-#endif /* BCMWAPI_WPI */
-
- case CRYPTO_ALGO_BIP: /* fall through */
- case CRYPTO_ALGO_BIP_GMAC:
- *key_len = BIP_KEY_SIZE;
- break;
-
- case CRYPTO_ALGO_AES_CCM256: /* fall through */
- case CRYPTO_ALGO_AES_GCM256: /* fall through */
- case CRYPTO_ALGO_BIP_CMAC256: /* fall through */
- case CRYPTO_ALGO_BIP_GMAC256:
- *key_len = AES256_KEY_SIZE;
- break;
-
- case CRYPTO_ALGO_OFF:
- *key_len = 0;
- break;
-
-#if !defined(BCMCCX) && !defined(BCMEXTCCX)
- case CRYPTO_ALGO_NALG: /* fall through */
-#else
- case CRYPTO_ALGO_CKIP: /* fall through */
- case CRYPTO_ALGO_CKIP_MMH: /* fall through */
- case CRYPTO_ALGO_WEP_MMH: /* fall through */
- case CRYPTO_ALGO_PMK: /* fall through default */
-#endif /* !defined(BCMCCX) && !defined(BCMEXTCCX) */
- default:
- *key_len = 0;
- err = BCME_UNSUPPORTED;
- break;
- }
- return err;
-}
dhd_pub_t *dhd = (dhd_pub_t *)handle;
unsigned long flags;
wifi_adapter_info_t *adapter;
+ int wowl_dngldown = 0;
if (dhd == NULL) {
DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
return;
}
adapter = (wifi_adapter_info_t *)dhd->adapter;
+#ifdef WL_EXT_WOWL
+ wowl_dngldown = dhd_conf_wowl_dngldown(dhd);
+#endif
- if (dhd->busstate == DHD_BUS_SUSPEND && state == DBUS_STATE_DOWN) {
+ if ((dhd->busstate == DHD_BUS_SUSPEND && state == DBUS_STATE_DOWN) ||
+ (dhd->hostsleep && wowl_dngldown)) {
DBUSERR(("%s: switch state %d to %d\n", __FUNCTION__, state, DBUS_STATE_SLEEP));
state = DBUS_STATE_SLEEP;
}
}
DBUSTRACE(("%s: Exit\n", __FUNCTION__));
+ wifi_clr_adapter_status(adapter, WIFI_STATUS_BUS_DISCONNECTED);
if (net_attached) {
wifi_set_adapter_status(adapter, WIFI_STATUS_NET_ATTACHED);
wake_up_interruptible(&adapter->status_event);
dhd_dbus_advertise_bus_remove(bus->dhd);
dbus_detach(pub->bus);
pub->bus = NULL;
+ wifi_set_adapter_status(adapter, WIFI_STATUS_BUS_DISCONNECTED);
wake_up_interruptible(&adapter->status_event);
} else {
osh = pub->osh;
DBUSTRACE(("%s: Exit\n", __FUNCTION__));
}
+int
+dhd_bus_sleep(dhd_pub_t *dhdp, bool sleep, uint32 *intstatus)
+{
+ wifi_adapter_info_t *adapter = (wifi_adapter_info_t *)dhdp->adapter;
+ s32 timeout = -1;
+ int err = 0;
+
+ timeout = wait_event_interruptible_timeout(adapter->status_event,
+ wifi_get_adapter_status(adapter, WIFI_STATUS_BUS_DISCONNECTED),
+ msecs_to_jiffies(12000));
+ if (timeout <= 0) {
+ err = -1;
+ DBUSERR(("%s: bus disconnected timeout\n", __FUNCTION__));
+ }
+
+ return err;
+}
+
#ifdef LINUX_EXTERNAL_MODULE_DBUS
static int __init
/** functions called by the Linux kernel USB subsystem */
static struct usb_driver dbus_usbdev = {
- name: "dbus_usbdev",
+ name: "dbus_usbdev"BUS_TYPE,
probe: dbus_usbos_probe,
disconnect: dbus_usbos_disconnect,
id_table: devid_table,
usb->portnum, WIFI_STATUS_POWER_ON);
if (adapter == NULL) {
DBUSERR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
+ ret = -ENOMEM;
goto fail;
}
}
if (usbos_info->tx_pipe)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
+ usbos_info->maxps = usb_maxpacket(usbos_info->usb,
+ usbos_info->tx_pipe);
+#else
usbos_info->maxps = usb_maxpacket(usbos_info->usb,
usbos_info->tx_pipe, usb_pipeout(usbos_info->tx_pipe));
+#endif /* #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 19, 0)) */
INIT_LIST_HEAD(&usbos_info->req_rxfreeq);
INIT_LIST_HEAD(&usbos_info->req_txfreeq);
{
return &g_probe_info.usb->dev;
}
-#endif /* LINUX */
\ No newline at end of file
+#endif /* LINUX */
} while (0)
#define DHD_TXFL_WAKE_LOCK_TIMEOUT(pub, val) \
do { \
- printf("call pm_wake_timeout enable\n"); \
+ printf("call txfl_wake_timeout enable\n"); \
dhd_txfl_wake_lock_timeout(pub, val); \
} while (0)
#define DHD_TXFL_WAKE_UNLOCK(pub) \
#define DHD_OS_OOB_IRQ_WAKE_UNLOCK(pub) dhd_os_oob_irq_wake_unlock(pub)
#endif /* BCMPCIE_OOB_HOST_WAKE */
+#ifndef DHD_PACKET_TIMEOUT_MS
#define DHD_PACKET_TIMEOUT_MS 500
+#endif
#define DHD_EVENT_TIMEOUT_MS 1500
#define SCAN_WAKE_LOCK_TIMEOUT 10000
+#ifndef MAX_TX_TIMEOUT
#define MAX_TX_TIMEOUT 500
+#endif
/* Enum for IOCTL recieved status */
typedef enum dhd_ioctl_recieved_status
#ifdef DBG_PKT_MON
/* Enable DHD PKT MON spin lock/unlock */
-#define DHD_PKT_MON_LOCK(lock, flags) (flags) = osl_mutex_lock(lock)
-#define DHD_PKT_MON_UNLOCK(lock, flags) osl_mutex_unlock(lock, (flags))
+#define DHD_PKT_MON_LOCK(lock, flags) (flags) = osl_spin_lock(lock)
+#define DHD_PKT_MON_UNLOCK(lock, flags) osl_spin_unlock(lock, (flags))
#endif /* DBG_PKT_MON */
#ifdef DHD_PKT_LOGGING
#define DHD_VFS_UNLINK(dir, b, c) 0
static INLINE struct file *dhd_filp_open(const char *filename, int flags, int mode)
- { return NULL; }
+ { printf("%s: DHD_SUPPORT_VFS_CALL not defined\n", __FUNCTION__); return NULL; }
static INLINE int dhd_filp_close(void *image, void *id)
{ return 0; }
static INLINE int dhd_i_size_read(const struct inode *inode)
chip == BCM4334_CHIP_ID || chip == BCM43340_CHIP_ID ||
chip == BCM43341_CHIP_ID || chip == BCM4324_CHIP_ID ||
chip == BCM4335_CHIP_ID || chip == BCM4339_CHIP_ID ||
- chip == BCM4354_CHIP_ID || chip == BCM4356_CHIP_ID ||
chip == BCM43143_CHIP_ID || chip == BCM43242_CHIP_ID ||
chip == BCM43569_CHIP_ID) {
return false;
#endif
#ifdef BCMSDIO
-bool
+static void
dhd_conf_disable_slpauto(dhd_pub_t *dhd)
{
uint chip = dhd->conf->chip;
chip == BCM43430_CHIP_ID ||
chip == BCM4345_CHIP_ID || chip == BCM43454_CHIP_ID ||
chip == BCM4359_CHIP_ID) {
- return false;
+ dhd_slpauto = FALSE;
}
-
- return true;
+ CONFIG_MSG("dhd_slpauto = %d\n", dhd_slpauto);
}
#endif
return;
}
-
#endif /* DHD_LINUX_STD_FW_API */
void
#endif
#ifdef DHD_LINUX_STD_FW_API
- // preprocess the filename to only left 'name'
dhd_conf_add_filepath(dhd, fw_path);
dhd_conf_add_filepath(dhd, nv_path);
dhd_conf_add_filepath(dhd, dhd->clm_path);
goto exit;
}
if (dhd->conf->insuspend & (NO_TXCTL_IN_SUSPEND | WOWL_IN_SUSPEND)) {
+ int wowl_dngldown = 0;
+#ifdef WL_EXT_WOWL
+ wowl_dngldown = dhd_conf_wowl_dngldown(dhd);
+#endif
if (cmd == WLC_SET_VAR) {
char *psleep = NULL;
- psleep = strstr(buf, "hostsleep");
- if (psleep) {
- *hostsleep_set = 1;
- memcpy(hostsleep_val, psleep+strlen("hostsleep")+1, sizeof(int));
+ if (wowl_dngldown) {
+ psleep = strstr(buf, "wowl_activate");
+ if (psleep) {
+ *hostsleep_set = 1;
+ memcpy(hostsleep_val, psleep+strlen("wowl_activate")+1, sizeof(int));
+ }
+ } else {
+ psleep = strstr(buf, "hostsleep");
+ if (psleep) {
+ *hostsleep_set = 1;
+ memcpy(hostsleep_val, psleep+strlen("hostsleep")+1, sizeof(int));
+ }
}
}
if (dhd->hostsleep && (!*hostsleep_set || *hostsleep_val)) {
return ret;
}
+
+int
+dhd_conf_wowl_dngldown(dhd_pub_t *dhd)
+{
+ int wowl_dngldown = 0;
+#ifdef BCMDBUS
+ uint insuspend = 0;
+ insuspend = dhd_conf_get_insuspend(dhd, ALL_IN_SUSPEND);
+ if ((insuspend & WOWL_IN_SUSPEND) && dhd_master_mode) {
+ wowl_dngldown = dhd->conf->wowl_dngldown;
+ }
+#endif
+
+ return wowl_dngldown;
+}
#endif
int
for(i=0; i<conf->pkt_filter_add.count; i++) {
dhd_conf_wowl_pattern(dhd, ifidx, TRUE, conf->pkt_filter_add.filter[i]);
}
+ CONFIG_MSG("wowl = 0x%x\n", conf->wowl);
dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl", conf->wowl, 0, FALSE);
- dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl_activate", 1, 0, FALSE);
+#ifdef BCMDBUS
+ CONFIG_MSG("wowl_dngldown = %d\n", conf->wowl_dngldown);
+ dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl_dngldown", conf->wowl_dngldown, 1, FALSE);
+#endif
dhd_conf_wowl_wakeind(dhd, ifidx, TRUE);
}
#endif
#ifdef WL_EXT_WOWL
if (insuspend & WOWL_IN_SUSPEND) {
dhd_conf_wowl_wakeind(dhd, ifidx, FALSE);
- dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl_activate", 0, 0, FALSE);
+// dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl_activate", 0, 0, FALSE);
dhd_conf_set_intiovar(dhd, ifidx, WLC_SET_VAR, "wowl", 0, 0, FALSE);
dhd_conf_wowl_pattern(dhd, ifidx, FALSE, "clr");
}
if (suspend) {
if (insuspend & (WOWL_IN_SUSPEND | NO_TXCTL_IN_SUSPEND)) {
-#ifdef BCMSDIO
uint32 intstatus = 0;
- int ret = 0;
-#endif
- int hostsleep = 2;
+ int ret = 0, hostsleep = 2, wowl_dngldown = 0;
#ifdef WL_EXT_WOWL
hostsleep = 1;
+ if ((insuspend & WOWL_IN_SUSPEND) && dhd_master_mode) {
+ dhd_conf_set_intiovar(dhd, 0, WLC_SET_VAR, "wowl_activate", 1, 0, FALSE);
+#ifdef BCMDBUS
+ wowl_dngldown = dhd->conf->wowl_dngldown;
#endif
- dhd_conf_set_intiovar(dhd, 0, WLC_SET_VAR, "hostsleep", hostsleep, 0, FALSE);
+ }
+#endif
+ if (!wowl_dngldown) {
+ dhd_conf_set_intiovar(dhd, 0, WLC_SET_VAR, "hostsleep", hostsleep, 0, FALSE);
+ }
#ifdef BCMSDIO
ret = dhd_bus_sleep(dhd, TRUE, &intstatus);
- CONFIG_TRACE("ret = %d, intstatus = 0x%x\n", ret, intstatus);
#endif
+#ifdef BCMPCIE
+ ret = dhd_bus_sleep(dhd, TRUE, NULL);
+#endif
+#ifdef BCMDBUS
+ if (wowl_dngldown) {
+ ret = dhd_bus_sleep(dhd, TRUE, NULL);
+ }
+#endif
+ CONFIG_MSG("ret = %d, intstatus = 0x%x\n", ret, intstatus);
}
} else {
if (insuspend & (WOWL_IN_SUSPEND | NO_TXCTL_IN_SUSPEND)) {
CONFIG_MSG("dhd_doflow = %d\n", dhd_doflow);
}
else if (!strncmp("dhd_slpauto=", full_param, len_param)) {
- if (!strncmp(data, "0", 1))
- dhd_slpauto = FALSE;
- else if (dhd_conf_disable_slpauto(dhd))
+ if (!strncmp(data, "0", 1)) {
+ dhd_conf_disable_slpauto(dhd);
+ } else
dhd_slpauto = TRUE;
CONFIG_MSG("dhd_slpauto = %d\n", dhd_slpauto);
}
conf->enq_hdr_pkt = (int)simple_strtol(data, NULL, 0);
CONFIG_MSG("enq_hdr_pkt = 0x%x\n", conf->enq_hdr_pkt);
}
+ else if (!strncmp("aspm=", full_param, len_param)) {
+ conf->aspm = (int)simple_strtol(data, NULL, 0);
+ CONFIG_MSG("aspm = %d\n", conf->aspm);
+ }
+ else if (!strncmp("l1ss=", full_param, len_param)) {
+ conf->l1ss = (int)simple_strtol(data, NULL, 0);
+ CONFIG_MSG("l1ss = %d\n", conf->l1ss);
+ }
else
return false;
conf->wowl = (int)simple_strtol(data, NULL, 0);
CONFIG_MSG("wowl = 0x%x\n", conf->wowl);
}
+#ifdef BCMDBUS
+ else if (!strncmp("wowl_dngldown=", full_param, len_param)) {
+ conf->wowl_dngldown = (int)simple_strtol(data, NULL, 0);
+ CONFIG_MSG("wowl_dngldown = 0x%x\n", conf->wowl_dngldown);
+ }
+#endif
#endif
else if (!strncmp("rekey_offload=", full_param, len_param)) {
if (!strncmp(data, "1", 1))
}
}
+
+static void
+dhd_conf_set_ampdu_mpdu(dhd_pub_t *dhd)
+{
+ uint chip = dhd->conf->chip;
+ char ampdu_mpdu[32] = "ampdu_mpdu=";
+ int val = -1;
+
+ if (chip == BCM43362_CHIP_ID || chip == BCM4330_CHIP_ID ||
+ chip == BCM4334_CHIP_ID || chip == BCM43340_CHIP_ID ||
+ chip == BCM43341_CHIP_ID || chip == BCM4324_CHIP_ID ||
+ chip == BCM4335_CHIP_ID || chip == BCM4339_CHIP_ID ||
+ chip == BCM4354_CHIP_ID || chip == BCM4356_CHIP_ID ||
+ chip == BCM4371_CHIP_ID ||
+ chip == BCM43430_CHIP_ID ||
+ chip == BCM4345_CHIP_ID || chip == BCM43454_CHIP_ID ||
+ chip == BCM4359_CHIP_ID || chip == BCM43012_CHIP_ID) {
+ val = 16;
+ } else if (chip == BCM43751_CHIP_ID || chip == BCM43752_CHIP_ID) {
+ val = 32;
+ }
+
+ if (val > 0) {
+ snprintf(ampdu_mpdu+strlen(ampdu_mpdu), sizeof(ampdu_mpdu), "%d", val);
+ dhd_conf_set_wl_cmd(dhd, ampdu_mpdu, TRUE);
+ }
+}
+
+#if defined(SDIO_ISR_THREAD)
+static void
+dhd_conf_set_intr_extn(dhd_pub_t *dhd)
+{
+ uint chip = dhd->conf->chip;
+
+ if (chip == BCM43012_CHIP_ID ||
+ chip == BCM4335_CHIP_ID || chip == BCM4339_CHIP_ID ||
+ chip == BCM43454_CHIP_ID || chip == BCM4345_CHIP_ID ||
+ chip == BCM4354_CHIP_ID || chip == BCM4356_CHIP_ID ||
+ chip == BCM4345_CHIP_ID || chip == BCM4371_CHIP_ID ||
+ chip == BCM4359_CHIP_ID ||
+ chip == BCM43751_CHIP_ID || chip == BCM43752_CHIP_ID ||
+ chip == BCM4375_CHIP_ID) {
+ CONFIG_TRACE("enable intr_extn\n");
+ dhd->conf->intr_extn = TRUE;
+ }
+}
+#endif /* SDIO_ISR_THREAD */
#endif
+static void
+dhd_conf_set_txbf(dhd_pub_t *dhd)
+{
+ uint chip = dhd->conf->chip;
+
+ if (chip == BCM4354_CHIP_ID || chip == BCM4356_CHIP_ID ||
+ chip == BCM4371_CHIP_ID || chip == BCM4359_CHIP_ID ||
+ chip == BCM43569_CHIP_ID ||
+ chip == BCM43751_CHIP_ID || chip == BCM43752_CHIP_ID ||
+ chip == BCM4375_CHIP_ID) {
+ CONFIG_TRACE("enable txbf\n");
+ dhd_conf_set_intiovar(dhd, 0, WLC_SET_VAR, "txbf", 1, 0, FALSE);
+ }
+}
+
+static void
+dhd_conf_tput_improve(dhd_pub_t *dhd)
+{
+ struct dhd_conf *conf = dhd->conf;
+ uint chip = conf->chip;
+ uint chiprev = conf->chiprev;
+
+ if ((chip == BCM43430_CHIP_ID && chiprev == 2) ||
+ chip == BCM43012_CHIP_ID ||
+ chip == BCM4335_CHIP_ID || chip == BCM4339_CHIP_ID ||
+ chip == BCM43454_CHIP_ID || chip == BCM4345_CHIP_ID ||
+ chip == BCM4354_CHIP_ID || chip == BCM4356_CHIP_ID ||
+ chip == BCM4345_CHIP_ID || chip == BCM4371_CHIP_ID ||
+ chip == BCM43569_CHIP_ID || chip == BCM4359_CHIP_ID ||
+ chip == BCM43751_CHIP_ID || chip == BCM43752_CHIP_ID ||
+ chip == BCM4375_CHIP_ID) {
+ CONFIG_TRACE("enable tput parameters\n");
+#ifdef DHDTCPACK_SUPPRESS
+#ifdef BCMSDIO
+ conf->tcpack_sup_mode = TCPACK_SUP_REPLACE;
+#endif
+#endif
+#if defined(BCMSDIO) || defined(BCMPCIE)
+ dhd_rxbound = 128;
+ dhd_txbound = 64;
+#endif
+ conf->frameburst = 1;
+#ifdef BCMSDIO
+ conf->dhd_txminmax = -1;
+ conf->txinrx_thres = 128;
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+ conf->orphan_move = 1;
+#else
+ conf->orphan_move = 0;
+#endif
+ }
+}
+
#ifdef UPDATE_MODULE_NAME
#if defined(BCMSDIO) || defined(BCMPCIE)
static void
dhd_conf_preinit_ioctls_sta(dhd, 0);
dhd_conf_set_wl_cmd(dhd, wl_preinit, TRUE);
#if defined(BCMSDIO)
- if (conf->chip == BCM43751_CHIP_ID || conf->chip == BCM43752_CHIP_ID) {
- char ampdu_mpdu[] = "ampdu_mpdu=32";
- dhd_conf_set_wl_cmd(dhd, ampdu_mpdu, TRUE);
- } else {
- char ampdu_mpdu[] = "ampdu_mpdu=16";
- dhd_conf_set_wl_cmd(dhd, ampdu_mpdu, TRUE);
- }
+ dhd_conf_set_ampdu_mpdu(dhd);
#endif
#ifdef DHD_TPUT_PATCH
if (dhd->conf->mtu)
dhd_change_mtu(dhd, dhd->conf->mtu, 0);
#endif
- if (conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
- conf->chip == BCM4371_CHIP_ID || conf->chip == BCM4359_CHIP_ID ||
- conf->chip == BCM43569_CHIP_ID ||
- conf->chip == BCM43751_CHIP_ID || conf->chip == BCM43752_CHIP_ID ||
- conf->chip == BCM4375_CHIP_ID) {
- dhd_conf_set_intiovar(dhd, 0, WLC_SET_VAR, "txbf", 1, 0, FALSE);
- }
+ dhd_conf_set_txbf(dhd);
if (conf->chip == BCM4375_CHIP_ID) {
char he_cmd[] = "110=1, nmode=1, vhtmode=1, he=enab 1";
dhd_conf_set_wl_cmd(dhd, he_cmd, TRUE);
#endif
#endif
#ifdef BCMPCIE
- conf->bus_deepsleep_disable = 1;
+ conf->bus_deepsleep_disable = -1;
conf->flow_ring_queue_threshold = FLOW_RING_QUEUE_THRESHOLD;
conf->d2h_intr_method = -1;
conf->d2h_intr_control = -1;
+ conf->aspm = -1;
+ conf->l1ss = -1;
conf->enq_hdr_pkt = 0;
#endif
conf->dpc_cpucore = -1;
#ifdef WL_EXT_WOWL
dhd_master_mode = TRUE;
conf->wowl = WL_WOWL_NET|WL_WOWL_DIS|WL_WOWL_BCN;
+#ifdef BCMDBUS
+ conf->wowl_dngldown = 0;
+#endif
conf->insuspend |= (WOWL_IN_SUSPEND | NO_TXDATA_IN_SUSPEND);
#endif
if (conf->suspend_mode == PM_NOTIFIER || conf->suspend_mode == SUSPEND_MODE_2)
memset(conf->isam_enable, 0, sizeof(conf->isam_enable));
#endif
#if defined(SDIO_ISR_THREAD)
- if (conf->chip == BCM43012_CHIP_ID ||
- conf->chip == BCM4335_CHIP_ID || conf->chip == BCM4339_CHIP_ID ||
- conf->chip == BCM43454_CHIP_ID || conf->chip == BCM4345_CHIP_ID ||
- conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
- conf->chip == BCM4345_CHIP_ID || conf->chip == BCM4371_CHIP_ID ||
- conf->chip == BCM4359_CHIP_ID ||
- conf->chip == BCM43751_CHIP_ID || conf->chip == BCM43752_CHIP_ID ||
- conf->chip == BCM4375_CHIP_ID) {
- conf->intr_extn = TRUE;
- }
-#endif
- if ((conf->chip == BCM43430_CHIP_ID && conf->chiprev == 2) ||
- conf->chip == BCM43012_CHIP_ID ||
- conf->chip == BCM4335_CHIP_ID || conf->chip == BCM4339_CHIP_ID ||
- conf->chip == BCM43454_CHIP_ID || conf->chip == BCM4345_CHIP_ID ||
- conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
- conf->chip == BCM4345_CHIP_ID || conf->chip == BCM4371_CHIP_ID ||
- conf->chip == BCM43569_CHIP_ID || conf->chip == BCM4359_CHIP_ID ||
- conf->chip == BCM43751_CHIP_ID || conf->chip == BCM43752_CHIP_ID ||
- conf->chip == BCM4375_CHIP_ID) {
-#ifdef DHDTCPACK_SUPPRESS
-#ifdef BCMSDIO
- conf->tcpack_sup_mode = TCPACK_SUP_REPLACE;
-#endif
-#endif
-#if defined(BCMSDIO) || defined(BCMPCIE)
- dhd_rxbound = 128;
- dhd_txbound = 64;
-#endif
- conf->frameburst = 1;
-#ifdef BCMSDIO
- conf->dhd_txminmax = -1;
- conf->txinrx_thres = 128;
+ dhd_conf_set_intr_extn(dhd);
#endif
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
- conf->orphan_move = 1;
-#else
- conf->orphan_move = 0;
-#endif
- }
+ dhd_conf_tput_improve(dhd);
#ifdef DHD_TPUT_PATCH
if (conf->chip == BCM43751_CHIP_ID || conf->chip == BCM43752_CHIP_ID ||
conf->chip == BCM4375_CHIP_ID) {
init_waitqueue_head(&conf->event_complete);
#if defined(BCMSDIO) && defined(CUSTOMER_HW_AMLOGIC)
- dhd_slpauto = dhd_conf_disable_slpauto(dhd);
+ dhd_conf_disable_slpauto(dhd);
conf->txglom_mode = SDPCM_TXGLOM_CPY;
conf->rekey_offload = TRUE;
#endif
int d2h_intr_method;
int d2h_intr_control;
int enq_hdr_pkt;
+ int aspm;
+ int l1ss;
#endif
int dpc_cpucore;
int rxf_cpucore;
uint war;
#ifdef WL_EXT_WOWL
uint wowl;
+#ifdef BCMDBUS
+ uint wowl_dngldown;
+#endif
#endif
#ifdef GET_CUSTOM_MAC_FROM_CONFIG
char hw_ether[62];
int dhd_conf_suspend_resume_sta(dhd_pub_t *dhd, int ifidx, int suspend);
/* Add to adjust 802.1x priority */
extern void pktset8021xprio(void *pkt, int prio);
-#ifdef BCMSDIO
+#if defined(BCMSDIO) || defined(BCMPCIE) || defined(BCMDBUS)
extern int dhd_bus_sleep(dhd_pub_t *dhdp, bool sleep, uint32 *intstatus);
#endif
+#ifdef WL_EXT_WOWL
+int dhd_conf_wowl_dngldown(dhd_pub_t *dhd);
+#endif
#endif /* _dhd_config_ */
+++ /dev/null
-/*
- * Firmware trace handling on the DHD side. Kernel thread reads the trace data and writes
- * to the file and implements various utility functions.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- *
- * $Id$
- */
-
-#ifdef BCMINTERNAL
-
-#ifdef DHD_FWTRACE
-
-#include <typedefs.h>
-#include <osl.h>
-
-#include <bcmutils.h>
-#include <bcmendian.h>
-
-#include <dngl_stats.h>
-#include <dhd.h>
-#include <dhd_proto.h>
-#include <dhd_dbg.h>
-#include <dhd_debug.h>
-
-#include <dhd_fwtrace.h>
-
-static int fwtrace_write_to_file(uint8 *buf, uint16 buf_len, dhd_pub_t *dhdp);
-static int fwtrace_close_file(dhd_pub_t *dhdp);
-static int fwtrace_open_file(uint32 fw_trace_enabled, dhd_pub_t *dhdp);
-static fwtrace_buf_t *fwtrace_get_trace_data_ptr(dhd_pub_t *dhdp);
-static void fwtrace_free_trace_buf(dhd_pub_t *dhdp);
-
-typedef struct fwtrace_info {
- struct file *fw_trace_fp;
- int file_index;
- int part_index;
- int trace_buf_index;
- int trace_buf_count;
- uint16 overflow_counter;
-
- char trace_file[TRACE_FILE_NAME_LEN];
-
- fwtrace_buf_t *trace_data_ptr;
-
- uint16 prev_seq;
-
- uint32 fwtrace_enable; /* Enable firmware tracing and the
- * trace file management.
- */
- struct mutex fwtrace_lock; /* Synchronization between the
- * ioctl and the kernel thread.
- */
- dhd_dma_buf_t fwtrace_buf; /* firmware trace buffer */
-} fwtrace_info_t;
-
-int
-dhd_fwtrace_attach(dhd_pub_t *dhdp)
-{
- fwtrace_info_t *fwtrace_info;
-
- /* Allocate prot structure */
- if (!(fwtrace_info = (fwtrace_info_t *)VMALLOCZ(dhdp->osh, sizeof(*fwtrace_info)))) {
- DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
- return (BCME_NOMEM);
- }
-
- bzero(fwtrace_info, sizeof(*fwtrace_info));
- dhdp->fwtrace_info = fwtrace_info;
-
- mutex_init(&dhdp->fwtrace_info->fwtrace_lock);
-
- DHD_INFO(("allocated DHD fwtrace\n"));
-
- return BCME_OK;
-}
-
-int
-dhd_fwtrace_detach(dhd_pub_t *dhdp)
-{
- fwtrace_info_t *fwtrace_info;
-
- DHD_TRACE(("%s: %d\n", __FUNCTION__, __LINE__));
-
- if (!dhdp) {
- return BCME_OK;
- }
-
- if (!dhdp->fwtrace_info) {
- return BCME_OK;
- }
-
- fwtrace_info = dhdp->fwtrace_info;
-
- dhd_dma_buf_free(dhdp, &dhdp->fwtrace_info->fwtrace_buf);
-
- /* close the file if valid */
- if (!(IS_ERR_OR_NULL(dhdp->fwtrace_info->fw_trace_fp))) {
- (void) dhd_filp_close(dhdp->fwtrace_info->fw_trace_fp, 0);
- }
-
- mutex_destroy(&dhdp->fwtrace_info->fwtrace_lock);
-
- VMFREE(dhdp->osh, fwtrace_info, sizeof(*fwtrace_info));
-
- dhdp->fwtrace_info = NULL;
-
- DHD_INFO(("Deallocated DHD fwtrace_info\n"));
-
- return (BCME_OK);
-}
-
-uint16
-get_fw_trace_overflow_counter(dhd_pub_t *dhdp)
-{
- return (dhdp->fwtrace_info->overflow_counter);
-}
-
-void
-process_fw_trace_data(dhd_pub_t *dhdp)
-{
- fwtrace_info_t *fwtrace_info = dhdp->fwtrace_info;
- uint16 length;
- uint16 incoming_seq;
- uint32 trace_buf_index = fwtrace_info->trace_buf_index;
- fwtrace_buf_t * trace_buf;
- fwtrace_buf_t * curr_buf;
-
- mutex_lock(&fwtrace_info->fwtrace_lock);
-
- if (fwtrace_info->fw_trace_fp == NULL) {
- goto done;
- }
-
- if ((trace_buf = fwtrace_get_trace_data_ptr(dhdp)) == NULL) {
- goto done;
- }
-
- do {
- curr_buf = trace_buf + trace_buf_index;
-
- length = curr_buf->info.length;
- /* If the incoming length is 0, means nothing is updated by the firmware */
- if (length == 0) {
- break;
- }
-
- incoming_seq = curr_buf->info.seq_num;
-
- if (((uint16)(fwtrace_info->prev_seq + 1) != incoming_seq) &&
- length != sizeof(*curr_buf)) {
- DHD_ERROR(("*** invalid trace len idx = %u, length = %u, "
- "cur seq = %u, in-seq = %u \n",
- trace_buf_index, length,
- fwtrace_info->prev_seq, incoming_seq));
- break;
- }
-
- DHD_TRACE(("*** TRACE BUS: IDX:%d, in-seq:%d(prev-%d), ptr:%p(%llu), len:%d\n",
- trace_buf_index, incoming_seq, fwtrace_info->prev_seq,
- curr_buf, (uint64)curr_buf, length));
-
- /* Write trace data to a file */
- if (fwtrace_write_to_file((uint8 *) curr_buf, length, dhdp) != BCME_OK) {
- DHD_ERROR(("*** fwtrace_write_to_file has failed \n"));
- break;
- }
-
- /* Reset length after consuming the fwtrace data */
- curr_buf->info.length = 0;
-
- if ((fwtrace_info->prev_seq + 1) != incoming_seq) {
- DHD_ERROR(("*** seq mismatch, index = %u, length = %u, "
- "cur seq = %u, in-seq = %u \n",
- trace_buf_index, length,
- fwtrace_info->prev_seq, incoming_seq));
- }
- fwtrace_info->prev_seq = incoming_seq;
-
- trace_buf_index++;
- trace_buf_index &= (fwtrace_info->trace_buf_count - 1u);
- fwtrace_info->trace_buf_index = trace_buf_index;
- } while (true);
-
-done:
- mutex_unlock(&fwtrace_info->fwtrace_lock);
- return;
-}
-
-/*
- * Write the incoming trace data to a file. The maximum file size is 1MB. After that
- * the trace data is saved into a new file.
- */
-static int
-fwtrace_write_to_file(uint8 *buf, uint16 buf_len, dhd_pub_t *dhdp)
-{
- fwtrace_info_t *fwtrace_info = dhdp->fwtrace_info;
- int ret_val = BCME_OK;
- int ret_val_1 = 0;
- mm_segment_t old_fs;
- loff_t pos = 0;
- struct kstat stat;
- int error;
-
- /* Change to KERNEL_DS address limit */
- old_fs = get_fs();
- set_fs(KERNEL_DS);
-
- if (buf == NULL) {
- ret_val = BCME_ERROR;
- goto done;
- }
-
- if (IS_ERR_OR_NULL(fwtrace_info->fw_trace_fp)) {
- ret_val = BCME_ERROR;
- goto done;
- }
-
- //
- // Get the file size
- // if the size + buf_len > TRACE_FILE_SIZE, then write to a different file.
- //
- error = dhd_vfs_stat(fwtrace_info->trace_file, &stat);
- if (error) {
- DHD_ERROR(("vfs_stat has failed with error code = %d\n", error));
- goto done;
- }
-
- if ((int) stat.size + buf_len > TRACE_FILE_SIZE) {
- fwtrace_close_file(dhdp);
- (fwtrace_info->part_index)++;
- fwtrace_open_file(TRUE, dhdp);
- }
-
- pos = fwtrace_info->fw_trace_fp->f_pos;
- /* Write buf to file */
- ret_val_1 = dhd_vfs_write(fwtrace_info->fw_trace_fp,
- (char *) buf, (uint32) buf_len, &pos);
- if (ret_val_1 < 0) {
- DHD_ERROR(("write file error, err = %d\n", ret_val_1));
- ret_val = BCME_ERROR;
- goto done;
- }
- fwtrace_info->fw_trace_fp->f_pos = pos;
-
- /* Sync file from filesystem to physical media */
- ret_val_1 = dhd_vfs_fsync(fwtrace_info->fw_trace_fp, 0);
- if (ret_val_1 < 0) {
- DHD_ERROR(("sync file error, error = %d\n", ret_val_1));
- ret_val = BCME_ERROR;
- goto done;
- }
-
-done:
- /* restore previous address limit */
- set_fs(old_fs);
- return (ret_val);
-}
-
-/*
- * Start the trace, gets called from the ioctl handler.
- */
-int
-fw_trace_start(dhd_pub_t *dhdp, uint32 fw_trace_enabled)
-{
- int ret_val = BCME_OK;
-
- (dhdp->fwtrace_info->file_index)++;
- dhdp->fwtrace_info->part_index = 1;
-
- dhdp->fwtrace_info->trace_buf_index = 0;
-
- mutex_lock(&dhdp->fwtrace_info->fwtrace_lock);
- ret_val = fwtrace_open_file(fw_trace_enabled, dhdp);
- if (ret_val == BCME_OK) {
- dhdp->fwtrace_info->fwtrace_enable = fw_trace_enabled;
- }
- mutex_unlock(&dhdp->fwtrace_info->fwtrace_lock);
-
- return (ret_val);
-}
-
-/*
- * Stop the trace collection and close the file descriptor.
- */
-int
-fw_trace_stop(dhd_pub_t *dhdp)
-{
- int ret_val = BCME_OK;
-
- /* Check to see if there is any trace data */
- process_fw_trace_data(dhdp);
-
- mutex_lock(&dhdp->fwtrace_info->fwtrace_lock); /* acquire lock */
- /* flush the trace buffer */
- ret_val = fwtrace_close_file(dhdp);
-
- /* free the trace buffer */
- fwtrace_free_trace_buf(dhdp);
- mutex_unlock(&dhdp->fwtrace_info->fwtrace_lock); /* release the lock */
-
- return (ret_val);
-}
-
-/*
- * The trace file format is: fw_trace_w_part_x_y_z
- * where w is the file index, x is the part index,
- * y is in seconds and z is in milliseconds
- *
- * fw_trace_1_part_1_1539298163209110
- * fw_trace_1_part_2_1539298194739003 etc.
- *
- */
-static int
-fwtrace_open_file(uint32 fw_trace_enabled, dhd_pub_t *dhdp)
-{
- fwtrace_info_t *fwtrace_info = dhdp->fwtrace_info;
- int ret_val = BCME_OK;
- uint32 file_mode;
- char ts_str[DEBUG_DUMP_TIME_BUF_LEN];
-
- if (fw_trace_enabled) {
- if (!(IS_ERR_OR_NULL(fwtrace_info->fw_trace_fp))) {
- (void) dhd_filp_close(fwtrace_info->fw_trace_fp, 0);
- }
-
- DHD_INFO((" *** Creating the trace file \n"));
-
- file_mode = O_CREAT | O_WRONLY | O_SYNC;
- clear_debug_dump_time(ts_str);
- get_debug_dump_time(ts_str);
-
- snprintf(fwtrace_info->trace_file,
- sizeof(fwtrace_info->trace_file),
- "%sfw_trace_%d_part_%d_%x_%s",
- DHD_COMMON_DUMP_PATH, fwtrace_info->file_index,
- fwtrace_info->part_index,
- dhd_bus_get_bp_base(dhdp),
- ts_str);
-
- fwtrace_info->fw_trace_fp =
- dhd_filp_open(fwtrace_info->trace_file, file_mode, 0664);
-
- if (IS_ERR(fwtrace_info->fw_trace_fp) || (fwtrace_info->fw_trace_fp == NULL)) {
- DHD_ERROR(("Unable to create the fw trace file file: %s\n",
- fwtrace_info->trace_file));
- ret_val = BCME_ERROR;
- goto done;
- }
- }
-
-done:
- return (ret_val);
-}
-
-static int
-fwtrace_close_file(dhd_pub_t *dhdp)
-{
- int ret_val = BCME_OK;
-
- if (!(IS_ERR_OR_NULL(dhdp->fwtrace_info->fw_trace_fp))) {
- (void) dhd_filp_close(dhdp->fwtrace_info->fw_trace_fp, 0);
- }
-
- dhdp->fwtrace_info->fw_trace_fp = NULL;
-
- return (ret_val);
-}
-
-#define FWTRACE_HADDR_PARAMS_SIZE 256u
-#define FW_TRACE_FLUSH 0x8u /* bit 3 */
-
-static int send_fw_trace_val(dhd_pub_t *dhdp, int val);
-
-/*
- * Initialize FWTRACE.
- * Allocate trace buffer and open trace file.
- */
-int
-fwtrace_init(dhd_pub_t *dhdp)
-{
- int ret_val = BCME_OK;
- fwtrace_hostaddr_info_t host_buf_info;
-
- if (dhdp->fwtrace_info->fwtrace_buf.va != NULL) {
- /* Already initialized */
- goto done;
- }
-
- ret_val = fwtrace_get_haddr(dhdp, &host_buf_info);
-
- if (ret_val != BCME_OK) {
- goto done;
- }
-
- DHD_INFO(("dhd_get_trace_haddr: addr = %llx, len = %u\n",
- host_buf_info.haddr.u64, host_buf_info.num_bufs));
-
- /* Initialize and setup the file */
- ret_val = fw_trace_start(dhdp, TRUE);
-
-done:
- return ret_val;
-}
-
-/*
- * Process the fwtrace set command to enable/disable firmware tracing.
- * Always, enable preceeds with disable.
- */
-int
-handle_set_fwtrace(dhd_pub_t *dhdp, uint32 val)
-{
- int ret, ret_val = BCME_OK;
-
- /* On set, consider only lower two bytes for now */
- dhdp->fwtrace_info->fwtrace_enable = (val & 0xFFFF);
-
- if (val & FW_TRACE_FLUSH) { /* only flush the trace buffer */
- if ((ret_val = send_fw_trace_val(dhdp, val)) != BCME_OK) {
- goto done;
- }
- } else if (val == 0) { /* disable the tracing */
- /* Disable the trace in the firmware */
- if ((ret_val = send_fw_trace_val(dhdp, val)) != BCME_OK) {
- goto done;
- }
-
- /* cleanup in the driver */
- fw_trace_stop(dhdp);
- } else { /* enable the tracing */
- fwtrace_hostaddr_info_t haddr_info;
-
- ret_val = fwtrace_init(dhdp);
- if (ret_val != BCME_OK) {
- goto done;
- }
-
- if ((ret_val = fwtrace_get_haddr(dhdp, &haddr_info)) != BCME_OK) {
- DHD_ERROR(("%s: set dhd_iovar has failed for "
- "fw_trace_haddr, "
- "ret=%d\n", __FUNCTION__, ret_val));
- goto done;
- }
-
- ret = dhd_iovar(dhdp, 0, "dngl:fwtrace_haddr",
- (char *) &haddr_info, sizeof(haddr_info),
- NULL, 0, TRUE);
- if (ret < 0) {
- DHD_ERROR(("%s: set dhd_iovar has failed for "
- "fwtrace_haddr, "
- "ret=%d\n", __FUNCTION__, ret));
- ret_val = BCME_NOMEM;
- goto done;
- }
-
- /* Finaly, enable the trace in the firmware */
- if ((ret_val = send_fw_trace_val(dhdp, val)) != BCME_OK) {
- goto done;
- }
- }
-done:
- return (ret_val);
-}
-
-/*
- * Send dngl:fwtrace IOVAR to the firmware.
- */
-
-static int
-send_fw_trace_val(dhd_pub_t *dhdp, int val)
-{
- int ret_val = BCME_OK;
-
- if ((ret_val = dhd_iovar(dhdp, 0, "dngl:fwtrace", (char *)&val, sizeof(val),
- NULL, 0, TRUE)) < 0) {
- DHD_ERROR(("%s: set dhd_iovar has failed fwtrace, "
- "ret=%d\n", __FUNCTION__, ret_val));
- }
-
- return (ret_val);
-}
-
-/*
- * Returns the virual address for the firmware trace buffer.
- * DHD monitors this buffer for an update from the firmware.
- */
-static fwtrace_buf_t *
-fwtrace_get_trace_data_ptr(dhd_pub_t *dhdp)
-{
- return ((fwtrace_buf_t *) dhdp->fwtrace_info->fwtrace_buf.va);
-}
-
-int
-fwtrace_get_haddr(dhd_pub_t *dhdp, fwtrace_hostaddr_info_t *haddr_info)
-{
- int ret_val = BCME_NOMEM;
- int num_host_buffers = FWTRACE_NUM_HOST_BUFFERS;
-
- if (haddr_info == NULL) {
- ret_val = BCME_BADARG;
- goto done;
- }
-
- if (dhdp->fwtrace_info->fwtrace_buf.va != NULL) {
- /* Use the existing buffer and send to the firmware */
- haddr_info->haddr.u64 = HTOL64(*(uint64 *)
- &dhdp->fwtrace_info->fwtrace_buf.pa);
- haddr_info->num_bufs = dhdp->fwtrace_info->trace_buf_count;
- haddr_info->buf_len = sizeof(fwtrace_buf_t);
- ret_val = BCME_OK;
- goto done;
- }
-
- do {
- /* Initialize firmware trace buffer */
- if (dhd_dma_buf_alloc(dhdp, &dhdp->fwtrace_info->fwtrace_buf,
- sizeof(fwtrace_buf_t) * num_host_buffers) == BCME_OK) {
- dhdp->fwtrace_info->trace_buf_count = num_host_buffers;
- ret_val = BCME_OK;
- break;
- }
-
- DHD_ERROR(("%s: Allocing %d buffers of size %lu bytes failed\n",
- __FUNCTION__, num_host_buffers,
- sizeof(fwtrace_buf_t) * num_host_buffers));
-
- /* Retry with smaller numbers */
- num_host_buffers >>= 1;
- } while (num_host_buffers > 0);
-
- haddr_info->haddr.u64 = HTOL64(*(uint64 *)&dhdp->fwtrace_info->fwtrace_buf.pa);
- haddr_info->num_bufs = num_host_buffers;
- haddr_info->buf_len = sizeof(fwtrace_buf_t);
-
- DHD_INFO(("Firmware trace buffer, host address = %llx, count = %u \n",
- haddr_info->haddr.u64,
- haddr_info->num_bufs));
-done:
- return (ret_val);
-}
-
-/*
- * Frees the host buffer.
- */
-static void
-fwtrace_free_trace_buf(dhd_pub_t *dhdp)
-{
- dhd_dma_buf_free(dhdp, &dhdp->fwtrace_info->fwtrace_buf);
- return;
-}
-
-#endif /* DHD_FWTRACE */
-
-#endif /* BCMINTERNAL */
+++ /dev/null
-/*
- * Data structures required for the firmware tracing support on Linux.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- *
- * $Id$
- */
-
-#ifndef _DHD_FWTRACE_H
-#define _DHD_FWTRACE_H
-
-#ifdef BCMINTERNAL
-#ifdef DHD_FWTRACE /* firmware tracing */
-
-#include <dngl_stats.h>
-#include <dhd.h>
-#include <dhd_proto.h>
-#include <dhd_dbg.h>
-#include <dhd_debug.h>
-#include <dhd_fwtrace.h>
-
-#include <linux/mutex.h>
-#include <bcm_fwtrace.h>
-
-#define TRACE_FILE_NAME_LEN 128u /* bytes */
-#define TRACE_FILE_SIZE (1024u * 1024u) /* Trace file size is 1 MB */
-
-/* Prototypes */
-void dhd_event_logtrace_enqueue_fwtrace(dhd_pub_t *dhdp);
-int dhd_fwtrace_attach(dhd_pub_t *dhdinfo);
-int dhd_fwtrace_detach(dhd_pub_t *dhdinfo);
-
-void process_fw_trace_data(dhd_pub_t *dhdp);
-uint32 dhd_bus_get_bp_base(dhd_pub_t *dhdp);
-int fwtrace_init(dhd_pub_t *dhdp);
-int fw_trace_start(dhd_pub_t *dhdp, uint32 fw_trace_enabled);
-int fw_trace_stop(dhd_pub_t *dhdp);
-int handle_set_fwtrace(dhd_pub_t *dhdp, uint32 val);
-uint16 get_fw_trace_overflow_counter(dhd_pub_t *dhdp);
-int fwtrace_get_haddr(dhd_pub_t *dhdp, fwtrace_hostaddr_info_t *haddr_info);
-
-#endif /* DHD_FWTRACE */
-
-#endif /* BCMINTERNAL */
-
-#endif /* _DHD_FWTRACE_H */
#include <osl.h>
#include <dhd_linux.h>
#include <linux/gpio.h>
+#ifdef BCMDHD_DTS
+#include <linux/of_gpio.h>
+#endif
+#ifdef BCMDHD_PLATDEV
+#include <linux/platform_device.h>
+#endif
#if defined(BUS_POWER_RESTORE) && defined(BCMSDIO)
#include <linux/mmc/core.h>
#ifdef BCMDHD_DTS
/* This is sample code in dts file.
-bcmdhd {
+bcmdhd_wlan {
compatible = "android,bcmdhd_wlan";
gpio_wl_reg_on = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
gpio_wl_host_wake = <&gpio GPIOZ_15 GPIO_ACTIVE_HIGH>;
}
#ifdef CUSTOMER_HW_AMLOGIC
#ifdef BCMSDIO
-// extern_wifi_set_enable(0);
-// mdelay(200);
extern_wifi_set_enable(1);
- mdelay(200);
+// mdelay(200);
// sdio_reinit();
#endif
#ifdef BCMDBUS
- if (dhd_pwr_ctrl) {
- set_usb_wifi_power(0);
- mdelay(200);
- set_usb_wifi_power(1);
- mdelay(200);
- }
+ if (dhd_pwr_ctrl) {
+ set_usb_wifi_power(1);
+ }
#endif
#ifdef BCMPCIE
// extern_wifi_set_enable(0);
#ifdef CUSTOMER_HW_AMLOGIC
#ifdef BCMSDIO
extern_wifi_set_enable(0);
- mdelay(200);
#endif
#ifdef BCMDBUS
- if (dhd_pwr_ctrl) {
- set_usb_wifi_power(0);
- mdelay(200);
- }
+ if (dhd_pwr_ctrl) {
+ set_usb_wifi_power(0);
+ }
#endif
#ifdef BCMPCIE
// extern_wifi_set_enable(0);
-// mdelay(200);
#endif
#endif
}
struct device_node *root_node = NULL;
#endif
int err = 0;
- int gpio_wl_reg_on;
+ int gpio_wl_reg_on = -1;
#ifdef CUSTOMER_OOB
- int gpio_wl_host_wake;
+ int gpio_wl_host_wake = -1;
int host_oob_irq = -1;
uint host_oob_irq_flags = 0;
#endif
* WL_REG_ON and WL_HOST_WAKE.
*/
#ifdef BCMDHD_DTS
+#ifdef BCMDHD_PLATDEV
+ if (adapter->pdev) {
+ root_node = adapter->pdev->dev.of_node;
+ strcpy(wlan_node, root_node->name);
+ } else {
+ printf("%s: adapter->pdev is NULL\n", __FUNCTION__);
+ return -1;
+ }
+#else
strcpy(wlan_node, DHD_DT_COMPAT_ENTRY);
- printf("======== Get GPIO from DTS(%s) ========\n", wlan_node);
root_node = of_find_compatible_node(NULL, NULL, wlan_node);
+#endif
+ printf("======== Get GPIO from DTS(%s) ========\n", wlan_node);
if (root_node) {
gpio_wl_reg_on = of_get_named_gpio(root_node, GPIO_WL_REG_ON_PROPNAME, 0);
#ifdef CUSTOMER_OOB
dhd_pub_t *dhd = &dhdinfo->pub;
struct dhd_conf *conf = dhd->conf;
int suspend_mode = conf->suspend_mode;
+#if defined(BCMDBUS) && defined(WL_EXT_WOWL)
+ int wowl_dngldown = 0;
+#endif
BCM_REFERENCE(dhdinfo);
BCM_REFERENCE(suspend);
+#if defined(BCMDBUS) && defined(WL_EXT_WOWL)
+ wowl_dngldown = dhd_conf_wowl_dngldown(dhd);
+#endif
+
switch (action) {
case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
dhd_suspend_resume_helper(dhdinfo, suspend, 0);
#ifdef BCMDBUS
} else {
- printf("%s: skip resume since bus suspeneded\n", __FUNCTION__);
+#if defined(BCMDBUS) && defined(WL_EXT_WOWL)
+ if (wowl_dngldown) {
+ printf("%s: reset power\n", __FUNCTION__);
+ dhd_wifi_platform_set_power(dhd, FALSE);
+ dhd_wifi_platform_set_power(dhd, TRUE);
+ } else
+#endif
+ {
+ printf("%s: skip resume since bus suspeneded\n", __FUNCTION__);
+ }
}
#endif
}
return;
}
+#ifdef DHD_NOTIFY_MAC_CHANGED
+ rtnl_lock();
+#endif /* DHD_NOTIFY_MAC_CHANGED */
dhd_net_if_lock_local(dhd);
DHD_OS_WAKE_LOCK(&dhd->pub);
ifp->set_macaddress = FALSE;
-#ifdef DHD_NOTIFY_MAC_CHANGED
- rtnl_lock();
-#endif /* DHD_NOTIFY_MAC_CHANGED */
-
if (_dhd_set_mac_address(dhd, ifp->idx, ifp->mac_addr, TRUE) == 0)
DHD_INFO(("%s: MACID is overwritten\n", __FUNCTION__));
else
DHD_ERROR(("%s: _dhd_set_mac_address() failed\n", __FUNCTION__));
-#ifdef DHD_NOTIFY_MAC_CHANGED
- rtnl_unlock();
-#endif /* DHD_NOTIFY_MAC_CHANGED */
-
done:
DHD_OS_WAKE_UNLOCK(&dhd->pub);
dhd_net_if_unlock_local(dhd);
+#ifdef DHD_NOTIFY_MAC_CHANGED
+ rtnl_unlock();
+#endif /* DHD_NOTIFY_MAC_CHANGED */
}
static void
#endif
/* Make sure there's enough room for any header */
#if !defined(BCM_ROUTER_DHD)
- if (skb_headroom(skb) < dhd->pub.hdrlen + htsfdlystat_sz) {
- struct sk_buff *skb2;
-
- DHD_INFO(("%s: insufficient headroom\n",
- dhd_ifname(&dhd->pub, ifidx)));
- dhd->pub.tx_realloc++;
-
+ if (skb_cow(skb, (dhd->pub.hdrlen + htsfdlystat_sz))) {
+ DHD_ERROR(("%s: skb_cow failed\n",
+ dhd_ifname(&dhd->pub, ifidx)));
bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, __FUNCTION__, __LINE__);
- skb2 = skb_realloc_headroom(skb, dhd->pub.hdrlen + htsfdlystat_sz);
-
- dev_kfree_skb(skb);
- if ((skb = skb2) == NULL) {
- DHD_ERROR(("%s: skb_realloc_headroom failed\n",
- dhd_ifname(&dhd->pub, ifidx)));
- ret = -ENOMEM;
- goto done;
- }
- bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, __FUNCTION__, __LINE__);
+ dev_kfree_skb_any(skb);
+ ret = -ENOMEM;
+ goto done;
}
#endif /* !BCM_ROUTER_DHD */
}
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
-#ifdef CONFIG_HAS_WAKELOCK
-#define dhd_wake_lock_unlock_destroy(wlock) \
-{ \
- if (dhd_wake_lock_active(wlock)) { \
- dhd_wake_unlock(wlock); \
- } \
- dhd_wake_lock_destroy(wlock); \
-}
-#endif /* CONFIG_HAS_WAKELOCK */
-
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) && defined(DHD_TCP_LIMIT_OUTPUT)
#define DHD_TCP_LIMIT_OUTPUT_BYTES (4 * 1024 * 1024)
#ifndef TCP_DEFAULT_LIMIT_OUTPUT
#if defined(WL_STATIC_IF) && defined(WL_CFG80211)
/* If static if is operational, don't reset the chip */
- if (wl_cfg80211_static_if_active(cfg)) {
+ if ((!dhd->pub.hang_was_sent) && wl_cfg80211_static_if_active(cfg)) {
WL_MSG(net->name, "static if operational. skip chip reset.\n");
skip_reset = true;
wl_cfg80211_sta_ifdown(net);
}
#endif /* WL_STATIC_IF && WL_CFG80211 */
#ifdef DHD_NOTIFY_MAC_CHANGED
- if (dhd->pub.skip_dhd_stop) {
+ if (!dhd->pub.hang_was_sent && dhd->pub.skip_dhd_stop) {
WL_MSG(net->name, "skip chip reset.\n");
skip_reset = true;
#if defined(WL_CFG80211)
#endif /* DHDTCPACK_SUPPRESS && BCMPCIE */
if (need_rtnl_lock)
unregister_netdev(ifp->net);
- else
+ else {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) && defined(WL_CFG80211)
+ cfg80211_unregister_netdevice(ifp->net);
+#else
unregister_netdevice(ifp->net);
+#endif
+ }
#if defined(WLDWDS) && defined(WL_EXT_IAPSTA)
if (ifp->dwds) {
wl_ext_iapsta_dettach_dwds_netdev(ifp->net, ifidx, ifp->bssidx);
dhd->wakelock_counter = 0;
/* wakelocks prevent a system from going into a low power state */
#ifdef CONFIG_HAS_WAKELOCK
- // terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
- dhd_wake_lock_init(&dhd->wl_wifi, WAKE_LOCK_SUSPEND, "wlan_wake");
- dhd_wake_lock_init(&dhd->wl_wdwake, WAKE_LOCK_SUSPEND, "wlan_wd_wake");
+ dhd_wake_lock_init(dhd->wl_wdwake, dhd_bus_to_dev(bus), "wlan_wd_wake");
#endif /* CONFIG_HAS_WAKELOCK */
#if defined(OEM_ANDROID)
dhd_os_start_logging(&dhd->pub, BT_LOG_RING_NAME, 3, 0, 0, 0);
#endif /* !OEM_ANDROID && BTLOG */
#ifdef DBG_PKT_MON
- dhd->pub.dbg->pkt_mon_lock = osl_mutex_lock_init(dhd->pub.osh);
- if (!dhd->pub.dbg->pkt_mon_lock) {
- DHD_ERROR(("%s: pkt_mon_lock init failed !\n", __FUNCTION__));
- goto fail;
- }
+ dhd->pub.dbg->pkt_mon_lock = osl_spin_lock_init(dhd->pub.osh);
#ifdef DBG_PKT_MON_INIT_DEFAULT
dhd_os_dbg_attach_pkt_monitor(&dhd->pub);
#endif /* DBG_PKT_MON_INIT_DEFAULT */
if (dhdp->dbg) {
#ifdef DBG_PKT_MON
dhd_os_dbg_detach_pkt_monitor(dhdp);
- osl_mutex_lock_deinit(dhd->pub.osh, dhd->pub.dbg->pkt_mon_lock);
+ osl_spin_lock_deinit(dhd->pub.osh, dhd->pub.dbg->pkt_mon_lock);
#endif /* DBG_PKT_MON */
}
#endif /* DEBUGABILITY */
DHD_TRACE(("wd wakelock count:%d\n", dhd->wakelock_wd_counter));
#ifdef CONFIG_HAS_WAKELOCK
dhd->wakelock_wd_counter = 0;
- dhd_wake_lock_unlock_destroy(&dhd->wl_wdwake);
- // terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
- dhd_wake_lock_unlock_destroy(&dhd->wl_wifi);
+ dhd_wake_lock_destroy(dhd->wl_wdwake);
#endif /* CONFIG_HAS_WAKELOCK */
if (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT) {
DHD_OS_WAKE_LOCK_DESTROY(dhd);
/* convert to BCME_NOTFOUND error for error handling */
ret = BCME_NOTFOUND;
} else
- DHD_ERROR(("%s: %s (%zu bytes) open success\n", __FUNCTION__, file_path, (*fw)->size));
+ DHD_ERROR(("%s: %s (%zu bytes) open success\n", __FUNCTION__, file_path, (*fw)->size));
return ret;
}
ret = dhd->wakelock_rx_timeout_enable > dhd->wakelock_ctrl_timeout_enable ?
dhd->wakelock_rx_timeout_enable : dhd->wakelock_ctrl_timeout_enable;
#ifdef CONFIG_HAS_WAKELOCK
+#ifdef DHD_DEBUG_WAKE_LOCK
+ printf("%s: rx_timeout=%dms, ctrl_timeout=%dms\n", __FUNCTION__,
+ dhd->wakelock_rx_timeout_enable, dhd->wakelock_ctrl_timeout_enable);
+#endif
if (dhd->wakelock_rx_timeout_enable)
- dhd_wake_lock_timeout(&dhd->wl_rxwake,
+ dhd_wake_lock_timeout(dhd->wl_rxwake,
msecs_to_jiffies(dhd->wakelock_rx_timeout_enable));
if (dhd->wakelock_ctrl_timeout_enable)
- dhd_wake_lock_timeout(&dhd->wl_ctrlwake,
+ dhd_wake_lock_timeout(dhd->wl_ctrlwake,
msecs_to_jiffies(dhd->wakelock_ctrl_timeout_enable));
#endif
dhd->wakelock_rx_timeout_enable = 0;
DHD_WAKE_SPIN_LOCK(&dhd->wakelock_spinlock, flags);
dhd->wakelock_ctrl_timeout_enable = 0;
#ifdef CONFIG_HAS_WAKELOCK
- if (dhd_wake_lock_active(&dhd->wl_ctrlwake))
- dhd_wake_unlock(&dhd->wl_ctrlwake);
+ if (dhd_wake_lock_active(dhd->wl_ctrlwake))
+ dhd_wake_unlock(dhd->wl_ctrlwake);
#endif
DHD_WAKE_SPIN_UNLOCK(&dhd->wakelock_spinlock, flags);
}
DHD_WAKE_SPIN_LOCK(&dhd->wakelock_spinlock, flags);
if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_lock(&dhd->wl_wifi);
+ dhd_wake_lock(dhd->wl_wifi);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_stay_awake(pub);
#endif
if (dhd) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_lock(&dhd->wl_evtwake);
+ dhd_wake_lock(dhd->wl_evtwake);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_stay_awake(pub);
#endif
dhd_info_t *dhd = (dhd_info_t *)(pub->info);
if (dhd) {
- dhd_wake_lock_timeout(&dhd->wl_pmwake, msecs_to_jiffies(val));
+ dhd_wake_lock_timeout(dhd->wl_pmwake, msecs_to_jiffies(val));
}
#endif /* CONFIG_HAS_WAKE_LOCK */
}
dhd_info_t *dhd = (dhd_info_t *)(pub->info);
if (dhd) {
- dhd_wake_lock_timeout(&dhd->wl_txflwake, msecs_to_jiffies(val));
+ dhd_wake_lock_timeout(dhd->wl_txflwake, msecs_to_jiffies(val));
}
#endif /* CONFIG_HAS_WAKE_LOCK */
}
dhd_info_t *dhd = (dhd_info_t *)(pub->info);
if (dhd) {
- dhd_wake_lock_timeout(&dhd->wl_nanwake, msecs_to_jiffies(val));
+ dhd_wake_lock_timeout(dhd->wl_nanwake, msecs_to_jiffies(val));
}
#endif /* CONFIG_HAS_WAKE_LOCK */
}
#endif /* DHD_TRACE_WAKE_LOCK */
if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_unlock(&dhd->wl_wifi);
+ dhd_wake_unlock(dhd->wl_wifi);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_relax(pub);
#endif
if (dhd) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_unlock(&dhd->wl_evtwake);
+ dhd_wake_unlock(dhd->wl_evtwake);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_relax(pub);
#endif
if (dhd) {
/* if wl_pmwake is active, unlock it */
- if (dhd_wake_lock_active(&dhd->wl_pmwake)) {
- dhd_wake_unlock(&dhd->wl_pmwake);
+ if (dhd_wake_lock_active(dhd->wl_pmwake)) {
+ dhd_wake_unlock(dhd->wl_pmwake);
}
}
#endif /* CONFIG_HAS_WAKELOCK */
if (dhd) {
/* if wl_txflwake is active, unlock it */
- if (dhd_wake_lock_active(&dhd->wl_txflwake)) {
- dhd_wake_unlock(&dhd->wl_txflwake);
+ if (dhd_wake_lock_active(dhd->wl_txflwake)) {
+ dhd_wake_unlock(dhd->wl_txflwake);
}
}
#endif /* CONFIG_HAS_WAKELOCK */
if (dhd) {
/* if wl_nanwake is active, unlock it */
- if (dhd_wake_lock_active(&dhd->wl_nanwake)) {
- dhd_wake_unlock(&dhd->wl_nanwake);
+ if (dhd_wake_lock_active(dhd->wl_nanwake)) {
+ dhd_wake_unlock(dhd->wl_nanwake);
}
}
#endif /* CONFIG_HAS_WAKELOCK */
#ifdef CONFIG_HAS_WAKELOCK
c = dhd->wakelock_counter;
- l1 = dhd_wake_lock_active(&dhd->wl_wifi);
- l2 = dhd_wake_lock_active(&dhd->wl_wdwake);
+ l1 = dhd_wake_lock_active(dhd->wl_wifi);
+ l2 = dhd_wake_lock_active(dhd->wl_wdwake);
lock_active = (l1 || l2);
/* Indicate to the SD Host to avoid going to suspend if internal locks are up */
if (lock_active) {
#ifdef CONFIG_HAS_WAKELOCK
c = dhd->wakelock_counter;
- l1 = dhd_wake_lock_active(&dhd->wl_wifi);
- l2 = dhd_wake_lock_active(&dhd->wl_wdwake);
- l3 = dhd_wake_lock_active(&dhd->wl_rxwake);
- l4 = dhd_wake_lock_active(&dhd->wl_ctrlwake);
- l7 = dhd_wake_lock_active(&dhd->wl_evtwake);
+ l1 = dhd_wake_lock_active(dhd->wl_wifi);
+ l2 = dhd_wake_lock_active(dhd->wl_wdwake);
+ l3 = dhd_wake_lock_active(dhd->wl_rxwake);
+ l4 = dhd_wake_lock_active(dhd->wl_ctrlwake);
+ l7 = dhd_wake_lock_active(dhd->wl_evtwake);
#ifdef BCMPCIE_OOB_HOST_WAKE
- l5 = dhd_wake_lock_active(&dhd->wl_intrwake);
+ l5 = dhd_wake_lock_active(dhd->wl_intrwake);
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef DHD_USE_SCAN_WAKELOCK
- l6 = dhd_wake_lock_active(&dhd->wl_scanwake);
+ l6 = dhd_wake_lock_active(dhd->wl_scanwake);
#endif /* DHD_USE_SCAN_WAKELOCK */
- l8 = dhd_wake_lock_active(&dhd->wl_pmwake);
- l9 = dhd_wake_lock_active(&dhd->wl_txflwake);
- l10 = dhd_wake_lock_active(&dhd->wl_nanwake);
+ l8 = dhd_wake_lock_active(dhd->wl_pmwake);
+ l9 = dhd_wake_lock_active(dhd->wl_txflwake);
+ l10 = dhd_wake_lock_active(dhd->wl_nanwake);
lock_active = (l1 || l2 || l3 || l4 || l5 || l6 || l7 || l8 || l9 || l10);
/* Indicate to the Host to avoid going to suspend if internal locks are up */
if (dhd->wakelock_wd_counter == 0 && !dhd->waive_wakelock) {
#ifdef CONFIG_HAS_WAKELOCK
/* if wakelock_wd_counter was never used : lock it at once */
- dhd_wake_lock(&dhd->wl_wdwake);
+ dhd_wake_lock(dhd->wl_wdwake);
#endif
}
dhd->wakelock_wd_counter++;
dhd->wakelock_wd_counter = 0;
if (!dhd->waive_wakelock) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_unlock(&dhd->wl_wdwake);
+ dhd_wake_unlock(dhd->wl_wdwake);
#endif
}
}
dhd_info_t *dhd = (dhd_info_t *)(pub->info);
if (dhd) {
- dhd_wake_lock_timeout(&dhd->wl_intrwake, msecs_to_jiffies(val));
+ dhd_wake_lock_timeout(dhd->wl_intrwake, msecs_to_jiffies(val));
}
#endif /* CONFIG_HAS_WAKELOCK */
}
if (dhd) {
/* if wl_intrwake is active, unlock it */
- if (dhd_wake_lock_active(&dhd->wl_intrwake)) {
- dhd_wake_unlock(&dhd->wl_intrwake);
+ if (dhd_wake_lock_active(dhd->wl_intrwake)) {
+ dhd_wake_unlock(dhd->wl_intrwake);
}
}
#endif /* CONFIG_HAS_WAKELOCK */
dhd_info_t *dhd = (dhd_info_t *)(pub->info);
if (dhd) {
- dhd_wake_lock_timeout(&dhd->wl_scanwake, msecs_to_jiffies(val));
+ dhd_wake_lock_timeout(dhd->wl_scanwake, msecs_to_jiffies(val));
}
#endif /* CONFIG_HAS_WAKELOCK */
}
if (dhd) {
/* if wl_scanwake is active, unlock it */
- if (dhd_wake_lock_active(&dhd->wl_scanwake)) {
- dhd_wake_unlock(&dhd->wl_scanwake);
+ if (dhd_wake_lock_active(dhd->wl_scanwake)) {
+ dhd_wake_unlock(dhd->wl_scanwake);
}
}
#endif /* CONFIG_HAS_WAKELOCK */
if (dhd->wakelock_before_waive == 0 && dhd->wakelock_counter > 0) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_lock(&dhd->wl_wifi);
+ dhd_wake_lock(dhd->wl_wifi);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_stay_awake(&dhd->pub);
#endif
} else if (dhd->wakelock_before_waive > 0 && dhd->wakelock_counter == 0) {
#ifdef CONFIG_HAS_WAKELOCK
- dhd_wake_unlock(&dhd->wl_wifi);
+ dhd_wake_unlock(dhd->wl_wifi);
#elif defined(BCMSDIO)
dhd_bus_dev_pm_relax(&dhd->pub);
#endif
dhd->wakelock_ctrl_timeout_enable = 0;
/* wakelocks prevent a system from going into a low power state */
#ifdef CONFIG_HAS_WAKELOCK
- // terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
- dhd_wake_lock_init(&dhd->wl_rxwake, WAKE_LOCK_SUSPEND, "wlan_rx_wake");
- dhd_wake_lock_init(&dhd->wl_ctrlwake, WAKE_LOCK_SUSPEND, "wlan_ctrl_wake");
- dhd_wake_lock_init(&dhd->wl_evtwake, WAKE_LOCK_SUSPEND, "wlan_evt_wake");
- dhd_wake_lock_init(&dhd->wl_pmwake, WAKE_LOCK_SUSPEND, "wlan_pm_wake");
- dhd_wake_lock_init(&dhd->wl_txflwake, WAKE_LOCK_SUSPEND, "wlan_txfl_wake");
+ dhd_wake_lock_init(dhd->wl_wifi, dhd_bus_to_dev(dhd->pub.bus), "wlan_wake");
+ dhd_wake_lock_init(dhd->wl_rxwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_rx_wake");
+ dhd_wake_lock_init(dhd->wl_ctrlwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_ctrl_wake");
+ dhd_wake_lock_init(dhd->wl_evtwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_evt_wake");
+ dhd_wake_lock_init(dhd->wl_pmwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_pm_wake");
+ dhd_wake_lock_init(dhd->wl_txflwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_txfl_wake");
#ifdef BCMPCIE_OOB_HOST_WAKE
- dhd_wake_lock_init(&dhd->wl_intrwake, WAKE_LOCK_SUSPEND, "wlan_oob_irq_wake");
+ dhd_wake_lock_init(dhd->wl_intrwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_oob_irq_wake");
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef DHD_USE_SCAN_WAKELOCK
- dhd_wake_lock_init(&dhd->wl_scanwake, WAKE_LOCK_SUSPEND, "wlan_scan_wake");
+ dhd_wake_lock_init(dhd->wl_scanwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_scan_wake");
#endif /* DHD_USE_SCAN_WAKELOCK */
- dhd_wake_lock_init(&dhd->wl_nanwake, WAKE_LOCK_SUSPEND, "wlan_nan_wake");
+ dhd_wake_lock_init(dhd->wl_nanwake, dhd_bus_to_dev(dhd->pub.bus), "wlan_nan_wake");
#endif /* CONFIG_HAS_WAKELOCK */
#ifdef DHD_TRACE_WAKE_LOCK
dhd_wk_lock_trace_init(dhd);
dhd->wakelock_counter = 0;
dhd->wakelock_rx_timeout_enable = 0;
dhd->wakelock_ctrl_timeout_enable = 0;
- // terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
- dhd_wake_lock_unlock_destroy(&dhd->wl_rxwake);
- dhd_wake_lock_unlock_destroy(&dhd->wl_ctrlwake);
- dhd_wake_lock_unlock_destroy(&dhd->wl_evtwake);
- dhd_wake_lock_unlock_destroy(&dhd->wl_pmwake);
- dhd_wake_lock_unlock_destroy(&dhd->wl_txflwake);
+ dhd_wake_lock_destroy(dhd->wl_wifi);
+ dhd_wake_lock_destroy(dhd->wl_rxwake);
+ dhd_wake_lock_destroy(dhd->wl_ctrlwake);
+ dhd_wake_lock_destroy(dhd->wl_evtwake);
+ dhd_wake_lock_destroy(dhd->wl_pmwake);
+ dhd_wake_lock_destroy(dhd->wl_txflwake);
#ifdef BCMPCIE_OOB_HOST_WAKE
- dhd_wake_lock_unlock_destroy(&dhd->wl_intrwake);
+ dhd_wake_lock_destroy(dhd->wl_intrwake);
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef DHD_USE_SCAN_WAKELOCK
- dhd_wake_lock_unlock_destroy(&dhd->wl_scanwake);
+ dhd_wake_lock_destroy(dhd->wl_scanwake);
#endif /* DHD_USE_SCAN_WAKELOCK */
- dhd_wake_lock_unlock_destroy(&dhd->wl_nanwake);
+ dhd_wake_lock_destroy(dhd->wl_nanwake);
#ifdef DHD_TRACE_WAKE_LOCK
dhd_wk_lock_trace_deinit(dhd);
#endif /* DHD_TRACE_WAKE_LOCK */
dhd_get_random_bytes(uint8 *buf, uint len)
{
#ifdef BCMPCIE
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0))
- int rndlen = get_random_bytes_arch(buf, len);
- if (rndlen != len) {
- bzero(buf, len);
- get_random_bytes(buf, len);
- }
-#else
- get_random_bytes_arch(buf, len);
-#endif
+ get_random_bytes(buf, len);
#endif /* BCMPCIE */
return BCME_OK;
}
enum wifi_adapter_status {
WIFI_STATUS_POWER_ON = 0,
WIFI_STATUS_FW_READY,
- WIFI_STATUS_NET_ATTACHED
+ WIFI_STATUS_NET_ATTACHED,
+ WIFI_STATUS_BUS_DISCONNECTED
};
#define wifi_chk_adapter_status(adapter, stat) (test_bit(stat, &(adapter)->status))
#define wifi_get_adapter_status(adapter, stat) (test_bit(stat, &(adapter)->status))
struct pci_dev *pci_dev;
struct pci_saved_state *pci_saved_state;
#endif /* BCMPCIE */
+#ifdef BCMDHD_PLATDEV
+ struct platform_device *pdev;
+#endif /* BCMDHD_PLATDEV */
} wifi_adapter_info_t;
#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CUSTOMER_HW4)
{
int ret = BCME_ERROR;
if (inode) {
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0))
+ ret = single_open(file, 0, pde_data(inode));
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
ret = single_open(file, 0, PDE_DATA(inode));
#else
/* This feature is not supported for lower kernel versions */
#include<linux/of_gpio.h>
#endif /* CONFIG_DTS */
-#if defined(CUSTOMER_HW)
+#if defined(CUSTOMER_HW) || defined(BCMDHD_PLATDEV)
extern int dhd_wlan_init_plat_data(wifi_adapter_info_t *adapter);
extern void dhd_wlan_deinit_plat_data(wifi_adapter_info_t *adapter);
#endif /* CUSTOMER_HW */
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
#endif
struct resource dhd_wlan_resources = {0};
-struct wifi_platform_data dhd_wlan_control = {0};
+extern struct wifi_platform_data dhd_wlan_control;
#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
adapter->wifi_plat_data = (void *)&dhd_wlan_control;
#endif
+#ifdef BCMDHD_PLATDEV
+ adapter->pdev = pdev;
+ wifi_plat_dev_probe_ret = dhd_wlan_init_plat_data(adapter);
+ if (!wifi_plat_dev_probe_ret)
+ wifi_plat_dev_probe_ret = dhd_wifi_platform_load();
+ return wifi_plat_dev_probe_ret;
+#endif
+
resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
if (resource == NULL)
resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcm4329_wlan_irq");
#ifdef CONFIG_DTS
regulator_put(wifi_regulator);
#endif /* CONFIG_DTS */
+#ifdef BCMDHD_PLATDEV
+ dhd_wlan_deinit_plat_data(adapter);
+#endif
return 0;
}
/* Wakelocks */
#if defined(CONFIG_HAS_WAKELOCK)
- struct wakeup_source wl_wifi; /* Wifi wakelock */
- struct wakeup_source wl_rxwake; /* Wifi rx wakelock */
- struct wakeup_source wl_ctrlwake; /* Wifi ctrl wakelock */
- struct wakeup_source wl_wdwake; /* Wifi wd wakelock */
- struct wakeup_source wl_evtwake; /* Wifi event wakelock */
- struct wakeup_source wl_pmwake; /* Wifi pm handler wakelock */
- struct wakeup_source wl_txflwake; /* Wifi tx flow wakelock */
+ struct wakeup_source *wl_wifi; /* Wifi wakelock */
+ struct wakeup_source *wl_rxwake; /* Wifi rx wakelock */
+ struct wakeup_source *wl_ctrlwake; /* Wifi ctrl wakelock */
+ struct wakeup_source *wl_wdwake; /* Wifi wd wakelock */
+ struct wakeup_source *wl_evtwake; /* Wifi event wakelock */
+ struct wakeup_source *wl_pmwake; /* Wifi pm handler wakelock */
+ struct wakeup_source *wl_txflwake; /* Wifi tx flow wakelock */
#ifdef BCMPCIE_OOB_HOST_WAKE
- struct wakeup_source wl_intrwake; /* Host wakeup wakelock */
+ struct wakeup_source *wl_intrwake; /* Host wakeup wakelock */
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef DHD_USE_SCAN_WAKELOCK
- struct wakeup_source wl_scanwake; /* Wifi scan wakelock */
+ struct wakeup_source *wl_scanwake; /* Wifi scan wakelock */
#endif /* DHD_USE_SCAN_WAKELOCK */
- struct wakeup_source wl_nanwake; /* NAN wakelock */
+ struct wakeup_source *wl_nanwake; /* NAN wakelock */
#endif /* CONFIG_HAS_WAKELOCK */
#if defined(OEM_ANDROID)
extern uint fis_enab;
#endif /* DHD_SSSR_DUMP */
+#if defined(ANDROID_VERSION) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0))
+#define WAKELOCK_BACKPORT
+#endif
+
#ifdef CONFIG_HAS_WAKELOCK
-enum {
- WAKE_LOCK_SUSPEND, /* Prevent suspend */
- WAKE_LOCK_TYPE_COUNT
-};
-#define dhd_wake_lock_init(wakeup_source, type, name) wakeup_source_add(wakeup_source)
-#define dhd_wake_lock_destroy(wakeup_source) wakeup_source_remove(wakeup_source)
+#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) || defined(WAKELOCK_BACKPORT))
+#define dhd_wake_lock_init(wakeup_source, dev, name) \
+do { \
+ wakeup_source = wakeup_source_register(dev, name); \
+} while (0);
+#else
+#define dhd_wake_lock_init(wakeup_source, dev, name) \
+do { \
+ wakeup_source = wakeup_source_register(name); \
+} while (0);
+#endif /* LINUX_VERSION >= 5.4.0 */
+#define dhd_wake_lock_destroy(wakeup_source) \
+do { \
+ wakeup_source_unregister(wakeup_source); \
+} while (0);
#define dhd_wake_lock(wakeup_source) __pm_stay_awake(wakeup_source)
#define dhd_wake_unlock(wakeup_source) __pm_relax(wakeup_source)
-#define dhd_wake_lock_active(wakeup_source) ((wakeup_source)->active)
+#define dhd_wake_lock_active(wakeup_source) ((wakeup_source)?((wakeup_source)->active):0)
#define dhd_wake_lock_timeout(wakeup_source, timeout) \
__pm_wakeup_event(wakeup_source, jiffies_to_msecs(timeout))
#endif /* CONFIG_HAS_WAKELOCK */
+++ /dev/null
-/* D11 macdbg functions for Broadcom 802.11abgn
- * Networking Adapter Device Drivers.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- *
- * $Id: dhd_macdbg.c 670412 2016-11-15 20:01:18Z shinuk $
- */
-
-#ifdef BCMDBG
-#include <typedefs.h>
-#include <osl.h>
-
-#include <bcmutils.h>
-#include <dhd_dbg.h>
-#include <dhd_macdbg.h>
-#include "d11reglist_proto.h"
-#include "dhdioctl.h"
-#include <sdiovar.h>
-
-#include <dhd_bus.h>
-#define BUS_IOVAR_OP dhd_bus_iovar_op
-
-typedef struct _macdbg_info_t {
- dhd_pub_t *dhdp;
- d11regs_list_t *pd11regs;
- uint16 d11regs_sz;
- d11regs_list_t *pd11regs_x;
- uint16 d11regsx_sz;
- svmp_list_t *psvmpmems;
- uint16 svmpmems_sz;
-} macdbg_info_t;
-
-#define SVMPLIST_HARDCODE
-
-int
-dhd_macdbg_attach(dhd_pub_t *dhdp)
-{
- macdbg_info_t *macdbg_info = MALLOCZ(dhdp->osh, sizeof(*macdbg_info));
-#ifdef SVMPLIST_HARDCODE
- svmp_list_t svmpmems[] = {
- {0x20000, 256},
- {0x21e10, 16},
- {0x20300, 16},
- {0x20700, 16},
- {0x20b00, 16},
- {0x20be0, 16},
- {0x20bff, 16},
- {0xc000, 32},
- {0xe000, 32},
- {0x10000, 0x8000},
- {0x18000, 0x8000}
- };
-#endif /* SVMPLIST_HARDCODE */
-
- if (macdbg_info == NULL) {
- return BCME_NOMEM;
- }
- dhdp->macdbg_info = macdbg_info;
- macdbg_info->dhdp = dhdp;
-
-#ifdef SVMPLIST_HARDCODE
- macdbg_info->psvmpmems = MALLOCZ(dhdp->osh, sizeof(svmpmems));
- if (macdbg_info->psvmpmems == NULL) {
- return BCME_NOMEM;
- }
-
- macdbg_info->svmpmems_sz = ARRAYSIZE(svmpmems);
- memcpy(macdbg_info->psvmpmems, svmpmems, sizeof(svmpmems));
-
- DHD_ERROR(("%s: psvmpmems %p svmpmems_sz %d\n",
- __FUNCTION__, macdbg_info->psvmpmems, macdbg_info->svmpmems_sz));
-#endif
- return BCME_OK;
-}
-
-void
-dhd_macdbg_detach(dhd_pub_t *dhdp)
-{
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- ASSERT(macdbg_info);
-
- if (macdbg_info->pd11regs) {
- ASSERT(macdbg_info->d11regs_sz > 0);
- MFREE(dhdp->osh, macdbg_info->pd11regs,
- (macdbg_info->d11regs_sz * sizeof(macdbg_info->pd11regs[0])));
- macdbg_info->d11regs_sz = 0;
- }
- if (macdbg_info->pd11regs_x) {
- ASSERT(macdbg_info->d11regsx_sz > 0);
- MFREE(dhdp->osh, macdbg_info->pd11regs_x,
- (macdbg_info->d11regsx_sz * sizeof(macdbg_info->pd11regs_x[0])));
- macdbg_info->d11regsx_sz = 0;
- }
- if (macdbg_info->psvmpmems) {
- ASSERT(macdbg_info->svmpmems_sz > 0);
- MFREE(dhdp->osh, macdbg_info->psvmpmems,
- (macdbg_info->svmpmems_sz * sizeof(macdbg_info->psvmpmems[0])));
- macdbg_info->svmpmems_sz = 0;
- }
- MFREE(dhdp->osh, macdbg_info, sizeof(*macdbg_info));
-}
-
-void
-dhd_macdbg_event_handler(dhd_pub_t *dhdp, uint32 reason,
- uint8 *event_data, uint32 datalen)
-{
- d11regs_list_t *pd11regs;
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- uint d11regs_sz;
-
- DHD_TRACE(("%s: reason %d datalen %d\n", __FUNCTION__, reason, datalen));
- switch (reason) {
- case WLC_E_MACDBG_LIST_PSMX:
- /* Fall through */
- case WLC_E_MACDBG_LIST_PSM:
- pd11regs = MALLOCZ(dhdp->osh, datalen);
- if (pd11regs == NULL) {
- DHD_ERROR(("%s: NOMEM for len %d\n", __FUNCTION__, datalen));
- return;
- }
- memcpy(pd11regs, event_data, datalen);
- d11regs_sz = datalen / sizeof(pd11regs[0]);
- DHD_ERROR(("%s: d11regs %p d11regs_sz %d\n",
- __FUNCTION__, pd11regs, d11regs_sz));
- if (reason == WLC_E_MACDBG_LIST_PSM) {
- macdbg_info->pd11regs = pd11regs;
- macdbg_info->d11regs_sz = (uint16)d11regs_sz;
- } else {
- macdbg_info->pd11regs_x = pd11regs;
- macdbg_info->d11regsx_sz = (uint16)d11regs_sz;
- }
- break;
- case WLC_E_MACDBG_REGALL:
-#ifdef LINUX
- /* Schedule to work queue as this context could be ISR */
- dhd_schedule_macdbg_dump(dhdp);
-#else
- /* Dump PSMr */
- (void) dhd_macdbg_dumpmac(dhdp, NULL, 0, NULL, FALSE);
- /* Dump PSMx */
- (void) dhd_macdbg_dumpmac(dhdp, NULL, 0, NULL, TRUE);
- /* Dump SVMP mems */
- (void) dhd_macdbg_dumpsvmp(dhdp, NULL, 0, NULL);
-#endif
- break;
- default:
- DHD_ERROR(("%s: Unknown reason %d\n",
- __FUNCTION__, reason));
- }
- return;
-}
-
-static uint16
-_dhd_get_ihr16(macdbg_info_t *macdbg_info, uint16 addr, struct bcmstrbuf *b, bool verbose)
-{
- sdreg_t sdreg;
- uint16 val;
-
- sdreg.func = 2;
- sdreg.offset = (0x1000 | addr);
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- &sdreg, sizeof(sdreg), &val, sizeof(val), IOV_GET);
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: IHR16: read 0x%08x, size 2, value 0x%04x\n",
- (addr + 0x18001000), val);
- } else {
- printf("DEBUG: IHR16: read 0x%08x, size 2, value 0x%04x\n",
- (addr + 0x18001000), val);
- }
- }
- return val;
-}
-
-static uint32
-_dhd_get_ihr32(macdbg_info_t *macdbg_info, uint16 addr, struct bcmstrbuf *b, bool verbose)
-{
- sdreg_t sdreg;
- uint32 val;
-
- sdreg.func = 4;
- sdreg.offset = (0x1000 | addr);
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- &sdreg, sizeof(sdreg), &val, sizeof(val), IOV_GET);
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: IHR32: read 0x%08x, size 4, value 0x%08x\n",
- (addr + 0x18001000), val);
- } else {
- printf("DEBUG: IHR32: read 0x%08x, size 4, value 0x%08x\n",
- (addr + 0x18001000), val);
- }
- }
- return val;
-}
-
-static void
-_dhd_set_ihr16(macdbg_info_t *macdbg_info, uint16 addr, uint16 val,
- struct bcmstrbuf *b, bool verbose)
-{
- sdreg_t sdreg;
-
- sdreg.func = 2;
- sdreg.offset = (0x1000 | addr);
- sdreg.value = val;
-
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: IHR16: write 0x%08x, size 2, value 0x%04x\n",
- (addr + 0x18001000), val);
- } else {
- printf("DEBUG: IHR16: write 0x%08x, size 2, value 0x%04x\n",
- (addr + 0x18001000), val);
- }
- }
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- NULL, 0, &sdreg, sizeof(sdreg), IOV_SET);
-}
-
-static void
-_dhd_set_ihr32(macdbg_info_t *macdbg_info, uint16 addr, uint32 val,
- struct bcmstrbuf *b, bool verbose)
-{
- sdreg_t sdreg;
-
- sdreg.func = 4;
- sdreg.offset = (0x1000 | addr);
- sdreg.value = val;
-
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: IHR32: write 0x%08x, size 4, value 0x%08x\n",
- (addr + 0x18001000), val);
- } else {
- printf("DEBUG: IHR32: write 0x%08x, size 4, value 0x%08x\n",
- (addr + 0x18001000), val);
- }
- }
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- NULL, 0, &sdreg, sizeof(sdreg), IOV_SET);
-}
-
-static uint32
-_dhd_get_d11obj32(macdbg_info_t *macdbg_info, uint16 objaddr, uint32 sel,
- struct bcmstrbuf *b, bool verbose)
-{
- uint32 val;
- sdreg_t sdreg;
- sdreg.func = 4; // 4bytes by default.
- sdreg.offset = 0x1160;
-
- if (objaddr == 0xffff) {
- if (verbose) {
- goto objaddr_read;
- } else {
- goto objdata_read;
- }
- }
-
- if (objaddr & 0x3) {
- printf("%s: ERROR! Invalid addr 0x%x\n", __FUNCTION__, objaddr);
- }
-
- sdreg.value = (sel | (objaddr >> 2));
-
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: %s: Indirect: write 0x%08x, size %d, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, sdreg.value);
- } else {
- printf("DEBUG: %s: Indirect: write 0x%08x, size %d, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, sdreg.value);
- }
- }
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- NULL, 0, &sdreg, sizeof(sdreg), IOV_SET);
-
-objaddr_read:
- /* Give some time to obj addr register */
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- &sdreg, sizeof(sdreg), &val, sizeof(val), IOV_GET);
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: %s: Indirect: Read 0x%08x, size %d, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, val);
- } else {
- printf("DEBUG: %s: Indirect: Read 0x%08x, size %d, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, val);
- }
- }
-
-objdata_read:
- sdreg.offset = 0x1164;
- BUS_IOVAR_OP(macdbg_info->dhdp, "sbreg",
- &sdreg, sizeof(sdreg), &val, sizeof(val), IOV_GET);
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: %s: Indirect: Read 0x%08x, size %d, value 0x%04x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, val);
- } else {
- printf("DEBUG: %s: Indirect: Read 0x%08x, size %d, value 0x%04x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- (sdreg.offset + 0x18000000), sdreg.func, val);
- }
- }
- return val;
-}
-
-static uint16
-_dhd_get_d11obj16(macdbg_info_t *macdbg_info, uint16 objaddr,
- uint32 sel, d11obj_cache_t *obj_cache, struct bcmstrbuf *b, bool verbose)
-{
- uint32 val;
- if (obj_cache && obj_cache->cache_valid && ((obj_cache->sel ^ sel) & (0xffffff)) == 0) {
- if (obj_cache->addr32 == (objaddr & ~0x3)) {
- /* XXX: Same objaddr read as the previous one */
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: %s: Read cache value: "
- "addr32 0x%04x, sel 0x%08x, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- obj_cache->addr32, obj_cache->sel, obj_cache->val);
- } else {
- printf("DEBUG: %s: Read cache value: "
- "addr32 0x%04x, sel 0x%08x, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- obj_cache->addr32, obj_cache->sel, obj_cache->val);
- }
- }
- val = obj_cache->val;
- goto exit;
- } else if ((obj_cache->sel & 0x02000000) &&
- (obj_cache->addr32 + 4 == (objaddr & ~0x3))) {
- /* XXX: objaddr is auto incrementing, so just read objdata */
- if (verbose) {
- if (b) {
- bcm_bprintf(b, "DEBUG: %s: Read objdata only: "
- "addr32 0x%04x, sel 0x%08x, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- obj_cache->addr32, obj_cache->sel, obj_cache->val);
- } else {
- printf("DEBUG: %s: Read objdata only: "
- "addr32 0x%04x, sel 0x%08x, value 0x%08x\n",
- (sel & 0x00020000) ? "SCR":"SHM",
- obj_cache->addr32, obj_cache->sel, obj_cache->val);
- }
- }
- val = _dhd_get_d11obj32(macdbg_info, 0xffff, sel, b, verbose);
- goto exit;
- }
- }
- val = _dhd_get_d11obj32(macdbg_info, (objaddr & ~0x2), sel, b, verbose);
-exit:
- if (obj_cache) {
- obj_cache->addr32 = (objaddr & ~0x3);
- obj_cache->sel = sel;
- obj_cache->val = val;
- obj_cache->cache_valid = TRUE;
- }
- return (uint16)((objaddr & 0x2) ? (val >> 16) : val);
-}
-
-static int
-_dhd_print_d11reg(macdbg_info_t *macdbg_info, int idx, int type, uint16 addr, struct bcmstrbuf *b,
- d11obj_cache_t *obj_cache, bool verbose)
-{
- const char *regname[D11REG_TYPE_MAX] = D11REGTYPENAME;
- uint32 val;
-
- if (type == D11REG_TYPE_IHR32) {
- if ((addr & 0x3)) {
- printf("%s: ERROR! Invalid addr 0x%x\n", __FUNCTION__, addr);
- addr &= ~0x3;
- }
- val = _dhd_get_ihr32(macdbg_info, addr, b, verbose);
- if (b) {
- bcm_bprintf(b, "%-3d %s 0x%-4x = 0x%-8x\n",
- idx, regname[type], addr, val);
- } else {
- printf("%-3d %s 0x%-4x = 0x%-8x\n",
- idx, regname[type], addr, val);
- }
- } else {
- switch (type) {
- case D11REG_TYPE_IHR16: {
- if ((addr & 0x1)) {
- printf("%s: ERROR! Invalid addr 0x%x\n", __FUNCTION__, addr);
- addr &= ~0x1;
- }
- val = _dhd_get_ihr16(macdbg_info, addr, b, verbose);
- break;
- }
- case D11REG_TYPE_IHRX16:
- val = _dhd_get_d11obj16(macdbg_info, (addr - 0x400) << 1, 0x020b0000,
- obj_cache, b, verbose);
- break;
- case D11REG_TYPE_SCR:
- val = _dhd_get_d11obj16(macdbg_info, addr << 2, 0x02020000,
- obj_cache, b, verbose);
- break;
- case D11REG_TYPE_SCRX:
- val = _dhd_get_d11obj16(macdbg_info, addr << 2, 0x020a0000,
- obj_cache, b, verbose);
- break;
- case D11REG_TYPE_SHM:
- val = _dhd_get_d11obj16(macdbg_info, addr, 0x02010000,
- obj_cache, b, verbose);
- break;
- case D11REG_TYPE_SHMX:
- val = _dhd_get_d11obj16(macdbg_info, addr, 0x02090000,
- obj_cache, b, verbose);
- break;
- default:
- printf("Unrecognized type %d!\n", type);
- return 0;
- }
- if (b) {
- bcm_bprintf(b, "%-3d %s 0x%-4x = 0x%-4x\n",
- idx, regname[type], addr, val);
- } else {
- printf("%-3d %s 0x%-4x = 0x%-4x\n",
- idx, regname[type], addr, val);
- }
- }
- return 1;
-}
-
-static int
-_dhd_print_d11regs(macdbg_info_t *macdbg_info, d11regs_list_t *pregs,
- int start_idx, struct bcmstrbuf *b, bool verbose)
-{
- uint16 addr;
- int idx = 0;
- d11obj_cache_t obj_cache = {0, 0, 0, FALSE};
-
- addr = pregs->addr;
- if (pregs->type >= D11REG_TYPE_MAX) {
- printf("%s: wrong type %d\n", __FUNCTION__, pregs->type);
- return 0;
- }
- if (pregs->bitmap) {
- while (pregs->bitmap) {
- if (pregs->bitmap && (pregs->bitmap & 0x1)) {
- _dhd_print_d11reg(macdbg_info, (idx + start_idx), pregs->type,
- addr, b, &obj_cache, verbose);
- idx++;
- }
- pregs->bitmap = pregs->bitmap >> 1;
- addr += pregs->step;
- }
- } else {
- for (; idx < pregs->cnt; idx++) {
- _dhd_print_d11reg(macdbg_info, (idx + start_idx), pregs->type,
- addr, b, &obj_cache, verbose);
- addr += pregs->step;
- }
- }
- return idx;
-}
-
-static int
-_dhd_pd11regs_bylist(macdbg_info_t *macdbg_info, d11regs_list_t *reglist,
- uint16 reglist_sz, struct bcmstrbuf *b)
-{
- uint i, idx = 0;
-
- if (reglist != NULL && reglist_sz > 0) {
- for (i = 0; i < reglist_sz; i++) {
- DHD_TRACE(("%s %d %p %d\n", __FUNCTION__, __LINE__,
- ®list[i], reglist_sz));
- idx += _dhd_print_d11regs(macdbg_info, ®list[i], idx, b, FALSE);
- }
- }
- return idx;
-}
-
-int
-dhd_macdbg_dumpmac(dhd_pub_t *dhdp, char *buf, int buflen,
- int *outbuflen, bool dump_x)
-{
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- struct bcmstrbuf *b = NULL;
- struct bcmstrbuf bcmstrbuf;
- uint cnt = 0;
-
- DHD_TRACE(("%s %d %p %d %p %d %p %d\n", __FUNCTION__, __LINE__,
- buf, buflen, macdbg_info->pd11regs, macdbg_info->d11regs_sz,
- macdbg_info->pd11regs_x, macdbg_info->d11regsx_sz));
-
- if (buf && buflen > 0) {
- bcm_binit(&bcmstrbuf, buf, buflen);
- b = &bcmstrbuf;
- }
- if (!dump_x) {
- /* Dump PSMr */
- cnt += _dhd_pd11regs_bylist(macdbg_info, macdbg_info->pd11regs,
- macdbg_info->d11regs_sz, b);
- } else {
- /* Dump PSMx */
- cnt += _dhd_pd11regs_bylist(macdbg_info, macdbg_info->pd11regs_x,
- macdbg_info->d11regsx_sz, b);
- }
-
- if (b && outbuflen) {
- if ((uint)buflen > BCMSTRBUF_LEN(b)) {
- *outbuflen = buflen - BCMSTRBUF_LEN(b);
- } else {
- DHD_ERROR(("%s: buflen insufficient!\n", __FUNCTION__));
- *outbuflen = buflen;
- /* Do not return buftooshort to allow printing macregs we have got */
- }
- }
-
- return ((cnt > 0) ? BCME_OK : BCME_UNSUPPORTED);
-}
-
-int
-dhd_macdbg_pd11regs(dhd_pub_t *dhdp, char *params, int plen, char *buf, int buflen)
-{
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- dhd_pd11regs_param *pd11regs = (void *)params;
- dhd_pd11regs_buf *pd11regs_buf = (void *)buf;
- uint16 start_idx;
- bool verbose;
- d11regs_list_t reglist;
- struct bcmstrbuf *b = NULL;
- struct bcmstrbuf bcmstrbuf;
-
- start_idx = pd11regs->start_idx;
- verbose = pd11regs->verbose;
- memcpy(®list, pd11regs->plist, sizeof(reglist));
- memset(buf, '\0', buflen);
- bcm_binit(&bcmstrbuf, (char *)(pd11regs_buf->pbuf),
- (buflen - OFFSETOF(dhd_pd11regs_buf, pbuf)));
- b = &bcmstrbuf;
- pd11regs_buf->idx = (uint16)_dhd_print_d11regs(macdbg_info, ®list,
- start_idx, b, verbose);
-
- return ((pd11regs_buf->idx > 0) ? BCME_OK : BCME_ERROR);
-}
-
-int
-dhd_macdbg_reglist(dhd_pub_t *dhdp, char *buf, int buflen)
-{
- int err, desc_idx = 0;
- dhd_maclist_t *maclist = (dhd_maclist_t *)buf;
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- void *xtlvbuf_p = maclist->plist;
- uint16 xtlvbuflen = (uint16)buflen;
- xtlv_desc_t xtlv_desc[] = {
- {0, 0, NULL},
- {0, 0, NULL},
- {0, 0, NULL},
- {0, 0, NULL}
- };
-
- if (!macdbg_info->pd11regs) {
- err = BCME_NOTFOUND;
- goto exit;
- }
- ASSERT(macdbg_info->d11regs_sz > 0);
- xtlv_desc[desc_idx].type = DHD_MACLIST_XTLV_R;
- xtlv_desc[desc_idx].len =
- macdbg_info->d11regs_sz * (uint16)sizeof(*(macdbg_info->pd11regs));
- xtlv_desc[desc_idx].ptr = macdbg_info->pd11regs;
- desc_idx++;
-
- if (macdbg_info->pd11regs_x) {
- ASSERT(macdbg_info->d11regsx_sz);
- xtlv_desc[desc_idx].type = DHD_MACLIST_XTLV_X;
- xtlv_desc[desc_idx].len = macdbg_info->d11regsx_sz *
- (uint16)sizeof(*(macdbg_info->pd11regs_x));
- xtlv_desc[desc_idx].ptr = macdbg_info->pd11regs_x;
- desc_idx++;
- }
-
- if (macdbg_info->psvmpmems) {
- ASSERT(macdbg_info->svmpmems_sz);
- xtlv_desc[desc_idx].type = DHD_SVMPLIST_XTLV;
- xtlv_desc[desc_idx].len = macdbg_info->svmpmems_sz *
- (uint16)sizeof(*(macdbg_info->psvmpmems));
- xtlv_desc[desc_idx].ptr = macdbg_info->psvmpmems;
- desc_idx++;
- }
-
- err = bcm_pack_xtlv_buf_from_mem((uint8 **)&xtlvbuf_p, &xtlvbuflen,
- xtlv_desc, BCM_XTLV_OPTION_ALIGN32);
-
- maclist->version = 0; /* No version control for now anyway */
- maclist->bytes_len = (buflen - xtlvbuflen);
-
-exit:
- return err;
-}
-
-static int
-_dhd_print_svmps(macdbg_info_t *macdbg_info, svmp_list_t *psvmp,
- int start_idx, struct bcmstrbuf *b, bool verbose)
-{
- int idx;
- uint32 addr, mem_id, offset, prev_mem_id, prev_offset;
- uint16 cnt, val;
-
- BCM_REFERENCE(start_idx);
-
- /* Set tbl ID and tbl offset. */
- _dhd_set_ihr32(macdbg_info, 0x3fc, 0x30000d, b, verbose);
- _dhd_set_ihr32(macdbg_info, 0x3fc, 0x8000000e, b, verbose);
-
- addr = psvmp->addr;
- cnt = psvmp->cnt;
-
- /* In validate previous mem_id and offset */
- prev_mem_id = (uint32)(-1);
- prev_offset = (uint32)(-1);
-
- for (idx = 0; idx < cnt; idx++, addr++) {
- mem_id = (addr >> 15);
- offset = (addr & 0x7fff) >> 1;
-
- if (mem_id != prev_mem_id) {
- /* Set mem_id */
- _dhd_set_ihr32(macdbg_info, 0x3fc, ((mem_id & 0xffff0000) | 0x10),
- b, verbose);
- _dhd_set_ihr32(macdbg_info, 0x3fc, ((mem_id << 16) | 0xf),
- b, verbose);
- }
-
- if (offset != prev_offset) {
- /* XXX: Is this needed?
- * _dhd_set_ihr32(macdbg_info, 0x3fc, 0x30000d, b, verbose);
- */
- /* svmp offset */
- _dhd_set_ihr32(macdbg_info, 0x3fc, ((offset << 16) | 0xe),
- b, verbose);
- }
- /* Read hi or lo */
- _dhd_set_ihr16(macdbg_info, 0x3fc, ((addr & 0x1) ? 0x10 : 0xf), b, verbose);
- val = _dhd_get_ihr16(macdbg_info, 0x3fe, b, verbose);
- if (b) {
- bcm_bprintf(b, "0x%-4x 0x%-4x\n",
- addr, val);
-
- } else {
- printf("0x%-4x 0x%-4x\n",
- addr, val);
- }
- prev_mem_id = mem_id;
- prev_offset = offset;
- }
- return idx;
-}
-
-static int
-_dhd_psvmps_bylist(macdbg_info_t *macdbg_info, svmp_list_t *svmplist,
- uint16 svmplist_sz, struct bcmstrbuf *b)
-{
- uint i, idx = 0;
-
- if (svmplist != NULL && svmplist_sz > 0) {
- for (i = 0; i < svmplist_sz; i++) {
- DHD_TRACE(("%s %d %p %d\n", __FUNCTION__, __LINE__,
- &svmplist[i], svmplist_sz));
- idx += _dhd_print_svmps(macdbg_info, &svmplist[i], idx, b, FALSE);
- }
- }
- return idx;
-}
-
-int
-dhd_macdbg_dumpsvmp(dhd_pub_t *dhdp, char *buf, int buflen,
- int *outbuflen)
-{
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- struct bcmstrbuf *b = NULL;
- struct bcmstrbuf bcmstrbuf;
- uint cnt = 0;
-
- DHD_TRACE(("%s %d %p %d %p %d\n", __FUNCTION__, __LINE__,
- buf, buflen, macdbg_info->psvmpmems, macdbg_info->svmpmems_sz));
-
- if (buf && buflen > 0) {
- bcm_binit(&bcmstrbuf, buf, buflen);
- b = &bcmstrbuf;
- }
- cnt = _dhd_psvmps_bylist(macdbg_info, macdbg_info->psvmpmems,
- macdbg_info->svmpmems_sz, b);
-
- if (b && outbuflen) {
- if ((uint)buflen > BCMSTRBUF_LEN(b)) {
- *outbuflen = buflen - BCMSTRBUF_LEN(b);
- } else {
- DHD_ERROR(("%s: buflen insufficient!\n", __FUNCTION__));
- *outbuflen = buflen;
- /* Do not return buftooshort to allow printing macregs we have got */
- }
- }
-
- return ((cnt > 0) ? BCME_OK : BCME_UNSUPPORTED);
-}
-
-int
-dhd_macdbg_psvmpmems(dhd_pub_t *dhdp, char *params, int plen, char *buf, int buflen)
-{
- macdbg_info_t *macdbg_info = dhdp->macdbg_info;
- dhd_pd11regs_param *pd11regs = (void *)params;
- dhd_pd11regs_buf *pd11regs_buf = (void *)buf;
- uint16 start_idx;
- bool verbose;
- svmp_list_t reglist;
- struct bcmstrbuf *b = NULL;
- struct bcmstrbuf bcmstrbuf;
-
- start_idx = pd11regs->start_idx;
- verbose = pd11regs->verbose;
- memcpy(®list, pd11regs->plist, sizeof(reglist));
- memset(buf, '\0', buflen);
- bcm_binit(&bcmstrbuf, (char *)(pd11regs_buf->pbuf),
- (buflen - OFFSETOF(dhd_pd11regs_buf, pbuf)));
- b = &bcmstrbuf;
- pd11regs_buf->idx = (uint16)_dhd_print_svmps(macdbg_info, ®list,
- start_idx, b, verbose);
-
- return ((pd11regs_buf->idx > 0) ? BCME_OK : BCME_ERROR);
-}
-
-#endif /* BCMDBG */
+++ /dev/null
-/* D11 macdbg function prototypes for Broadcom 802.11abgn
- * Networking Adapter Device Drivers.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- *
- * $Id: dhd_macdbg.h 649388 2016-07-15 22:54:42Z shinuk $
- */
-
-#ifndef _dhd_macdbg_h_
-#define _dhd_macdbg_h_
-#ifdef BCMDBG
-#include <dngl_stats.h>
-#include <dhd.h>
-
-extern int dhd_macdbg_attach(dhd_pub_t *dhdp);
-extern void dhd_macdbg_detach(dhd_pub_t *dhdp);
-extern void dhd_macdbg_event_handler(dhd_pub_t *dhdp, uint32 reason,
- uint8 *event_data, uint32 datalen);
-extern int dhd_macdbg_dumpmac(dhd_pub_t *dhdp, char *buf, int buflen, int *outbuflen, bool dump_x);
-extern int dhd_macdbg_pd11regs(dhd_pub_t *dhdp, char *params, int plen, char *buf, int buflen);
-extern int dhd_macdbg_reglist(dhd_pub_t *dhdp, char *buf, int buflen);
-extern int dhd_macdbg_dumpsvmp(dhd_pub_t *dhdp, char *buf, int buflen, int *outbuflen);
-extern int dhd_macdbg_psvmpmems(dhd_pub_t *dhdp, char *params, int plen, char *buf, int buflen);
-#endif /* BCMDBG */
-#endif /* _dhd_macdbg_h_ */
void
dhd_set_bus_params(struct dhd_bus *bus)
{
- if (bus->dhd->conf->dhd_poll >= 0) {
- bus->poll = bus->dhd->conf->dhd_poll;
+ struct dhd_conf *conf = bus->dhd->conf;
+
+ if (conf->dhd_poll >= 0) {
+ bus->poll = conf->dhd_poll;
if (!bus->pollrate)
bus->pollrate = 1;
- printf("%s: set polling mode %d\n", __FUNCTION__, bus->dhd->conf->dhd_poll);
+ printf("%s: set polling mode %d\n", __FUNCTION__, conf->dhd_poll);
}
- if (bus->dhd->conf->d2h_intr_control >= 0)
- bus->d2h_intr_control = bus->dhd->conf->d2h_intr_control;
+ if (conf->d2h_intr_control >= 0)
+ bus->d2h_intr_control = conf->d2h_intr_control;
printf("d2h_intr_method -> %s(%d); d2h_intr_control -> %s(%d)\n",
bus->d2h_intr_method ? "PCIE_MSI" : "PCIE_INTX", bus->d2h_intr_method,
bus->d2h_intr_control ? "HOST_IRQ" : "D2H_INTMASK", bus->d2h_intr_control);
+
+ if (conf->aspm != -1) {
+ bool aspm = conf->aspm ? TRUE : FALSE;
+ dhd_bus_aspm_enable_rc_ep(bus, aspm);
+ }
+ if (conf->l1ss != -1) {
+ bool l1ss = conf->l1ss ? TRUE : FALSE;
+ dhd_bus_l1ss_enable_rc_ep(bus, l1ss);
+ }
}
/**
val = 1;
dhd_sbreg_op(dhd, addr, &val, FALSE);
}
+
+#define BUS_SLEEP_WAIT_CNT 3
+#define BUS_SLEEP_WAIT_MS 20
+int
+dhd_bus_sleep(dhd_pub_t *dhdp, bool sleep, uint32 *intstatus)
+{
+ dhd_bus_t *bus = dhdp->bus;
+ int active, cnt = 0;
+
+ if (bus) {
+ while ((active = dhd_os_check_wakelock_all(bus->dhd)) &&
+ (cnt < BUS_SLEEP_WAIT_CNT)) {
+ OSL_SLEEP(BUS_SLEEP_WAIT_MS);
+ cnt++;
+ }
+ } else {
+ DHD_ERROR(("bus is NULL\n"));
+ active = -1;
+ }
+
+ return active;
+}
goto exit;
}
- printf("PCI_PROBE: bus %X, slot %X,vendor %X, device %X"
+ printf("PCI_PROBE: bus 0x%X, slot 0x%X,vendor 0x%X, device 0x%X"
"(good PCI location)\n", pdev->bus->number,
PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device);
#if defined(WL_EXT_IAPSTA) && defined(DHD_LOSSLESS_ROAMING)
state = wl_ext_any_sta_handshaking(bus->dhd);
if (state) {
- DHD_ERROR(("handshaking %d\n", state));
+ if (dump_msg_level & DUMP_EAPOL_VAL)
+ DHD_ERROR(("handshaking %d\n", state));
return BCME_BUSY;
}
#endif /* WL_EXT_IAPSTA && DHD_LOSSLESS_ROAMING */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/wifi/dhd_static_buf.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-#define pr_fmt(fmt) "Wifi: %s: " fmt, __func__
-
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/wlan_plat.h>
#include <linux/amlogic/dhd_buf.h>
-#define DHD_STATIC_VERSION_STR "101.10.361.18 (wlan=r892223-20220519-1)"
-#define STATIC_ERROR_LEVEL (1 << 0)
-#define STATIC_TRACE_LEVEL (1 << 1)
-#define STATIC_MSG_LEVEL (1 << 0)
+#define DHD_STATIC_VERSION_STR "101.10.361.26 (wlan=r892223-20221011-1)"
+#define STATIC_ERROR_LEVEL BIT(0)
+#define STATIC_TRACE_LEVEL BIT(1)
+#define STATIC_MSG_LEVEL BIT(0)
uint static_msg_level = STATIC_ERROR_LEVEL | STATIC_MSG_LEVEL;
#define DHD_STATIC_MSG(x, args...) \
} \
} while (0)
-#define BCMDHD_SDIO
-#define BCMDHD_PCIE
-//#define BCMDHD_USB
-#define CONFIG_BCMDHD_VTS := y
-#define CONFIG_BCMDHD_DEBUG := y
+#ifdef DHD_STATIC_IN_DRIVER
+#if ANDROID_VERSION > 0
+#define CONFIG_BCMDHD_VTS { : = y}
+#define CONFIG_BCMDHD_DEBUG { : = y}
+#endif
+#else
+#define BCMSDIO
+#define BCMPCIE
+//#define BCMDBUS
+#define CONFIG_BCMDHD_VTS { : = y}
+#define CONFIG_BCMDHD_DEBUG { : = y}
//#define BCMDHD_UNUSE_MEM
+#endif
#ifndef MAX_NUM_ADAPTERS
#define MAX_NUM_ADAPTERS 1
enum dhd_prealloc_index {
DHD_PREALLOC_PROT = 0,
-#if defined(BCMDHD_SDIO)
+#if defined(BCMSDIO)
DHD_PREALLOC_RXBUF = 1,
DHD_PREALLOC_DATABUF = 2,
-#endif /* BCMDHD_SDIO */
+#endif /* BCMSDIO */
DHD_PREALLOC_OSL_BUF = 3,
DHD_PREALLOC_SKB_BUF = 4,
DHD_PREALLOC_WIPHY_ESCAN0 = 5,
DHD_PREALLOC_WIPHY_ESCAN1 = 6,
DHD_PREALLOC_DHD_INFO = 7,
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
DHD_PREALLOC_DHD_WLFC_INFO = 8,
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
-#ifdef BCMDHD_PCIE
+#endif /* BCMSDIO | BCMDBUS */
+#ifdef BCMPCIE
DHD_PREALLOC_IF_FLOW_LKUP = 9,
-#endif /* BCMDHD_PCIE */
+#endif /* BCMPCIE */
DHD_PREALLOC_MEMDUMP_BUF = 10,
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
DHD_PREALLOC_MEMDUMP_RAM = 11,
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
DHD_PREALLOC_DHD_WLFC_HANGER = 12,
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
+#endif /* BCMSDIO | BCMDBUS */
DHD_PREALLOC_PKTID_MAP = 13,
DHD_PREALLOC_PKTID_MAP_IOCTL = 14,
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
};
#define STATIC_BUF_MAX_NUM 20
-#define STATIC_BUF_SIZE (PAGE_SIZE*2)
+#define STATIC_BUF_SIZE (PAGE_SIZE * 2)
#ifndef CUSTOM_LOG_DUMP_BUFSIZE_MB
-#define CUSTOM_LOG_DUMP_BUFSIZE_MB 4 /* DHD_LOG_DUMP_BUF_SIZE 4 MB static memory in kernel */
+/* DHD_LOG_DUMP_BUF_SIZE 4 MB static memory in kernel */
+#define CUSTOM_LOG_DUMP_BUFSIZE_MB 4
#endif /* CUSTOM_LOG_DUMP_BUFSIZE_MB */
#define DHD_PREALLOC_PROT_SIZE (16 * 1024)
#define DHD_PREALLOC_DATABUF_SIZE (64 * 1024)
#define DHD_PREALLOC_OSL_BUF_SIZE (STATIC_BUF_MAX_NUM * STATIC_BUF_SIZE)
#define DHD_PREALLOC_WIPHY_ESCAN0_SIZE (64 * 1024)
-#define DHD_PREALLOC_DHD_INFO_SIZE (36 * 1024)
+#define DHD_PREALLOC_DHD_INFO_SIZE (43 * 1024)
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
#define DHD_PREALLOC_MEMDUMP_RAM_SIZE (1290 * 1024)
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
#endif /* CONFIG_64BIT */
#define WLAN_DHD_MEMDUMP_SIZE (800 * 1024)
-#define DHD_SKB_1PAGE_BUFSIZE (PAGE_SIZE*1)
-#define DHD_SKB_2PAGE_BUFSIZE (PAGE_SIZE*2)
-#define DHD_SKB_4PAGE_BUFSIZE (PAGE_SIZE*4)
+#define DHD_SKB_1PAGE_BUFSIZE (PAGE_SIZE * 1)
+#define DHD_SKB_2PAGE_BUFSIZE (PAGE_SIZE * 2)
+#define DHD_SKB_4PAGE_BUFSIZE (PAGE_SIZE * 4)
-#ifdef BCMDHD_PCIE
+#ifdef BCMPCIE
#define DHD_SKB_1PAGE_BUF_NUM 0
#define DHD_SKB_2PAGE_BUF_NUM 192
-#elif defined(BCMDHD_SDIO)
+#elif defined(BCMSDIO)
#define DHD_SKB_1PAGE_BUF_NUM 8
#define DHD_SKB_2PAGE_BUF_NUM 8
-#endif /* BCMDHD_PCIE */
+#endif /* BCMPCIE */
#define DHD_SKB_4PAGE_BUF_NUM 1
/* The number is defined in linux_osl.c
* WLAN_SKB_1_2PAGE_BUF_NUM => STATIC_PKT_1_2PAGE_NUM
* WLAN_SKB_BUF_NUM => STATIC_PKT_MAX_NUM
*/
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
+#if defined(BCMSDIO) || defined(BCMPCIE)
#define WLAN_SKB_1_2PAGE_BUF_NUM ((DHD_SKB_1PAGE_BUF_NUM) + \
(DHD_SKB_2PAGE_BUF_NUM))
#define WLAN_SKB_BUF_NUM ((WLAN_SKB_1_2PAGE_BUF_NUM) + (DHD_SKB_4PAGE_BUF_NUM))
#endif
-void *wlan_static_prot[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_rxbuf [MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_databuf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_osl_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_scan_buf0[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_scan_buf1[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_info_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_wlfc_info_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_if_flow_lkup[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_memdump_ram_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_wlfc_hanger_buf[MAX_NUM_ADAPTERS] = {NULL};
+void *wlan_static_prot[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_rxbuf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_databuf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_osl_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_scan_buf0[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_scan_buf1[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_info_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_wlfc_info_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_if_flow_lkup[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_memdump_ram_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_wlfc_hanger_buf[MAX_NUM_ADAPTERS] = {};
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
-void *wlan_static_dhd_log_dump_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_log_dump_buf_ex[MAX_NUM_ADAPTERS] = {NULL};
+void *wlan_static_dhd_log_dump_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_log_dump_buf_ex[MAX_NUM_ADAPTERS] = {};
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
-void *wlan_static_wl_escan_info_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_fw_verbose_ring_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_fw_event_ring_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_dhd_event_ring_buf[MAX_NUM_ADAPTERS] = {NULL};
-void *wlan_static_nan_event_ring_buf[MAX_NUM_ADAPTERS] = {NULL};
+void *wlan_static_wl_escan_info_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_fw_verbose_ring_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_fw_event_ring_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_dhd_event_ring_buf[MAX_NUM_ADAPTERS] = {};
+void *wlan_static_nan_event_ring_buf[MAX_NUM_ADAPTERS] = {};
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
-static struct sk_buff *wlan_static_skb[MAX_NUM_ADAPTERS][WLAN_SKB_BUF_NUM] = {NULL};
-#endif /* BCMDHD_SDIO | BCMDHD_PCIE */
+#if defined(BCMSDIO) || defined(BCMPCIE)
+static struct sk_buff *wlan_static_skb[MAX_NUM_ADAPTERS][WLAN_SKB_BUF_NUM] = {};
+#endif /* BCMSDIO | BCMPCIE */
void *
bcmdhd_mem_prealloc(
#endif
#if defined(BCMDHD_MDRIVER) && !defined(DHD_STATIC_IN_DRIVER)
- DHD_STATIC_MSG("bus_type %d, index %d, sectoin %d, size %ld\n",
+ DHD_STATIC_MSG("bus_type %d, index %d, section %d, size %ld\n",
bus_type, index, section, size);
#else
- DHD_STATIC_MSG("sectoin %d, size %ld\n", section, size);
+ DHD_STATIC_MSG("section %d, size %ld\n", section, size);
#endif
if (section == DHD_PREALLOC_PROT)
return wlan_static_prot[index];
-#if defined(BCMDHD_SDIO)
+#if defined(BCMSDIO)
if (section == DHD_PREALLOC_RXBUF)
return wlan_static_rxbuf[index];
if (section == DHD_PREALLOC_DATABUF)
return wlan_static_databuf[index];
-#endif /* BCMDHD_SDIO */
+#endif /* BCMSDIO */
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
+#if defined(BCMSDIO) || defined(BCMPCIE)
if (section == DHD_PREALLOC_SKB_BUF)
return wlan_static_skb[index];
-#endif /* BCMDHD_SDIO | BCMDHD_PCIE */
+#endif /* BCMSDIO | BCMPCIE */
if (section == DHD_PREALLOC_WIPHY_ESCAN0)
return wlan_static_scan_buf0[index];
}
return wlan_static_dhd_info_buf[index];
}
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
if (section == DHD_PREALLOC_DHD_WLFC_INFO) {
if (size > WLAN_DHD_WLFC_BUF_SIZE) {
DHD_STATIC_ERROR("request DHD_WLFC_INFO(%lu) > %d\n",
}
return wlan_static_dhd_wlfc_info_buf[index];
}
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
-#ifdef BCMDHD_PCIE
+#endif /* BCMSDIO | BCMDBUS */
+#ifdef BCMPCIE
if (section == DHD_PREALLOC_IF_FLOW_LKUP) {
if (size > DHD_PREALLOC_IF_FLOW_LKUP_SIZE) {
DHD_STATIC_ERROR("request DHD_IF_FLOW_LKUP(%lu) > %d\n",
}
return wlan_static_if_flow_lkup[index];
}
-#endif /* BCMDHD_PCIE */
+#endif /* BCMPCIE */
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
if (section == DHD_PREALLOC_MEMDUMP_RAM) {
if (size > DHD_PREALLOC_MEMDUMP_RAM_SIZE) {
return wlan_static_dhd_memdump_ram_buf[index];
}
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
if (section == DHD_PREALLOC_DHD_WLFC_HANGER) {
if (size > DHD_PREALLOC_DHD_WLFC_HANGER_SIZE) {
DHD_STATIC_ERROR("request DHD_WLFC_HANGER(%lu) > %d\n",
}
return wlan_static_dhd_wlfc_hanger_buf[index];
}
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
+#endif /* BCMSDIO | BCMDBUS */
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
if (section == DHD_PREALLOC_DHD_LOG_DUMP_BUF) {
if (size > DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE) {
static void
dhd_deinit_wlan_mem(int index)
{
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
+#if defined(BCMSDIO) || defined(BCMPCIE)
int i;
-#endif /* BCMDHD_SDIO | BCMDHD_PCIE */
+#endif /* BCMSDIO | BCMPCIE */
if (wlan_static_prot[index])
kfree(wlan_static_prot[index]);
-#if defined(BCMDHD_SDIO)
+#if defined(BCMSDIO)
if (wlan_static_rxbuf[index])
kfree(wlan_static_rxbuf[index]);
if (wlan_static_databuf[index])
kfree(wlan_static_databuf[index]);
-#endif /* BCMDHD_SDIO */
+#endif /* BCMSDIO */
if (wlan_static_osl_buf[index])
kfree(wlan_static_osl_buf[index]);
if (wlan_static_scan_buf0[index])
kfree(wlan_static_scan_buf1[index]);
if (wlan_static_dhd_info_buf[index])
kfree(wlan_static_dhd_info_buf[index]);
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
if (wlan_static_dhd_wlfc_info_buf[index])
kfree(wlan_static_dhd_wlfc_info_buf[index]);
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
-#ifdef BCMDHD_PCIE
+#endif /* BCMSDIO | BCMDBUS */
+#ifdef BCMPCIE
if (wlan_static_if_flow_lkup[index])
kfree(wlan_static_if_flow_lkup[index]);
-#endif /* BCMDHD_PCIE */
+#endif /* BCMPCIE */
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
if (wlan_static_dhd_memdump_ram_buf[index])
kfree(wlan_static_dhd_memdump_ram_buf[index]);
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
+#if defined(BCMSDIO) || defined(BCMDBUS)
if (wlan_static_dhd_wlfc_hanger_buf[index])
kfree(wlan_static_dhd_wlfc_hanger_buf[index]);
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
+#endif /* BCMSDIO | BCMDBUS */
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
if (wlan_static_dhd_log_dump_buf[index])
kfree(wlan_static_dhd_log_dump_buf[index]);
kfree(wlan_static_nan_event_ring_buf[index]);
#endif /* BCMDHD_UNUSE_MEM */
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
+#if defined(BCMSDIO) || defined(BCMPCIE)
for (i=0; i<WLAN_SKB_BUF_NUM; i++) {
if (wlan_static_skb[index][i])
dev_kfree_skb(wlan_static_skb[index][i]);
}
-#endif /* BCMDHD_SDIO | BCMDHD_PCIE */
+#endif /* BCMSDIO | BCMPCIE */
return;
}
static int
dhd_init_wlan_mem(int index, unsigned int all_buf)
{
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
+#if defined(BCMSDIO) || defined(BCMPCIE)
int i;
#endif
unsigned long size = 0;
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_PCIE)
- for (i=0; i <WLAN_SKB_BUF_NUM; i++) {
+#if defined(BCMSDIO) || defined(BCMPCIE)
+ for (i = 0; i < WLAN_SKB_BUF_NUM; i++)
wlan_static_skb[index][i] = NULL;
- }
for (i = 0; i < DHD_SKB_1PAGE_BUF_NUM; i++) {
wlan_static_skb[index][i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
- if (!wlan_static_skb[index][i]) {
+ if (!wlan_static_skb[index][i])
goto err_mem_alloc;
- }
size += DHD_SKB_1PAGE_BUFSIZE;
- DHD_STATIC_TRACE("sectoin %d skb[%d], size=%ld\n",
+ DHD_STATIC_TRACE("section %d skb[%d], size=%ld\n",
DHD_PREALLOC_SKB_BUF, i, DHD_SKB_1PAGE_BUFSIZE);
}
for (i = DHD_SKB_1PAGE_BUF_NUM; i < WLAN_SKB_1_2PAGE_BUF_NUM; i++) {
wlan_static_skb[index][i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
- if (!wlan_static_skb[index][i]) {
+ if (!wlan_static_skb[index][i])
goto err_mem_alloc;
- }
size += DHD_SKB_2PAGE_BUFSIZE;
- DHD_STATIC_TRACE("sectoin %d skb[%d], size=%ld\n",
+ DHD_STATIC_TRACE("section %d skb[%d], size=%ld\n",
DHD_PREALLOC_SKB_BUF, i, DHD_SKB_2PAGE_BUFSIZE);
}
-#endif /* BCMDHD_SDIO | BCMDHD_PCIE */
+#endif /* BCMSDIO | BCMPCIE */
if (all_buf == 1) {
-#if defined(BCMDHD_SDIO)
- wlan_static_skb[index][i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
- if (!wlan_static_skb[index][i])
- goto err_mem_alloc;
- size += DHD_SKB_4PAGE_BUFSIZE;
- DHD_STATIC_TRACE("sectoin %d skb[%d], size=%ld\n",
- DHD_PREALLOC_SKB_BUF, i, DHD_SKB_4PAGE_BUFSIZE);
-#endif /* BCMDHD_SDIO */
+#if defined(BCMSDIO)
+ wlan_static_skb[index][i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
+ if (!wlan_static_skb[index][i])
+ goto err_mem_alloc;
+ size += DHD_SKB_4PAGE_BUFSIZE;
+ DHD_STATIC_TRACE("section %d skb[%d], size=%ld\n",
+ DHD_PREALLOC_SKB_BUF, i, DHD_SKB_4PAGE_BUFSIZE);
+#endif /* BCMSDIO */
- wlan_static_prot[index] = kmalloc(DHD_PREALLOC_PROT_SIZE, GFP_KERNEL);
- if (!wlan_static_prot[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_PROT_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_PROT, DHD_PREALLOC_PROT_SIZE);
+ wlan_static_prot[index] = kmalloc(DHD_PREALLOC_PROT_SIZE, GFP_KERNEL);
+ if (!wlan_static_prot[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_PROT_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_PROT, DHD_PREALLOC_PROT_SIZE);
-#if defined(BCMDHD_SDIO)
- wlan_static_rxbuf[index] = kmalloc(DHD_PREALLOC_RXBUF_SIZE, GFP_KERNEL);
- if (!wlan_static_rxbuf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_RXBUF_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_RXBUF, DHD_PREALLOC_RXBUF_SIZE);
+#if defined(BCMSDIO)
+ wlan_static_rxbuf[index] = kmalloc(DHD_PREALLOC_RXBUF_SIZE, GFP_KERNEL);
+ if (!wlan_static_rxbuf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_RXBUF_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_RXBUF, DHD_PREALLOC_RXBUF_SIZE);
- wlan_static_databuf[index] = kmalloc(DHD_PREALLOC_DATABUF_SIZE, GFP_KERNEL);
- if (!wlan_static_databuf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_DATABUF_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DATABUF, DHD_PREALLOC_DATABUF_SIZE);
-#endif /* BCMDHD_SDIO */
+ wlan_static_databuf[index] = kmalloc(DHD_PREALLOC_DATABUF_SIZE, GFP_KERNEL);
+ if (!wlan_static_databuf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_DATABUF_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DATABUF, DHD_PREALLOC_DATABUF_SIZE);
+#endif /* BCMSDIO */
- wlan_static_osl_buf[index] = kmalloc(DHD_PREALLOC_OSL_BUF_SIZE, GFP_KERNEL);
- if (!wlan_static_osl_buf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_OSL_BUF_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%ld\n",
- DHD_PREALLOC_OSL_BUF, DHD_PREALLOC_OSL_BUF_SIZE);
+ wlan_static_osl_buf[index] = kmalloc(DHD_PREALLOC_OSL_BUF_SIZE, GFP_KERNEL);
+ if (!wlan_static_osl_buf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_OSL_BUF_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%ld\n",
+ DHD_PREALLOC_OSL_BUF, DHD_PREALLOC_OSL_BUF_SIZE);
- wlan_static_scan_buf0[index] = kmalloc(DHD_PREALLOC_WIPHY_ESCAN0_SIZE, GFP_KERNEL);
- if (!wlan_static_scan_buf0[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_WIPHY_ESCAN0_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_WIPHY_ESCAN0, DHD_PREALLOC_WIPHY_ESCAN0_SIZE);
+ wlan_static_scan_buf0[index] = kmalloc(DHD_PREALLOC_WIPHY_ESCAN0_SIZE, GFP_KERNEL);
+ if (!wlan_static_scan_buf0[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_WIPHY_ESCAN0_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_WIPHY_ESCAN0, DHD_PREALLOC_WIPHY_ESCAN0_SIZE);
- wlan_static_dhd_info_buf[index] = kmalloc(DHD_PREALLOC_DHD_INFO_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_info_buf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_DHD_INFO_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_INFO, DHD_PREALLOC_DHD_INFO_SIZE);
+ wlan_static_dhd_info_buf[index] = kmalloc(DHD_PREALLOC_DHD_INFO_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_info_buf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_DHD_INFO_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_INFO, DHD_PREALLOC_DHD_INFO_SIZE);
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
- wlan_static_dhd_wlfc_info_buf[index] = kmalloc(WLAN_DHD_WLFC_BUF_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_wlfc_info_buf[index])
- goto err_mem_alloc;
- size += WLAN_DHD_WLFC_BUF_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_WLFC_INFO, WLAN_DHD_WLFC_BUF_SIZE);
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
-
-#ifdef BCMDHD_PCIE
- wlan_static_if_flow_lkup[index] = kmalloc(DHD_PREALLOC_IF_FLOW_LKUP_SIZE, GFP_KERNEL);
- if (!wlan_static_if_flow_lkup[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_IF_FLOW_LKUP_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_IF_FLOW_LKUP, DHD_PREALLOC_IF_FLOW_LKUP_SIZE);
-#endif /* BCMDHD_PCIE */
+#if defined(BCMSDIO) || defined(BCMDBUS)
+ wlan_static_dhd_wlfc_info_buf[index] = kmalloc(WLAN_DHD_WLFC_BUF_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_wlfc_info_buf[index])
+ goto err_mem_alloc;
+ size += WLAN_DHD_WLFC_BUF_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_WLFC_INFO, WLAN_DHD_WLFC_BUF_SIZE);
+#endif /* BCMSDIO | BCMDBUS */
+
+#ifdef BCMPCIE
+ wlan_static_if_flow_lkup[index] = kmalloc(DHD_PREALLOC_IF_FLOW_LKUP_SIZE, GFP_KERNEL);
+ if (!wlan_static_if_flow_lkup[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_IF_FLOW_LKUP_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_IF_FLOW_LKUP, DHD_PREALLOC_IF_FLOW_LKUP_SIZE);
+#endif /* BCMPCIE */
}
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
if (!wlan_static_dhd_memdump_ram_buf[index])
goto err_mem_alloc;
size += DHD_PREALLOC_MEMDUMP_RAM_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
+ DHD_STATIC_TRACE("section %d, size=%d\n",
DHD_PREALLOC_MEMDUMP_RAM, DHD_PREALLOC_MEMDUMP_RAM_SIZE);
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
if (all_buf == 1) {
-#if defined(BCMDHD_SDIO) || defined(BCMDHD_USB)
- wlan_static_dhd_wlfc_hanger_buf[index] = kmalloc(DHD_PREALLOC_DHD_WLFC_HANGER_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_wlfc_hanger_buf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_DHD_WLFC_HANGER_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_WLFC_HANGER, DHD_PREALLOC_DHD_WLFC_HANGER_SIZE);
-#endif /* BCMDHD_SDIO | BCMDHD_USB */
+#if defined(BCMSDIO) || defined(BCMDBUS)
+ wlan_static_dhd_wlfc_hanger_buf[index] = kmalloc(DHD_PREALLOC_DHD_WLFC_HANGER_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_wlfc_hanger_buf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_DHD_WLFC_HANGER_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_WLFC_HANGER, DHD_PREALLOC_DHD_WLFC_HANGER_SIZE);
+#endif /* BCMSDIO | BCMDBUS */
#if defined(CONFIG_BCMDHD_VTS) || defined(CONFIG_BCMDHD_DEBUG)
- wlan_static_dhd_log_dump_buf[index] = kmalloc(DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_log_dump_buf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_LOG_DUMP_BUF, DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE);
+ wlan_static_dhd_log_dump_buf[index] = kmalloc(DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_log_dump_buf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_LOG_DUMP_BUF, DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE);
- wlan_static_dhd_log_dump_buf_ex[index] = kmalloc(DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_log_dump_buf_ex[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX, DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE);
+ wlan_static_dhd_log_dump_buf_ex[index] = kmalloc(DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_log_dump_buf_ex[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX, DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE);
#endif /* CONFIG_BCMDHD_VTS | CONFIG_BCMDHD_DEBUG */
- wlan_static_wl_escan_info_buf[index] = kmalloc(DHD_PREALLOC_WL_ESCAN_SIZE, GFP_KERNEL);
- if (!wlan_static_wl_escan_info_buf[index])
- goto err_mem_alloc;
- size += DHD_PREALLOC_WL_ESCAN_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_WL_ESCAN, DHD_PREALLOC_WL_ESCAN_SIZE);
+ wlan_static_wl_escan_info_buf[index] = kmalloc(DHD_PREALLOC_WL_ESCAN_SIZE, GFP_KERNEL);
+ if (!wlan_static_wl_escan_info_buf[index])
+ goto err_mem_alloc;
+ size += DHD_PREALLOC_WL_ESCAN_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_WL_ESCAN, DHD_PREALLOC_WL_ESCAN_SIZE);
}
wlan_static_fw_verbose_ring_buf[index] = kmalloc(FW_VERBOSE_RING_SIZE, GFP_KERNEL);
if (!wlan_static_fw_verbose_ring_buf[index])
goto err_mem_alloc;
size += FW_VERBOSE_RING_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
+ DHD_STATIC_TRACE("section %d, size=%d\n",
DHD_PREALLOC_FW_VERBOSE_RING, FW_VERBOSE_RING_SIZE);
if (all_buf == 1) {
- wlan_static_fw_event_ring_buf[index] = kmalloc(FW_EVENT_RING_SIZE, GFP_KERNEL);
- if (!wlan_static_fw_event_ring_buf[index])
- goto err_mem_alloc;
- size += FW_EVENT_RING_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_FW_EVENT_RING, FW_EVENT_RING_SIZE);
+ wlan_static_fw_event_ring_buf[index] = kmalloc(FW_EVENT_RING_SIZE, GFP_KERNEL);
+ if (!wlan_static_fw_event_ring_buf[index])
+ goto err_mem_alloc;
+ size += FW_EVENT_RING_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_FW_EVENT_RING, FW_EVENT_RING_SIZE);
- wlan_static_dhd_event_ring_buf[index] = kmalloc(DHD_EVENT_RING_SIZE, GFP_KERNEL);
- if (!wlan_static_dhd_event_ring_buf[index])
- goto err_mem_alloc;
- size += DHD_EVENT_RING_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_DHD_EVENT_RING, DHD_EVENT_RING_SIZE);
+ wlan_static_dhd_event_ring_buf[index] = kmalloc(DHD_EVENT_RING_SIZE, GFP_KERNEL);
+ if (!wlan_static_dhd_event_ring_buf[index])
+ goto err_mem_alloc;
+ size += DHD_EVENT_RING_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_DHD_EVENT_RING, DHD_EVENT_RING_SIZE);
#if defined(BCMDHD_UNUSE_MEM)
- wlan_static_nan_event_ring_buf[index] = kmalloc(NAN_EVENT_RING_SIZE, GFP_KERNEL);
- if (!wlan_static_nan_event_ring_buf[index])
- goto err_mem_alloc;
- size += NAN_EVENT_RING_SIZE;
- DHD_STATIC_TRACE("sectoin %d, size=%d\n",
- DHD_PREALLOC_NAN_EVENT_RING, NAN_EVENT_RING_SIZE);
+ wlan_static_nan_event_ring_buf[index] = kmalloc(NAN_EVENT_RING_SIZE, GFP_KERNEL);
+ if (!wlan_static_nan_event_ring_buf[index])
+ goto err_mem_alloc;
+ size += NAN_EVENT_RING_SIZE;
+ DHD_STATIC_TRACE("section %d, size=%d\n",
+ DHD_PREALLOC_NAN_EVENT_RING, NAN_EVENT_RING_SIZE);
#endif /* BCMDHD_UNUSE_MEM */
}
- DHD_STATIC_MSG("prealloc ok for index %d: %ld(%ldK)\n", index, size, size/1024);
+ DHD_STATIC_MSG("prealloc ok for index %d: %ld(%ldK)\n", index, size, size / 1024);
return 0;
err_mem_alloc:
return ret;
}
+#if 0
#ifdef DHD_STATIC_IN_DRIVER
void
#else
for (i=0; i<MAX_NUM_ADAPTERS; i++)
dhd_deinit_wlan_mem(i);
}
+#endif
#ifndef DHD_STATIC_IN_DRIVER
EXPORT_SYMBOL(bcmdhd_init_wlan_mem);
+++ /dev/null
-
-/*
- * Firmware trace implementation common header file between DHD and the firmware.
- *
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Secret:>>
- */
-
-#ifndef _bcm_fwtrace_h
-#define _bcm_fwtrace_h
-
-#include <bcmpcie.h>
-#include <bcmmsgbuf.h>
-
-#define FWTRACE_VERSION 1u
-
-/*
- * Number of trace entries per trace buffer.
- * Both DHD and FW must use same number.
- */
-#define FWTRACE_NUM_ENTRIES (2u * 1024u) /* 2KB, power of 2 */
-/*
- * Number of buffers provided by the host.
- * DHD may allocate smaller number of trace buffers based on continuous memory availability.
- */
-#define FWTRACE_NUM_HOST_BUFFERS 32u
-
-/* Magic value to differentiate between regural trace data Vs other blobs */
-#define FWTRACE_BLOB_MAGIC (0xFFu)
-#define FWTRACE_BLOB_MGIC_SHIFT (24u)
-
-/* The lower 24 bits of the fwtrace_entry->func_ptr is used to push different type of
- * information to host such as ACK bitmap, interrupts DPC is going to process etc.
- */
-#define FWTRACE_BLOB_TYPE_MASK (0xFFFFFFu)
-#define FWTRACE_BLOB_TYPE_SHIFT (0)
-
-#define FWTRACE_BLOB_TYPE_NUM_PKTS (0x1u)
-#define FWTRACE_BLOB_TYPE_ACK_BMAP1 (0x2u) /* Ack bits (0-31 ) */
-#define FWTRACE_BLOB_TYPE_ACK_BMAP2 (0x4u) /* Ack bits (32-63) */
-#define FWTRACE_BLOB_TYPE_ACK_BMAP3 (0x8u) /* Ack bits (64-95) */
-#define FWTRACE_BLOB_TYPE_ACK_BMAP4 (0x10u) /* Ack bits (96-127) */
-#define FWTRACE_BLOB_TYPE_INTR1 (0x20u) /* interrupts the DPC is going to process */
-#define FWTRACE_BLOB_TYPE_INTR2 (0x40u) /* interrupts the DPC is going to process */
-/* The blob data for LFRAGS_INFO will contain
- * Bit31-16: Available buffer/lfrags info
- * Bit15-0 : # of lfrags requested by FW in the fetch request
- */
-#define FWTRACE_BLOB_TYPE_LFRAGS_INFO (0x80u) /* Available and fetch requested lfrags */
-
-#define FWTRACE_BLOB_DATA_MASK (0xFFFFFu)
-
-#define FWTRACE_BLOB_ADD_CUR (0) /* updates with in the existing trace entry */
-#define FWTRACE_BLOB_ADD_NEW (1u) /* Creates new trace entry */
-
-/*
- * Host sends host memory location to FW via iovar.
- * FW will push trace information here.
- */
-typedef struct fwtrace_hostaddr_info {
- bcm_addr64_t haddr; /* host address for the firmware to DMA trace data */
- uint32 buf_len;
- uint32 num_bufs; /* Number of trace buffers */
-} fwtrace_hostaddr_info_t;
-
-/*
- * Eact trace info buffer pushed to host will have this header.
- */
-typedef struct fwtrace_dma_header_info {
- uint16 length; /* length in bytes */
- uint16 seq_num; /* sequence number */
- uint32 version;
- uint32 hostmem_addr;
-} fwtrace_dma_header_info_t;
-
-/*
- * Content of each trace entry
- */
-typedef struct fwtrace_entry {
- uint32 func_ptr;
- /* How the pkts_cycle being used?
- * Bit31-23: (If present) Used to indicate the number of packets processed by the
- * current function
- * Bit22-1 : Used to indicate the CPU cycles(in units of 2Cycles). So to get the actual
- * cycles multiply the cycles by 2.
- * Bit0 : Used to indicate whether this entry is valid or not
- */
- uint32 pkts_cycles;
-} fwtrace_entry_t;
-
-#define FWTRACE_CYCLES_VALID (1u << 0u)
-
-/*
- * Format of firmware trace buffer pushed to host memory
- */
-typedef struct fwtrace_buf {
- fwtrace_dma_header_info_t info; /* includes the sequence number and the length */
- fwtrace_entry_t entry[FWTRACE_NUM_ENTRIES];
-} fwtrace_buf_t;
-
-void fwtracing_add_blob(uint32 update_type, uint32 trace_type, uint32 blob);
-#endif /* _bcm_fwtrace_h */
+++ /dev/null
-/*
- * Monitor Mode routines.
- * This header file housing the define and function use by DHD
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-#ifndef _BCMWIFI_MONITOR_H_
-#define _BCMWIFI_MONITOR_H_
-
-#include <monitor.h>
-
-typedef struct monitor_info monitor_info_t;
-
-typedef struct monitor_pkt_ts {
- union {
- uint32 ts_low; /* time stamp low 32 bits */
- uint32 reserved; /* If timestamp not used */
- };
- union {
- uint32 ts_high; /* time stamp high 28 bits */
- union {
- uint32 ts_high_ext :28; /* time stamp high 28 bits */
- uint32 clk_id_ext :3; /* clock ID source */
- uint32 phase :1; /* Phase bit */
- uint32 marker_ext;
- };
- };
-} monitor_pkt_ts_t;
-
-typedef struct monitor_pkt_info {
- uint32 marker;
- /* timestamp */
- monitor_pkt_ts_t ts;
-} monitor_pkt_info_t;
-
-typedef struct monitor_pkt_rssi {
- int8 dBm; /* number of full dBms */
- /* sub-dbm resolution */
- int8 decidBm; /* sub dBms : value after the decimal point */
-} monitor_pkt_rssi_t;
-
-/* structure to add specific information to rxsts structure
- * otherwise non available to all modules like core RSSI and qdbm resolution
-*/
-
-typedef struct monitor_pkt_rxsts {
- wl_rxsts_t *rxsts;
- uint8 corenum; /* number of cores/antennas */
- monitor_pkt_rssi_t rxpwr[4];
-} monitor_pkt_rxsts_t;
-
-#define HE_EXTRACT_FROM_PLCP(plcp, ppdu_type, field) \
- (getbits(plcp, D11_PHY_HDR_LEN, \
- HE_ ## ppdu_type ## _PPDU_ ## field ## _IDX, \
- HE_ ## ppdu_type ## _PPDU_ ## field ## _FSZ))
-
-#define HE_PACK_RTAP_FROM_PLCP(plcp, ppdu_type, field) \
- (HE_EXTRACT_FROM_PLCP(plcp, ppdu_type, field) << \
- HE_RADIOTAP_ ## field ## _SHIFT)
-
-#define HE_PACK_RTAP_GI_LTF_FROM_PLCP(plcp, ppdu_type, field, member) \
- ((he_plcp2ltf_gi[HE_EXTRACT_FROM_PLCP(plcp, ppdu_type, field)].member) << \
- HE_RADIOTAP_ ## field ## _SHIFT)
-
-#define HE_PACK_RTAP_FROM_VAL(val, field) \
- ((val) << HE_RADIOTAP_ ## field ## _SHIFT)
-
-#define HE_PACK_RTAP_FROM_PRXS(rxh, corerev, corerev_minor, field) \
- (HE_PACK_RTAP_FROM_VAL(D11PPDU_ ## field(rxh, corerev, corerev_minor), field))
-
-/* channel bandwidth */
-#define WLC_20_MHZ 20 /**< 20Mhz channel bandwidth */
-#define WLC_40_MHZ 40 /**< 40Mhz channel bandwidth */
-#define WLC_80_MHZ 80 /**< 80Mhz channel bandwidth */
-#define WLC_160_MHZ 160 /**< 160Mhz channel bandwidth */
-#define WLC_240_MHZ 240 /**< 240Mhz channel bandwidth */
-#define WLC_320_MHZ 320 /**< 320Mhz channel bandwidth */
-
-extern uint16 bcmwifi_monitor_create(monitor_info_t**);
-extern void bcmwifi_set_corerev_major(monitor_info_t* info, int8 corerev);
-extern void bcmwifi_set_corerev_minor(monitor_info_t* info, int8 corerev);
-extern void bcmwifi_monitor_delete(monitor_info_t* info);
-extern uint16 bcmwifi_monitor(monitor_info_t* info,
- monitor_pkt_info_t* pkt_info, void *pdata, uint16 len, void* pout,
- uint16* offset, uint16 pad_req, void *wrxh_in, void *wrxh_last);
-extern uint16 wl_rxsts_to_rtap(monitor_pkt_rxsts_t* pkt_rxsts, void *pdata,
- uint16 len, void* pout, uint16 pad_req);
-
-#endif /* _BCMWIFI_MONITOR_H_ */
+++ /dev/null
-/*
- * bcmwpa.h - interface definitions of shared WPA-related functions
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _BCMWPA_H_
-#define _BCMWPA_H_
-#ifdef BCM_EXTERNAL_APP
-typedef int osl_t;
-#endif
-#include <wpa.h>
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL) || \
- defined(MFP) || defined(BCMAUTH_PSK) || defined(WLFBT) || \
- defined(WL_OKC) || defined(GTKOE) || defined(WL_FILS)
-#include <eapol.h>
-#endif
-#include <802.11.h>
-#ifdef WLP2P
-#include <p2p.h>
-#endif
-#include <rc4.h>
-#include <bcmutils.h>
-#include <wlioctl.h>
-#include <sha2.h>
-#ifdef WL_OCV
-#include <bcm_ocv.h>
-#endif /* WL_OCV */
-
-/* Field sizes for WPA key hierarchy */
-#define WPA_TEMP_TX_KEY_LEN 8u
-#define WPA_TEMP_RX_KEY_LEN 8u
-
-#define PMK_LEN 32u
-#define TKIP_PTK_LEN 64u
-#define TKIP_TK_LEN 32u
-#define AES_PTK_LEN 48u
-#define AES_TK_LEN 16u
-#define AES_GCM_PTK_LEN 48u
-#define AES_GCM_TK_LEN 16u
-#define AES_GCM256_PTK_LEN 64u
-#define AES_GCM256_TK_LEN 32u
-
-/* limits for pre-shared key lengths */
-#define WPA_MIN_PSK_LEN 8u
-#define WPA_MAX_PSK_LEN 64u
-
-#define WPA_KEY_DATA_LEN_256 256u /* allocation size of 256 for temp data pointer. */
-#define WPA_KEY_DATA_LEN_128 128u /* allocation size of 128 for temp data pointer. */
-
-/* Minimum length of WPA2 GTK encapsulation in EAPOL */
-#define EAPOL_WPA2_GTK_ENCAP_MIN_LEN (EAPOL_WPA2_ENCAP_DATA_HDR_LEN - \
- TLV_HDR_LEN + EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN)
-
-/* Minimum length of WPA2 IGTK encapsulation in EAPOL */
-#define EAPOL_WPA2_IGTK_ENCAP_MIN_LEN (EAPOL_WPA2_ENCAP_DATA_HDR_LEN - \
- TLV_HDR_LEN + EAPOL_WPA2_KEY_IGTK_ENCAP_HDR_LEN)
-
-/* Minimum length of BIGTK encapsulation in EAPOL */
-#define EAPOL_WPA2_BIGTK_ENCAP_MIN_LEN (EAPOL_WPA2_ENCAP_DATA_HDR_LEN - \
- TLV_HDR_LEN + EAPOL_WPA2_KEY_BIGTK_ENCAP_HDR_LEN)
-
-#ifdef WL_OCV
-/* Size of the OCI element */
-#define WPA_OCV_OCI_IE_SIZE \
- (bcm_ocv_get_oci_len() + BCM_TLV_EXT_HDR_SIZE)
-
-/* Size of the OCI KDE */
-#define WPA_OCV_OCI_KDE_SIZE \
- (bcm_ocv_get_oci_len() + EAPOL_WPA2_ENCAP_DATA_HDR_LEN)
-
-/* Size of the OCI subelement */
-#define WPA_OCV_OCI_SUBELEM_SIZE \
- (bcm_ocv_get_oci_len() + TLV_HDR_LEN)
-
-/* Minimum length of WPA2 OCI encapsulation in EAPOL */
-#define EAPOL_WPA2_OCI_ENCAP_MIN_LEN \
- (WPA_OCV_OCI_KDE_SIZE - TLV_HDR_LEN)
-#endif /* WL_OCV */
-
-#ifdef WLFIPS
-#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
- ((bsscfg)->wsec & (WSEC_SWFLAG | FIPS_ENABLED))))
-#else
-#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
- ((bsscfg)->wsec & WSEC_SWFLAG)))
-#endif /* WLFIPS */
-
-/* This doesn't really belong here, but neither does WSEC_CKIP* */
-/* per-packet encryption exemption policy */
-/* no exemption...follow whatever standard rules apply */
-#define WSEC_EXEMPT_NO 0
-/* send unencrypted */
-#define WSEC_EXEMPT_ALWAYS 1
-/* send unencrypted if no pairwise key */
-#define WSEC_EXEMPT_NO_PAIRWISE 2
-
-#define WPA_CIPHER_UNSPECIFIED 0xff
-#define WPA_P_CIPHERS_UNSPECIFIED 0x80000000
-
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-#define WPA_AKMS_UNSPECIFIED 0x80000000
-#else
-#define WPA_AKMS_UNSPECIFIED 0
-#endif
-
-#ifdef BCMWAPI_WAI
-#define IS_WAPI_AUTH(auth) ((auth) == WAPI_AUTH_UNSPECIFIED || \
- (auth) == WAPI_AUTH_PSK)
-#define INCLUDES_WAPI_AUTH(auth) \
- ((auth) & (WAPI_AUTH_UNSPECIFIED | \
- WAPI_AUTH_PSK))
-#endif /* BCMWAPI_WAI */
-
-#define IS_WPA_AKM(akm) ((akm) == RSN_AKM_NONE || \
- (akm) == RSN_AKM_UNSPECIFIED || \
- (akm) == RSN_AKM_PSK)
-
-#define IS_WPA2_AKM(akm) ((akm) == RSN_AKM_UNSPECIFIED || \
- (akm) == RSN_AKM_PSK || \
- (akm) == RSN_AKM_FILS_SHA256 || \
- (akm) == RSN_AKM_FILS_SHA384)
-
-/* this doesn't mean much. A WPA (not RSN) akm type would match this */
-#define RSN_AKM_MASK (\
- BCM_BIT(RSN_AKM_UNSPECIFIED) | \
- BCM_BIT(RSN_AKM_PSK) | \
- BCM_BIT(RSN_AKM_SAE_PSK) | \
- BCM_BIT(RSN_AKM_FILS_SHA256) | \
- BCM_BIT(RSN_AKM_FILS_SHA384) | \
- BCM_BIT(RSN_AKM_OWE) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA384_1X))
-
-/* verify less than 32 before shifting bits */
-#define VALID_AKM_BIT(akm) ((akm) < 32u ? BCM_BIT((akm)) : 0u)
-
-#define IS_RSN_AKM(akm) (VALID_AKM_BIT((akm)) & RSN_AKM_MASK)
-
-#define FBT_AKM_MASK (BCM_BIT(RSN_AKM_FBT_1X) | \
- BCM_BIT(RSN_AKM_FBT_PSK) | \
- BCM_BIT(RSN_AKM_SAE_FBT) | \
- BCM_BIT(RSN_AKM_FBT_SHA256_FILS) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_FILS) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_PSK))
-
-#define IS_FBT_AKM(akm) (VALID_AKM_BIT((akm)) & FBT_AKM_MASK)
-
-#define FILS_AKM_MASK (\
- BCM_BIT(RSN_AKM_FILS_SHA256) | \
- BCM_BIT(RSN_AKM_FILS_SHA384))
-
-#define IS_FILS_AKM(akm) (VALID_AKM_BIT((akm)) & FILS_AKM_MASK)
-
-#define MFP_AKM_MASK (\
- BCM_BIT(RSN_AKM_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SHA256_PSK))
-
-#define IS_MFP_AKM(akm) (MFP_AKM_MASK & VALID_AKM_BIT((akm)))
-
-#ifdef BCMWAPI_WAI
-#define IS_WAPI_AKM(akm) ((akm) == RSN_AKM_NONE || \
- (akm) == RSN_AKM_UNSPECIFIED || \
- (akm) == RSN_AKM_PSK)
-#endif /* BCMWAPI_WAI */
-
-#define IS_TDLS_AKM(akm) ((akm) == RSN_AKM_TPK)
-
-/* Broadcom(OUI) authenticated key managment suite */
-#define BRCM_AKM_NONE 0
-#define BRCM_AKM_PSK 1u /* Proprietary PSK AKM */
-
-#define IS_BRCM_AKM(akm) ((akm) == BRCM_AKM_PSK)
-
-#define ONE_X_AKM_MASK (BCM_BIT(RSN_AKM_FBT_1X) | \
- BCM_BIT(RSN_AKM_MFP_1X) | \
- BCM_BIT(RSN_AKM_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_1X) | \
- BCM_BIT(RSN_AKM_UNSPECIFIED))
-
-#define IS_1X_AKM(akm) (VALID_AKM_BIT((akm)) & ONE_X_AKM_MASK)
-
-#define SUITEB_AKM_MASK (BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA384_1X))
-#define IS_1X_SUITEB_AKM(akm) (VALID_AKM_BIT((akm)) & SUITEB_AKM_MASK)
-
-#define SAE_AKM_MASK (BCM_BIT(RSN_AKM_SAE_PSK) | BCM_BIT(RSN_AKM_SAE_FBT))
-#define IS_SAE_AKM(akm) (VALID_AKM_BIT((akm)) & SAE_AKM_MASK)
-
-#define SHA256_AKM_MASK (BCM_BIT(RSN_AKM_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SHA256_PSK) | \
- BCM_BIT(RSN_AKM_SAE_PSK) | \
- BCM_BIT(RSN_AKM_SAE_FBT) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_FILS_SHA256) | \
- BCM_BIT(RSN_AKM_FBT_SHA256_FILS) | \
- BCM_BIT(RSN_AKM_OWE))
-#define IS_SHA256_AKM(akm) (VALID_AKM_BIT((akm)) & SHA256_AKM_MASK)
-
-#define SHA384_AKM_MASK (BCM_BIT(RSN_AKM_SUITEB_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FILS_SHA384) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_FILS) | \
- BCM_BIT(RSN_AKM_PSK_SHA384))
-#define IS_SHA384_AKM(akm) (VALID_AKM_BIT((akm)) & SHA384_AKM_MASK)
-
-#define OPEN_AUTH_AKM_MASK (\
- BCM_BIT(RSN_AKM_UNSPECIFIED) | \
- BCM_BIT(RSN_AKM_PSK) | \
- BCM_BIT(RSN_AKM_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SHA256_PSK) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA384_1X) | \
- BCM_BIT(RSN_AKM_PSK_SHA384))
-#define IS_OPEN_AUTH_AKM(akm) (VALID_AKM_BIT((akm)) & OPEN_AUTH_AKM_MASK)
-
-typedef enum akm_type {
- WPA_AUTH_IE = 0x01,
- RSN_AUTH_IE = 0x02,
- OSEN_AUTH_IE = 0x04
-} akm_type_t;
-
-#define MAX_ARRAY 1
-#define MIN_ARRAY 0
-
-#define WPS_ATID_SEL_REGISTRAR 0x1041
-
-/* move these to appropriate file(s) */
-#define WPS_IE_FIXED_LEN 6
-
-/* GTK indices we use - 0-3 valid per IEEE/802.11 2012 */
-#define GTK_INDEX_1 1
-#define GTK_INDEX_2 2
-
-/* IGTK indices we use - 4-5 are valid per IEEE 802.11 2012 */
-#define IGTK_INDEX_1 4
-#define IGTK_INDEX_2 5
-
-/* following needed for compatibility for router code because it automerges */
-#define IGTK_ID_TO_WSEC_INDEX(_id) (_id)
-#define WPA_AES_CMAC_CALC aes_cmac_calc
-
-#define IS_IGTK_INDEX(x) ((x) == IGTK_INDEX_1 || (x) == IGTK_INDEX_2)
-
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-typedef struct rsn_ie_info {
- uint8 version;
- int parse_status;
- device_type_t dev_type; /* AP or STA */
- auth_ie_type_mask_t auth_ie_type; /* bit field of WPA, WPA2 and (not yet) WAPI */
- rsn_cipher_t g_cipher;
- rsn_akm_t sta_akm; /* single STA akm */
- uint16 caps;
- rsn_ciphers_t rsn_p_ciphers;
- rsn_ciphers_t wpa_p_ciphers;
- rsn_akm_mask_t rsn_akms;
- rsn_akm_mask_t wpa_akms;
- uint8 pmkid_count;
- uint8 pmkids_offset; /* offset into the IE */
- rsn_cipher_t g_mgmt_cipher;
- rsn_cipher_t sta_cipher; /* single STA cipher */
- uint16 key_desc; /* key descriptor version as STA */
- uint16 mic_len; /* unused. keep for ROM compatibility. */
- uint8 pmk_len; /* EAPOL PMK */
- uint8 kck_mic_len; /* EAPOL MIC (by KCK) */
- uint8 kck_len; /* EAPOL KCK */
- uint8 kek_len; /* EAPOL KEK */
- uint8 tk_len; /* EAPOL TK */
- uint8 ptk_len; /* EAPOL PTK */
- uint8 kck2_len; /* EAPOL KCK2 */
- uint8 kek2_len; /* EAPOL KEK2 */
- uint8* rsn_ie; /* RSN IE from beacon or assoc request */
- uint16 rsn_ie_len; /* RSN IE length */
- uint8* wpa_ie; /* WPA IE */
- uint16 wpa_ie_len; /* WPA IE length (is it fixed ? */
- /* the following are helpers in the AP rsn info to be filled in by the STA
- * after determination of which IE is being used.in wsec_filter.
- */
- uint32 p_ciphers; /* current ciphers for the chosen auth IE */
- uint32 akms; /* current ciphers for the chosen auth IE */
- uint8 *auth_ie; /* pointer to current chosen auth IE */
- uint16 auth_ie_len;
- uint8 ref_count; /* external reference count to decide if structure must be freed */
- uint8 rsnxe_len; /* RSNXE IE length */
- uint8 PAD[3];
- uint8* rsnxe; /* RSNXE IE TLV buffer */
- uint32 rsnxe_cap; /* RSNXE IE cap flag, refer to 802.11.h */
-} rsn_ie_info_t;
-#endif /* RSN_IE_INFO_STRUCT_RELOCATED */
-
-/* WiFi WPS Attribute fixed portion */
-typedef struct wps_at_fixed {
- uint8 at[2];
- uint8 len[2];
- uint8 data[1];
-} wps_at_fixed_t;
-
-typedef const struct oui_akm_wpa_tbl {
- const char *oui; /* WPA auth category */
- uint16 rsn_akm;
- uint32 wpa_auth;
-} oui_akm_wpa_tbl_t;
-
-#define WPS_AT_FIXED_LEN 4
-
-#define wps_ie_fixed_t wpa_ie_fixed_t
-
-/* What should be the multicast mask for AES ? */
-#define WPA_UNICAST_AES_MASK (\
- BCM_BIT(WPA_CIPHER_AES_CCM) | \
- BCM_BIT(WPA_CIPHER_AES_GCM) | \
- BCM_BIT(WPA_CIPHER_AES_GCM256))
-
-#define WPA_CIPHER_WEP_MASK (\
- BCM_BIT(WPA_CIPHER_WEP_104) | \
- BCM_BIT(WPA_CIPHER_WEP_40))
-
-/* temporary to pass pre-commit */
-#ifdef TMP_USE_RSN_INFO
-/* wsec macros */
-#ifdef EXT_STA
-#define UCAST_NONE(rsn_info) (((rsn_info)->p_ciphers == (1 << WPA_CIPHER_NONE)) && \
- (!WLEXTSTA_ENAB(wlc->pub) || wlc->use_group_enabled))
-#else
-#define UCAST_NONE(rsn_info) (rsn_info->p_ciphers == (1 << WPA_CIPHER_NONE))
-#endif /* EXT_STA */
-
-#define UCAST_AES(rsn_info) (rsn_info->p_ciphers & WPA_UNICAST_AES_MASK)
-#define UCAST_TKIP(rsn_info) (rsn_info->p_ciphers & (1 << WPA_CIPHER_TKIP))
-#define UCAST_WEP(rsn_info) (rsn_info->p_ciphers & WPA_CIPHER_WEP_MASK)
-
-#define MCAST_NONE(rsn_info) ((rsn_info)->g_cipher == WPA_CIPHER_NONE)
-#define MCAST_AES(rsn_info) ((1 << rsn_info->g_cipher) & WPA_UNICAST_AES_MASK)
-#define MCAST_TKIP(rsn_info) (rsn_info->g_cipher == WPA_CIPHER_TKIP)
-#define MCAST_WEP(rsn_info) ((1 << rsn_info->g_cipher) & WPA_CIPHER_WEP_MASK)
-
-#endif /* TMP_USE_RSN_INFO */
-
-#define AKM_SHA256_MASK (\
- BCM_BIT(RSN_AKM_SHA256_1X) | \
- BCM_BIT(RSN_AKM_SHA256_PSK) | \
- BCM_BIT(RSN_AKM_SAE_PSK) | \
- BCM_BIT(RSN_AKM_OWE) | \
- BCM_BIT(RSN_AKM_SUITEB_SHA256_1X) | \
- BCM_BIT(RSN_AKM_FILS_SHA256) | \
- BCM_BIT(RSN_AKM_FBT_SHA256_FILS) | \
- BCM_BIT(RSN_AKM_SAE_FBT))
-
-#define AKM_SHA384_MASK (\
- BCM_BIT(RSN_AKM_SUITEB_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_1X) | \
- BCM_BIT(RSN_AKM_FILS_SHA384) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_FILS) | \
- BCM_BIT(RSN_AKM_FBT_SHA384_PSK) | \
- BCM_BIT(RSN_AKM_PSK_SHA384))
-
-/* these AKMs require MFP capable set in their IE */
-#define RSN_MFPC_AKM_MASK (\
- BCM_BIT(RSN_AKM_SAE_PSK) | \
- BCM_BIT(RSN_AKM_OWE) | \
- BCM_BIT(RSN_AKM_SAE_FBT))
-
-/* AKMs that supported by in-driver supplicant.
- * TODO: have to redesign this to include 1x and other PSK AKMs.
- */
-#define IS_BCMSUP_AKM(akm) \
- ((akm == RSN_AKM_PSK) | \
- (akm == RSN_AKM_SAE_PSK) | \
- (akm == RSN_AKM_OWE) | \
- (akm == RSN_AKM_FBT_PSK) | \
- (akm == RSN_AKM_SAE_FBT) | \
- (akm == RSN_AKM_FBT_SHA384_1X) | \
- (akm == RSN_AKM_FBT_SHA384_PSK))
-
-/* AKMs use common PSK which identified by broadcast addr */
-#define IS_SHARED_PMK_AKM(akm) \
- ((akm == RSN_AKM_PSK) | \
- (akm == RSN_AKM_FBT_PSK) | \
- (akm == RSN_AKM_SHA256_PSK) | \
- (akm == RSN_AKM_FBT_SHA384_PSK) | \
- (akm == RSN_AKM_PSK_SHA384))
-
-#define RSN_AKM_USE_KDF(akm) (akm >= RSN_AKM_FBT_1X ? 1u : 0)
-
-/* Macro to abstract access to the rsn_ie_info strucuture in case
- * we want to move it to a cubby or something else.
- * Gives the rsn_info pointer
- */
-
-#define RSN_INFO_GET(s) (s->rsn_info)
-/* where the rsn_info resides */
-#define RSN_INFO_GET_PTR(s) (&s->rsn_info)
-
-#define AUTH_AKM_INCLUDED(s) (s->rsn_info != NULL && s->rsn_info->parse_status == BCME_OK && \
- s->rsn_info->akms != WPA_AKMS_UNSPECIFIED)
-
-#define AKM_IS_MEMBER(akm, mask) ((mask) & VALID_AKM_BIT((akm)) || ((akm) == 0 && (mask) == 0))
-
-typedef enum eapol_key_type {
- EAPOL_KEY_NONE = 0,
- EAPOL_KEY_PMK = 1,
- EAPOL_KEY_KCK_MIC = 2,
- EAPOL_KEY_KEK = 3,
- EAPOL_KEY_TK = 4,
- EAPOL_KEY_PTK = 5,
- EAPOL_KEY_KCK = 6,
- EAPOL_KEY_KCK2 = 7,
- EAPOL_KEY_KEK2 = 8
-} eapol_key_type_t;
-
-/* Return address of max or min array depending first argument.
- * Return NULL in case of a draw.
- */
-extern const uint8 *wpa_array_cmp(int max_array, const uint8 *x, const uint8 *y, uint len);
-
-/* Increment the array argument */
-extern void wpa_incr_array(uint8 *array, uint len);
-
-/* Convert WPA IE cipher suite to locally used value */
-extern bool wpa_cipher(wpa_suite_t *suite, ushort *cipher, bool wep_ok);
-
-/* Look for a WPA IE; return it's address if found, NULL otherwise */
-extern wpa_ie_fixed_t *bcm_find_wpaie(uint8 *parse, uint len);
-extern bcm_tlv_t *bcm_find_wmeie(uint8 *parse, uint len, uint8 subtype, uint8 subtype_len);
-/* Look for a WPS IE; return it's address if found, NULL otherwise */
-extern wps_ie_fixed_t *bcm_find_wpsie(const uint8 *parse, uint len);
-extern wps_at_fixed_t *bcm_wps_find_at(wps_at_fixed_t *at, uint len, uint16 id);
-int bcm_find_security_ies(uint8 *buf, uint buflen, void **wpa_ie,
- void **rsn_ie);
-
-#ifdef WLP2P
-/* Look for a WiFi P2P IE; return it's address if found, NULL otherwise */
-extern wifi_p2p_ie_t *bcm_find_p2pie(const uint8 *parse, uint len);
-#endif
-/* Look for a hotspot2.0 IE; return it's address if found, NULL otherwise */
-bcm_tlv_t *bcm_find_hs20ie(uint8 *parse, uint len);
-/* Look for a OSEN IE; return it's address if found, NULL otherwise */
-bcm_tlv_t *bcm_find_osenie(uint8 *parse, uint len);
-
-/* Check whether the given IE has the specific OUI and the specific type. */
-extern bool bcm_has_ie(uint8 *ie, uint8 **tlvs, uint *tlvs_len,
- const uint8 *oui, uint oui_len, uint8 type);
-
-/* Check whether pointed-to IE looks like WPA. */
-#define bcm_is_wpa_ie(ie, tlvs, len) bcm_has_ie(ie, tlvs, len, \
- (const uint8 *)WPA_OUI, WPA_OUI_LEN, WPA_OUI_TYPE)
-/* Check whether pointed-to IE looks like WPS. */
-#define bcm_is_wps_ie(ie, tlvs, len) bcm_has_ie(ie, tlvs, len, \
- (const uint8 *)WPS_OUI, WPS_OUI_LEN, WPS_OUI_TYPE)
-#ifdef WLP2P
-/* Check whether the given IE looks like WFA P2P IE. */
-#define bcm_is_p2p_ie(ie, tlvs, len) bcm_has_ie(ie, tlvs, len, \
- (const uint8 *)P2P_OUI, P2P_OUI_LEN, P2P_OUI_TYPE)
-#endif
-
-/* Convert WPA2 IE cipher suite to locally used value */
-extern bool wpa2_cipher(wpa_suite_t *suite, ushort *cipher, bool wep_ok);
-
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL) || defined(GTKOE) || defined(WL_FILS)
-/* Look for an encapsulated GTK; return it's address if found, NULL otherwise */
-extern eapol_wpa2_encap_data_t *wpa_find_gtk_encap(uint8 *parse, uint len);
-
-/* Check whether pointed-to IE looks like an encapsulated GTK. */
-extern bool wpa_is_gtk_encap(uint8 *ie, uint8 **tlvs, uint *tlvs_len);
-
-/* Look for encapsulated key data; return it's address if found, NULL otherwise */
-extern eapol_wpa2_encap_data_t *wpa_find_kde(const uint8 *parse, uint len, uint8 type);
-
-/* Find kde data given eapol header. */
-extern int wpa_find_eapol_kde_data(eapol_header_t *eapol, uint8 eapol_mic_len,
- uint8 subtype, eapol_wpa2_encap_data_t **out_data);
-
-/* Look for kde data in key data. */
-extern int wpa_find_kde_data(const uint8 *kde_buf, uint16 buf_len,
- uint8 subtype, eapol_wpa2_encap_data_t **out_data);
-
-#ifdef WL_OCV
-/* Check if both local and remote are OCV capable */
-extern bool wpa_check_ocv_caps(uint16 local_caps, uint16 peer_caps);
-
-/* Write OCI KDE into the buffer */
-extern int wpa_add_oci_encap(chanspec_t chspec, uint8* buf, uint buf_len);
-
-/* Validate OCI KDE */
-extern int wpa_validate_oci_encap(chanspec_t chspec, const uint8* buf, uint buf_len);
-
-/* Write OCI IE into the buffer */
-extern int wpa_add_oci_ie(chanspec_t chspec, uint8* buf, uint buf_len);
-
-/* Validate OCI IE */
-extern int wpa_validate_oci_ie(chanspec_t chspec, const uint8* buf, uint buf_len);
-
-/* Write OCI subelement into the FTE buffer */
-extern int wpa_add_oci_ft_subelem(chanspec_t chspec, uint8* buf, uint buf_len);
-
-/* Validate OCI FTE subelement */
-extern int wpa_validate_oci_ft_subelem(chanspec_t chspec,
- const uint8* buf, uint buf_len);
-#endif /* WL_OCV */
-#endif /* defined(BCMSUP_PSK) || defined(BCMSUPPL) || defined(GTKOE) || defined(WL_FILS) */
-
-#if defined(BCMSUP_PSK) || defined(WLFBT) || defined(BCMAUTH_PSK)|| \
- defined(WL_OKC) || defined(GTKOE)
-/* Calculate a pair-wise transient key */
-extern int wpa_calc_ptk(rsn_akm_t akm, const struct ether_addr *auth_ea,
- const struct ether_addr *sta_ea, const uint8 *anonce, uint8 anonce_len,
- const uint8* snonce, uint8 snonce_len, const uint8 *pmk,
- uint pmk_len, uint8 *ptk, uint ptk_len);
-
-/* Compute Message Integrity Code (MIC) over EAPOL message */
-extern int wpa_make_mic(eapol_header_t *eapol, uint key_desc, uint8 *mic_key,
- rsn_ie_info_t *rsn_info, uchar *mic, uint mic_len);
-
-/* Check MIC of EAPOL message */
-extern bool wpa_check_mic(eapol_header_t *eapol,
- uint key_desc, uint8 *mic_key, rsn_ie_info_t *rsn_info);
-
-/* Calculate PMKID */
-extern void wpa_calc_pmkid(const struct ether_addr *auth_ea,
- const struct ether_addr *sta_ea, const uint8 *pmk, uint pmk_len, uint8 *pmkid);
-
-/* Encrypt key data for a WPA key message */
-extern bool wpa_encr_key_data(eapol_wpa_key_header_t *body, uint16 key_info,
- uint8 *ekey, uint8 *gtk, uint8 *data, uint8 *encrkey, rc4_ks_t *rc4key,
- const rsn_ie_info_t *rsn_info);
-
-typedef uint8 wpa_rc4_ivkbuf_t[EAPOL_WPA_KEY_IV_LEN + EAPOL_WPA_ENCR_KEY_MAX_LEN];
-/* Decrypt key data from a WPA key message */
-extern int wpa_decr_key_data(eapol_wpa_key_header_t *body, uint16 key_info,
- uint8 *ekey, wpa_rc4_ivkbuf_t ivk, rc4_ks_t *rc4key, const rsn_ie_info_t *rsn_info,
- uint16 *dec_len);
-#endif /* BCMSUP_PSK || WLFBT || BCMAUTH_PSK || defined(GTKOE) */
-
-#if defined(BCMSUP_PSK) || defined(WLFBT) || defined(BCMAUTH_PSK)|| \
- defined(WL_OKC) || defined(GTKOE) || defined(WLHOSTFBT)
-
-/* Calculate PMKR0 for FT association */
-extern void wpa_calc_pmkR0(sha2_hash_type_t hash_type, const uint8 *ssid, uint ssid_len,
- uint16 mdid, const uint8 *r0kh, uint r0kh_len, const struct ether_addr *sta_ea,
- const uint8 *pmk, uint pmk_len, uint8 *pmkr0, uint8 *pmkr0name);
-
-/* Calculate PMKR1 for FT association */
-extern void wpa_calc_pmkR1(sha2_hash_type_t hash_type, const struct ether_addr *r1kh,
- const struct ether_addr *sta_ea, const uint8 *pmk, uint pmk_len,
- const uint8 *pmkr0name, uint8 *pmkr1, uint8 *pmkr1name);
-
-/* Calculate PTK for FT association */
-extern void wpa_calc_ft_ptk(sha2_hash_type_t hash_type, const struct ether_addr *bssid,
- const struct ether_addr *sta_ea, const uint8 *anonce, const uint8* snonce,
- const uint8 *pmk, uint pmk_len, uint8 *ptk, uint ptk_len);
-
-extern void wpa_derive_pmkR1_name(sha2_hash_type_t hash_type, struct ether_addr *r1kh,
- struct ether_addr *sta_ea, uint8 *pmkr0name, uint8 *pmkr1name);
-
-#endif /* defined(BCMSUP_PSK) || defined(WLFBT) || defined(BCMAUTH_PSK) ||
- * defined(WL_OKC) || defined(WLTDLS) || defined(GTKOE) || defined(WLHOSTFBT)
- */
-
-#if defined(BCMSUP_PSK) || defined(BCMSUPPL)
-
-/* Translate RSNE group mgmt cipher to CRYPTO_ALGO_XXX */
-extern uint8 bcmwpa_find_group_mgmt_algo(rsn_cipher_t g_mgmt_cipher);
-
-#endif /* BCMSUP_PSK || BCMSUPPL */
-
-extern bool bcmwpa_akm2WPAauth(uint8 *akm, uint32 *auth, bool sta_iswpa);
-
-extern bool bcmwpa_cipher2wsec(uint8 *cipher, uint32 *wsec);
-
-#ifdef RSN_IE_INFO_STRUCT_RELOCATED
-extern uint32 bcmwpa_wpaciphers2wsec(uint32 unicast);
-extern int bcmwpa_decode_ie_type(const bcm_tlv_t *ie, rsn_ie_info_t *info,
- uint32 *remaining, uint8 *type);
-
-/* to be removed after merge to NEWT (changed into bcmwpa_rsn_ie_info_reset) */
-void rsn_ie_info_reset(rsn_ie_info_t *rsn_info, osl_t *osh);
-uint32 wlc_convert_rsn_to_wsec_bitmap(uint32 ap_cipher_mask);
-#else
-uint32 bcmwpa_wpaciphers2wsec(uint8 wpacipher);
-int bcmwpa_decode_ie_type(const bcm_tlv_t *ie, rsn_ie_info_t *info, uint32 *remaining);
-#endif /* RSN_IE_INFO_STRUCT_RELOCATED */
-
-extern int bcmwpa_parse_rsnie(const bcm_tlv_t *ie, rsn_ie_info_t *info, device_type_t dev_type);
-
-/* Calculate PMKID */
-extern void kdf_calc_pmkid(const struct ether_addr *auth_ea,
- const struct ether_addr *sta_ea, const uint8 *key, uint key_len, uint8 *pmkid,
- rsn_ie_info_t *rsn_info);
-
-extern void kdf_calc_ptk(const struct ether_addr *auth_ea, const struct ether_addr *sta_ea,
- const uint8 *anonce, const uint8 *snonce, const uint8 *pmk, uint pmk_len,
- uint8 *ptk, uint ptk_len);
-
-#ifdef WLTDLS
-/* Calculate TPK for TDLS association */
-extern void wpa_calc_tpk(const struct ether_addr *init_ea,
- const struct ether_addr *resp_ea, const struct ether_addr *bssid,
- const uint8 *anonce, const uint8* snonce, uint8 *tpk, uint tpk_len);
-#endif
-extern bool bcmwpa_is_wpa_auth(uint32 wpa_auth);
-extern bool bcmwpa_includes_wpa_auth(uint32 wpa_auth);
-extern bool bcmwpa_is_rsn_auth(uint32 wpa_auth);
-extern bool bcmwpa_includes_rsn_auth(uint32 wpa_auth);
-extern int bcmwpa_get_algo_key_len(uint8 algo, uint16 *key_len);
-
-/* macro to pass precommit on ndis builds */
-#define bcmwpa_is_wpa2_auth(wpa_auth) bcmwpa_is_rsn_auth(wpa_auth)
-extern uint8 bcmwpa_eapol_key_length(eapol_key_type_t key, rsn_akm_t akm, rsn_cipher_t cipher);
-
-/* rsn info allocation utilities. */
-void bcmwpa_rsn_ie_info_reset(rsn_ie_info_t *rsn_info, osl_t *osh);
-void bcmwpa_rsn_ie_info_rel_ref(rsn_ie_info_t **rsn_info, osl_t *osh);
-int bcmwpa_rsn_ie_info_add_ref(rsn_ie_info_t *rsn_info);
-int bcmwpa_rsn_akm_cipher_match(rsn_ie_info_t *rsn_info);
-int bcmwpa_rsnie_eapol_key_len(rsn_ie_info_t *info);
-#if defined(WL_BAND6G)
-/* Return TRUE if any of the akm in akms_bmp is invalid in 6Ghz */
-bool bcmwpa_is_invalid_6g_akm(const rsn_akm_mask_t akms_bmp);
-/* Return TRUE if any of the cipher in ciphers_bmp is invalid in 6Ghz */
-bool bcmwpa_is_invalid_6g_cipher(const rsn_ciphers_t ciphers_bmp);
-#endif /* WL_BAND6G */
-#endif /* _BCMWPA_H_ */
+++ /dev/null
-/*
- * Chip-specific hardware definitions for
- * Broadcom 802.11abg Networking Device Driver
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _D11_H
-#define _D11_H
-
-/*
- * Notes:
- * 1. pre40/pre rev40: corerev < 40
- * 2. pre80/pre rev80: 40 <= corerev < 80
- * 3. rev40/D11AC: 80 > corerev >= 40
- * 4. rev80: corerev >= 80
- */
-
-#include <typedefs.h>
-#include <hndsoc.h>
-#include <sbhnddma.h>
-#include <802.11.h>
-
-#if defined(BCMDONGLEHOST) || defined(WL_UNITTEST)
-typedef struct {
- uint32 pad;
-} shmdefs_t;
-#else /* defined(BCMDONGLEHOST)|| defined(WL_UNITTEST) */
-#include <d11shm.h>
-#ifdef USE_BCMCONF_H
-#include <bcmconf.h>
-#else
-#include <wlc_cfg.h>
-#endif
-#endif /* !defined(BCMDONGLEHOST)|| !defined(WL_UNITTEST) */
-
-#include <d11regs.h>
-
-/* This marks the start of a packed structure section. */
-#include <packed_section_start.h>
-
-/* cpp contortions to concatenate w/arg prescan */
-#ifndef PAD
-#define _PADLINE(line) pad ## line
-#define _XSTR(line) _PADLINE(line)
-#define PAD _XSTR(__LINE__)
-#endif
-
-#define D11AC_BCN_TMPL_LEN 640 /**< length of the BCN template area for 11AC */
-
-#define LPRS_TMPL_LEN 512 /**< length of the legacy PRS template area */
-
-/* RX FIFO numbers */
-#define RX_FIFO 0 /**< data and ctl frames */
-#define RX_FIFO1 1 /**< ctl frames */
-#define RX_FIFO2 2 /**< ctl frames */
-#define RX_FIFO_NUMBER 3
-
-/* TX FIFO numbers using WME Access Classes */
-#define TX_AC_BK_FIFO 0 /**< Access Category Background TX FIFO */
-#define TX_AC_BE_FIFO 1 /**< Access Category Best-Effort TX FIFO */
-#define TX_AC_VI_FIFO 2 /**< Access Class Video TX FIFO */
-#define TX_AC_VO_FIFO 3 /**< Access Class Voice TX FIFO */
-#define TX_BCMC_FIFO 4 /**< Broadcast/Multicast TX FIFO */
-#define TX_ATIM_FIFO 5 /**< TX fifo for ATIM window info */
-#define TX_AC_N_DATA_FIFO 4 /**< Number of legacy Data Fifos (BK, BE, VI, VO) */
-
-/* TX FIFO numbers for trigger queues for HE STA only chips (i.e
- * This is valid only for 4369 or similar STA chips that supports
- * a single HE STA connection.
- */
-#define TX_TRIG_BK_FIFO 6 /**< Access Category Background TX FIFO */
-#define TX_TRIG_BE_FIFO 7 /**< Access Category Best-Effort TX FIFO */
-#define TX_TRIG_VI_FIFO 8 /**< Access Class Video TX FIFO */
-#define TX_TRIG_VO_FIFO 9 /**< Access Class Voice TX FIFO */
-#define TX_TRIG_HP_FIFO 10 /**< Access High Priority TX FIFO */
-#define TX_TRIG_N_DATA_FIFO 4 /**< Number of Trigger Data Fifos (BK, BE, VI, VO) */
-
-#if defined(WL11AX_TRIGGERQ) && !defined(WL11AX_TRIGGERQ_DISABLED)
-#define IS_TRIG_FIFO(fifo) \
- (((fifo) >= TX_TRIG_BK_FIFO) && ((fifo) < (TX_TRIG_BK_FIFO + TX_TRIG_N_DATA_FIFO)))
-#else
-#define IS_TRIG_FIFO(fifo) FALSE
-#endif /* defined(WL11AX_TRIGGERQ) && !defined(WL11AX_TRIGGERQ_DISABLED) */
-
-#define IS_AC_FIFO(fifo) \
- ((fifo) < (TX_AC_BK_FIFO + TX_AC_N_DATA_FIFO))
-
-/** Legacy TX FIFO numbers */
-#define TX_DATA_FIFO TX_AC_BE_FIFO
-#define TX_CTL_FIFO TX_AC_VO_FIFO
-
-/** Trig TX FIFO numbers */
-#define TX_TRIG_DATA_FIFO TX_TRIG_BE_FIFO
-#define TX_TRIG_CTL_FIFO TX_TRIG_VO_FIFO
-
-/* Extended FIFOs for corerev >= 64 */
-#define TX_FIFO_6 6
-#define TX_FIFO_7 7
-#define TX_FIFO_16 16
-#define TX_FIFO_23 23
-#define TX_FIFO_25 25
-
-#define TX_FIFO_EXT_START TX_FIFO_6 /* Starting index of extendied HW TX FIFOs */
-#define TX_FIFO_MU_START 8 /* index at which MU TX FIFOs start */
-
-#define D11REG_IHR_WBASE 0x200
-#define D11REG_IHR_BASE (D11REG_IHR_WBASE << 1)
-
-#define PIHR_BASE 0x0400 /**< byte address of packed IHR region */
-
-/* biststatus */
-#define BT_DONE (1U << 31) /**< bist done */
-#define BT_B2S (1 << 30) /**< bist2 ram summary bit */
-
-/* DMA intstatus and intmask */
-#define I_PC (1 << 10) /**< pci descriptor error */
-#define I_PD (1 << 11) /**< pci data error */
-#define I_DE (1 << 12) /**< descriptor protocol error */
-#define I_RU (1 << 13) /**< receive descriptor underflow */
-#define I_RO (1 << 14) /**< receive fifo overflow */
-#define I_XU (1 << 15) /**< transmit fifo underflow */
-#define I_RI (1 << 16) /**< receive interrupt */
-#define I_XI (1 << 24) /**< transmit interrupt */
-
-/* interrupt receive lazy */
-#define IRL_TO_MASK 0x00ffffff /**< timeout */
-#define IRL_FC_MASK 0xff000000 /**< frame count */
-#define IRL_FC_SHIFT 24 /**< frame count */
-#define IRL_DISABLE 0x01000000 /**< Disabled value: int on 1 frame, zero time */
-
-/** for correv >= 80. prev rev uses bit 21 */
-#define MCTL_BCNS_PROMISC_SHIFT 21
-/** for correv < 80. prev rev uses bit 20 */
-#define MCTL_BCNS_PROMISC_SHIFT_LT80 20
-
-/* maccontrol register */
-#define MCTL_GMODE (1U << 31)
-#define MCTL_DISCARD_PMQ (1 << 30)
-#define MCTL_DISCARD_TXSTATUS (1 << 29)
-#define MCTL_TBTT_HOLD (1 << 28)
-#define MCTL_CLOSED_NETWORK (1 << 27)
-#define MCTL_WAKE (1 << 26)
-#define MCTL_HPS (1 << 25)
-#define MCTL_PROMISC (1 << 24)
-#define MCTL_KEEPBADFCS (1 << 23)
-#define MCTL_KEEPCONTROL (1 << 22)
-#define MCTL_BCNS_PROMISC (1 << MCTL_BCNS_PROMISC_SHIFT)
-#define MCTL_BCNS_PROMISC_LT80 (1 << MCTL_BCNS_PROMISC_SHIFT_LT80)
-#define MCTL_NO_TXDMA_LAST_PTR (1 << 20) /** for correv >= 85 */
-#define MCTL_LOCK_RADIO (1 << 19)
-#define MCTL_AP (1 << 18)
-#define MCTL_INFRA (1 << 17)
-#define MCTL_BIGEND (1 << 16)
-#define MCTL_DISABLE_CT (1 << 14) /** for corerev >= 83.1 */
-#define MCTL_GPOUT_SEL_MASK (3 << 14)
-#define MCTL_GPOUT_SEL_SHIFT 14
-#define MCTL_EN_PSMDBG (1 << 13)
-#define MCTL_IHR_EN (1 << 10)
-#define MCTL_SHM_UPPER (1 << 9)
-#define MCTL_SHM_EN (1 << 8)
-#define MCTL_PSM_JMP_0 (1 << 2)
-#define MCTL_PSM_RUN (1 << 1)
-#define MCTL_EN_MAC (1 << 0)
-
-/* maccontrol1 register */
-#define MCTL1_GCPS (1u << 0u)
-#define MCTL1_EGS_MASK 0x0000c000
-#define MCTL1_EGS_SHIFT 14u
-#define MCTL1_AVB_ENABLE (1u << 1u)
-#define MCTL1_GPIOSEL_SHIFT 8u
-#define MCTL1_GPIOSEL (0x3F)
-#define MCTL1_GPIOSEL_MASK (MCTL1_GPIOSEL << MCTL1_GPIOSEL_SHIFT)
-/* Select MAC_SMPL_CPTR debug data that is placed in pc<7:1> & ifs_gpio_out<8:0> GPIOs */
-#define MCTL1_GPIOSEL_TSF_PC_IFS(_corerev) (D11REV_GE(_corerev, 85) ? 0x3b : 0x36)
-#define MCTL1_AVB_TRIGGER (1u << 2u)
-#define MCTL1_THIRD_AXI1_FOR_PSM (1u << 3u)
-#define MCTL1_AXI1_FOR_RX (1u << 4u)
-#define MCTL1_TXDMA_ENABLE_PASS (1u << 5u)
-/* SampleCollectPlayCtrl */
-#define SC_PLAYCTRL_MASK_ENABLE (1u << 8u)
-#define SC_PLAYCTRL_TRANS_MODE (1u << 6u)
-#define SC_PLAYCTRL_SRC_SHIFT 3u
-#define SC_PLAYCTRL_SRC_MASK (3u << SC_PLAYCTRL_SRC_SHIFT)
-#define SC_PLAYCTRL_SRC_PHY_DBG (3u << SC_PLAYCTRL_SRC_SHIFT)
-#define SC_PLAYCTRL_SRC_GPIO_OUT (2u << SC_PLAYCTRL_SRC_SHIFT)
-#define SC_PLAYCTRL_SRC_GPIO_IN (1u << SC_PLAYCTRL_SRC_SHIFT)
-#define SC_PLAYCTRL_SRC_PHY_SMPL (0u << SC_PLAYCTRL_SRC_SHIFT)
-#define SC_PLAYCTRL_STOP (1u << 2u)
-#define SC_PLAYCTRL_PAUSE (1u << 1u)
-#define SC_PLAYCTRL_START (1u << 0u)
-/* SCPortalSel fields */
-#define SC_PORTAL_SEL_AUTO_INCR (1u << 15u) /* Autoincr */
-#define SC_PORTAL_SEL_STORE_MASK (0u << 5u) /* Bits 14:5 SCStoreMask15to0 */
-#define SC_PORTAL_SEL_MATCH_MASK (4u << 5u) /* Bits 14:5 SCMatchMask15to0 */
-#define SC_PORTAL_SEL_MATCH_VALUE (8u << 5u) /* Bits 14:5 SCMatchValue15to0 */
-#define SC_PORTAL_SEL_TRIGGER_MASK (12u << 0u) /* Bits 4:0 SCTriggerMask15to0 */
-#define SC_PORTAL_SEL_TRIGGER_VALUE (16u << 0u) /* Bits 4:0 SCTriggerValue15to0 */
-#define SC_PORTAL_SEL_TRANS_MASK (20u << 0u) /* Bits 4:0 SCTransMask15to0 */
-
-/* GpioOut register */
-#define MGPIO_OUT_RXQ1_IFIFO_CNT_MASK 0x1fc0u
-#define MGPIO_OUT_RXQ1_IFIFO_CNT_SHIFT 6u
-
-#define MAC_RXQ1_IFIFO_CNT_ADDR 0x26u
-#define MAC_RXQ1_IFIFO_MAXLEN 3u
-
-/* maccommand register */
-#define MCMD_BCN0VLD (1 << 0)
-#define MCMD_BCN1VLD (1 << 1)
-#define MCMD_DIRFRMQVAL (1 << 2)
-#define MCMD_CCA (1 << 3)
-#define MCMD_BG_NOISE (1 << 4)
-#define MCMD_SKIP_SHMINIT (1 << 5) /**< only used for simulation */
-#define MCMD_SLOWCAL (1 << 6)
-#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /**< reuse for sample collect */
-#define MCMD_IF_DOWN (1 << 8 ) /**< indicate interface is going down */
-#define MCMD_TOF (1 << 9) /**< wifi ranging processing in ucode for rxd frames */
-#define MCMD_TSYNC (1 << 10) /**< start timestamp sync process in ucode */
-#define MCMD_RADIO_DOWN (1 << 11) /**< radio down by ucode */
-#define MCMD_RADIO_UP (1 << 12) /**< radio up by ucode */
-#define MCMD_TXPU (1 << 13) /**< txpu control by ucode */
-
-/* macintstatus/macintmask */
-#define MI_MACSSPNDD (1 << 0) /**< MAC has gracefully suspended */
-#define MI_BCNTPL (1 << 1) /**< beacon template available */
-#define MI_TBTT (1 << 2) /**< TBTT indication */
-#define MI_BCNSUCCESS (1 << 3) /**< beacon successfully tx'd */
-#define MI_BCNCANCLD (1 << 4) /**< beacon canceled (IBSS) */
-#define MI_ATIMWINEND (1 << 5) /**< end of ATIM-window (IBSS) */
-#define MI_PMQ (1 << 6) /**< PMQ entries available */
-#define MI_ALTTFS (1 << 7) /**< TX status interrupt for ARM offloads */
-#define MI_NSPECGEN_1 (1 << 8) /**< non-specific gen-stat bits that are set by PSM */
-#define MI_MACTXERR (1 << 9) /**< MAC level Tx error */
-#define MI_PMQERR (1 << 10)
-#define MI_PHYTXERR (1 << 11) /**< PHY Tx error */
-#define MI_PME (1 << 12) /**< Power Management Event */
-#define MI_GP0 (1 << 13) /**< General-purpose timer0 */
-#define MI_GP1 (1 << 14) /**< General-purpose timer1 */
-#define MI_DMAINT (1 << 15) /**< (ORed) DMA-interrupts */
-#define MI_TXSTOP (1 << 16) /**< MAC has completed a TX FIFO Suspend/Flush */
-#define MI_CCA (1 << 17) /**< MAC has completed a CCA measurement */
-#define MI_BG_NOISE (1 << 18) /**< MAC has collected background noise samples */
-#define MI_DTIM_TBTT (1 << 19) /**< MBSS DTIM TBTT indication */
-#define MI_PRQ (1 << 20) /**< Probe response queue needs attention */
-#define MI_HEB (1 << 21) /**< HEB (Hardware Event Block) interrupt - 11ax cores */
-#define MI_BT_RFACT_STUCK (1 << 22) /**< MAC has detected invalid BT_RFACT pin,
- * valid when rev < 15
- */
-#define MI_TTTT (1 << 22) /**< Target TIM Transmission Time,
- * valid in rev = 26/29, or rev >= 42
- */
-#define MI_BT_PRED_REQ (1 << 23) /**< MAC requested driver BTCX predictor calc */
-#define MI_BCNTRIM_RX (1 << 24) /**< PSM received a partial beacon */
-#define MI_P2P (1 << 25) /**< WiFi P2P interrupt */
-#define MI_DMATX (1 << 26) /**< MAC new frame ready */
-#define MI_TSSI_LIMIT (1 << 27) /**< Tssi Limit Reach, TxIdx=0/127 Interrupt */
-#define MI_HWACI_NOTIFY (1 << 27) /**< HWACI detects ACI, Apply Mitigation settings */
-#define MI_RFDISABLE (1 << 28) /**< MAC detected a change on RF Disable input
- * (corerev >= 10)
- */
-#define MI_TFS (1 << 29) /**< MAC has completed a TX (corerev >= 5) */
-#define MI_LEGACY_BUS_ERROR (1 << 30) /**< uCode indicated bus error */
-#define MI_TO (1U << 31) /**< general purpose timeout (corerev >= 3) */
-
-#define MI_RXOV MI_NSPECGEN_1 /**< rxfifo overflow interrupt */
-
-/* macintstatus_ext/macintmask_ext */
-#define MI_BUS_ERROR (1U << 0u) /**< uCode indicated bus error */
-#define MI_VCOPLL (1U << 1u) /**< uCode indicated PLL lock issue */
-#define MI_EXT_PS_CHG (1U << 2u) /**< Power state is changing (PS 0 <-> 1) */
-#define MI_DIS_ULOFDMA (1U << 3u) /**< ucode indicated disabling ULOFDMA request */
-#define MI_EXT_PM_OFFLOAD (1U << 4u) /**< PM offload */
-#define MI_OBSS_INTR (1U << 5u) /**< OBSS detection interrupt */
-#define MI_SENSORC_CX_REQ (1U << 6u) /**< SensorC Mitigation Request interrupt */
-#define MI_RLL_NAV_HOF (1U << 7u) /**< RLLW Switch */
-
-#define MI_EXT_TXE_SHARED_ERR (1U << 28u) /* Error event in blocks inside TXE shared
- * (BMC/AQM/AQM-DMA/MIF)
- */
-
-/* Mac capabilities registers */
-#define MCAP_TKIPMIC 0x80000000 /**< TKIP MIC hardware present */
-#define MCAP_TKIPPH2KEY 0x40000000 /**< TKIP phase 2 key hardware present */
-#define MCAP_BTCX 0x20000000 /**< BT coexistence hardware and pins present */
-#define MCAP_MBSS 0x10000000 /**< Multi-BSS hardware present */
-#define MCAP_RXFSZ_MASK 0x0ff80000 /**< Rx fifo size in blocks (revid >= 16) */
-#define MCAP_RXFSZ_SHIFT 19
-#define MCAP_NRXQ_MASK 0x00070000 /**< Max Rx queues supported - 1 */
-#define MCAP_NRXQ_SHIFT 16
-#define MCAP_UCMSZ_MASK 0x0000e000 /**< Ucode memory size */
-#define MCAP_UCMSZ_3K3 0 /**< 3328 Words Ucode memory, in unit of 50-bit */
-#define MCAP_UCMSZ_4K 1 /**< 4096 Words Ucode memory */
-#define MCAP_UCMSZ_5K 2 /**< 5120 Words Ucode memory */
-#define MCAP_UCMSZ_6K 3 /**< 6144 Words Ucode memory */
-#define MCAP_UCMSZ_8K 4 /**< 8192 Words Ucode memory */
-#define MCAP_UCMSZ_SHIFT 13
-#define MCAP_TXFSZ_MASK 0x00000ff8 /**< Tx fifo size (* 512 bytes) */
-#define MCAP_TXFSZ_SHIFT 3
-#define MCAP_NTXQ_MASK 0x00000007 /**< Max Tx queues supported - 1 */
-#define MCAP_NTXQ_SHIFT 0
-
-#define MCAP_BTCX_SUP(corerev) (MCAP_BTCX)
-
-#define MCAP_UCMSZ_TYPES 8 /**< different Ucode memory size types */
-
-/* machwcap1 */
-#define MCAP1_ERC_MASK 0x00000001 /**< external radio coexistence */
-#define MCAP1_ERC_SHIFT 0
-#define MCAP1_SHMSZ_MASK 0x0000000e /**< shm size (corerev >= 16) */
-#define MCAP1_SHMSZ_SHIFT 1
-#define MCAP1_SHMSZ_1K 0 /**< 1024 words in unit of 32-bit */
-#define MCAP1_SHMSZ_2K 1 /**< 1536 words in unit of 32-bit */
-#define MCAP1_NUMMACCHAINS 0x00003000 /**< Indicates one less than the
- number of MAC Chains in the MAC.
- */
-#define MCAP1_NUMMACCHAINS_SHIFT 12
-#define MCAP1_RXBLMAX_MASK 0x1800000u
-#define MCAP1_RXBLMAX_SHIFT 23u
-#define MCAP1_NUM_HEB_MASK 0xE0000000u
-#define MCAP1_NUM_HEB_SHIFT 29u
-#define MCAP1_NUM_HEB_FACTOR 3u
-#define MCAP1_CT_CAPABLE_SHIFT 17
-
-/* BTCX control */
-#define BTCX_CTRL_EN 0x0001 /**< Enable BTCX module */
-#define BTCX_CTRL_SW 0x0002 /**< Enable software override */
-#define BTCX_CTRL_DSBLBTCXOUT 0x8000 /* Disable txconf/prisel signal output from btcx module */
-
-#define BTCX_CTRL_PRI_POL 0x0080 /* Invert prisel polarity */
-#define BTCX_CTRL_TXC_POL 0x0020 /* Invert txconf polarity */
-
-#define SW_PRI_ON 1 /* switch prisel polarity */
-#define SW_TXC_ON 2 /* switch txconf polarity */
-
-/* BTCX status */
-#define BTCX_STAT_RA 0x0001 /**< RF_ACTIVE state */
-
-/* BTCX transaction control */
-#define BTCX_TRANS_ANTSEL 0x0040 /**< ANTSEL output */
-#define BTCX_TRANS_TXCONF 0x0080 /**< TX_CONF output */
-
-/* pmqhost data */
-#define PMQH_DATA_MASK 0xffff0000 /**< data entry of head pmq entry */
-#define PMQH_BSSCFG 0x00100000 /**< PM entry for BSS config */
-#define PMQH_PMOFF 0x00010000 /**< PM Mode OFF: power save off */
-#define PMQH_PMON 0x00020000 /**< PM Mode ON: power save on */
-#define PMQH_PMPS 0x00200000 /**< PM Mode PRETEND */
-#define PMQH_DASAT 0x00040000 /**< Dis-associated or De-authenticated */
-#define PMQH_ATIMFAIL 0x00080000 /**< ATIM not acknowledged */
-#define PMQH_DEL_ENTRY 0x00000001 /**< delete head entry */
-#define PMQH_DEL_MULT 0x00000002 /**< delete head entry to cur read pointer -1 */
-#define PMQH_OFLO 0x00000004 /**< pmq overflow indication */
-#define PMQH_NOT_EMPTY 0x00000008 /**< entries are present in pmq */
-
-/* phydebug (corerev >= 3) */
-#define PDBG_CRS (1 << 0) /**< phy is asserting carrier sense */
-#define PDBG_TXA (1 << 1) /**< phy is taking xmit byte from mac this cycle */
-#define PDBG_TXF (1 << 2) /**< mac is instructing the phy to transmit a frame */
-#define PDBG_TXE (1 << 3) /**< phy is signaling a transmit Error to the mac */
-#define PDBG_RXF (1 << 4) /**< phy detected the end of a valid frame preamble */
-#define PDBG_RXS (1 << 5) /**< phy detected the end of a valid PLCP header */
-#define PDBG_RXFRG (1 << 6) /**< rx start not asserted */
-#define PDBG_RXV (1 << 7) /**< mac is taking receive byte from phy this cycle */
-#define PDBG_RFD (1 << 16) /**< RF portion of the radio is disabled */
-
-/* objaddr register */
-#define OBJADDR_UCM_SEL 0x00000000
-#define OBJADDR_SHM_SEL 0x00010000
-#define OBJADDR_SCR_SEL 0x00020000
-#define OBJADDR_IHR_SEL 0x00030000
-#define OBJADDR_RCMTA_SEL 0x00040000
-#define OBJADDR_AMT_SEL 0x00040000
-#define OBJADDR_SRCHM_SEL 0x00060000
-#define OBJADDR_KEYTBL_SEL 0x000c0000
-#define OBJADDR_HEB_SEL 0x00120000
-#define OBJADDR_TXDC_TBL_SEL 0x00140000
-#define OBJADDR_TXDC_RIB_SEL 0x00150000
-#define OBJADDR_FCBS_SEL 0x00160000
-#define OBJADDR_LIT_SEL 0x00170000
-#define OBJADDR_LIB_SEL 0x00180000
-#define OBJADDR_WINC 0x01000000
-#define OBJADDR_RINC 0x02000000
-#define OBJADDR_AUTO_INC 0x03000000
-/* SHM/SCR/IHR/SHMX/SCRX/IHRX allow 2 bytes read/write, else only 4 bytes */
-#define OBJADDR_2BYTES_ACCESS(sel) \
- (((sel & 0x70000) == OBJADDR_SHM_SEL) || \
- ((sel & 0x70000) == OBJADDR_SCR_SEL) || \
- ((sel & 0x70000) == OBJADDR_IHR_SEL))
-
-/* objdata register */
-#define OBJDATA_WR_COMPLT 0x00000001
-
-/* frmtxstatus */
-#define TXS_V (1 << 0) /**< valid bit */
-
-#define TXS_STATUS_MASK 0xffff
-/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
-#define TXS_COMPAT_MASK 0x3
-#define TXS_COMPAT_SHIFT 1
-#define TXS_FID_MASK 0xffff0000
-#define TXS_FID_SHIFT 16
-
-/* frmtxstatus2 */
-#define TXS_SEQ_MASK 0xffff
-#define TXS_PTX_MASK 0xff0000
-#define TXS_PTX_SHIFT 16
-#define TXS_MU_MASK 0x01000000
-#define TXS_MU_SHIFT 24
-
-/* clk_ctl_st, corerev >= 17 */
-#define CCS_ERSRC_REQ_D11PLL 0x00000100 /**< d11 core pll request */
-#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /**< PHY pll request */
-#define CCS_ERSRC_REQ_PTMPLL 0x00001000 /* PTM clock request */
-#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /**< d11 core pll available */
-#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /**< PHY pll available */
-#define CCS_ERSRC_AVAIL_PTMPLL 0x10000000 /**< PHY pll available */
-
-/* tsf_cfprep register */
-#define CFPREP_CBI_MASK 0xffffffc0
-#define CFPREP_CBI_SHIFT 6
-#define CFPREP_CFPP 0x00000001
-
-/* receive fifo control */
-#define RFC_FR (1 << 0) /**< frame ready */
-#define RFC_DR (1 << 1) /**< data ready */
-
-/* tx fifo sizes for corerev >= 9 */
-/* tx fifo sizes values are in terms of 256 byte blocks */
-#define TXFIFOCMD_RESET_MASK (1 << 15) /**< reset */
-#define TXFIFOCMD_FIFOSEL_SHIFT 8 /**< fifo */
-#define TXFIFOCMD_FIFOSEL_SET(val) ((val & 0x7) << TXFIFOCMD_FIFOSEL_SHIFT) /* fifo */
-#define TXFIFOCMD_FIFOSEL_GET(val) ((val >> TXFIFOCMD_FIFOSEL_SHIFT) & 0x7) /* fifo */
-#define TXFIFO_FIFOTOP_SHIFT 8 /**< fifo start */
-
-#define TXFIFO_FIFO_START(def, def1) ((def & 0xFF) | ((def1 & 0xFF) << 8))
-#define TXFIFO_FIFO_END(def, def1) (((def & 0xFF00) >> 8) | (def1 & 0xFF00))
-
-/* Must redefine to 65 for 16 MBSS */
-#ifdef WLLPRS
-#define TXFIFO_START_BLK16 (65+16) /**< Base address + 32 * 512 B/P + 8 * 512 11g P */
-#else /* WLLPRS */
-#define TXFIFO_START_BLK16 65 /**< Base address + 32 * 512 B/P */
-#endif /* WLLPRS */
-#define TXFIFO_START_BLK 6 /**< Base address + 6 * 256 B */
-#define TXFIFO_START_BLK_NIN 7 /**< Base address + 6 * 256 B */
-
-#define TXFIFO_AC_SIZE_PER_UNIT 512 /**< one unit corresponds to 512 bytes */
-
-#define MBSS16_TEMPLMEM_MINBLKS 65 /**< one unit corresponds to 256 bytes */
-
-/* phy versions, PhyVersion:Revision field */
-#define PV_AV_MASK 0xf000 /**< analog block version */
-#define PV_AV_SHIFT 12 /**< analog block version bitfield offset */
-#define PV_PT_MASK 0x0f00 /**< phy type */
-#define PV_PT_SHIFT 8 /**< phy type bitfield offset */
-#define PV_PV_MASK 0x00ff /**< phy version */
-#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
-
-/* phy types, PhyVersion:PhyType field */
-#ifndef USE_BCMCONF_H
-#define PHY_TYPE_A 0 /**< A-Phy value */
-#define PHY_TYPE_B 1 /**< B-Phy value */
-#define PHY_TYPE_G 2 /**< G-Phy value */
-#define PHY_TYPE_N 4 /**< N-Phy value */
-/* #define PHY_TYPE_LP 5 */ /**< LP-Phy value */
-/* #define PHY_TYPE_SSN 6 */ /**< SSLPN-Phy value */
-#define PHY_TYPE_HT 7 /**< 3x3 HTPhy value */
-#define PHY_TYPE_LCN 8 /**< LCN-Phy value */
-#define PHY_TYPE_LCNXN 9 /**< LCNXN-Phy value */
-#define PHY_TYPE_LCN40 10 /**< LCN40-Phy value */
-#define PHY_TYPE_AC 11 /**< AC-Phy value */
-#define PHY_TYPE_LCN20 12 /**< LCN20-Phy value */
-#define PHY_TYPE_HE 13 /**< HE-Phy value */
-#define PHY_TYPE_NULL 0xf /**< Invalid Phy value */
-#endif /* USE_BCMCONF_H */
-
-/* analog types, PhyVersion:AnalogType field */
-#define ANA_11G_018 1
-#define ANA_11G_018_ALL 2
-#define ANA_11G_018_ALLI 3
-#define ANA_11G_013 4
-#define ANA_11N_013 5
-#define ANA_11LP_013 6
-
-/** 802.11a PLCP header def */
-typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
-BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
- uint8 rlpt[3]; /**< rate, length, parity, tail */
- uint16 service;
- uint8 pad;
-} BWL_POST_PACKED_STRUCT;
-
-#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
-#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
-#define D11A_PHY_HDR_GLENGTH(phdr) (((*((uint32 *)((phdr)->rlpt))) >> 5) & 0x0fff)
-#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
-#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
-
-/** rate encoded per 802.11a-1999 sec 17.3.4.1 */
-#define D11A_PHY_HDR_SRATE(phdr, rate) \
- ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
-/** set reserved field to zero */
-#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
-/** length is number of octets in PSDU */
-#define D11A_PHY_HDR_SLENGTH(phdr, length) \
- (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \
- (((length) & 0x0fff) << 5))
-/** set the tail to all zeros */
-#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
-
-#define D11A_PHY_HDR_LEN_L 3 /**< low-rate part of PLCP header */
-#define D11A_PHY_HDR_LEN_R 2 /**< high-rate part of PLCP header */
-
-#define D11A_PHY_TX_DELAY (2) /**< 2.1 usec */
-
-#define D11A_PHY_HDR_TIME (4) /**< low-rate part of PLCP header */
-#define D11A_PHY_PRE_TIME (16)
-#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
-
-/** 802.11b PLCP header def */
-typedef struct cck_phy_hdr cck_phy_hdr_t;
-BWL_PRE_PACKED_STRUCT struct cck_phy_hdr {
- uint8 signal;
- uint8 service;
- uint16 length;
- uint16 crc;
-} BWL_POST_PACKED_STRUCT;
-
-#define D11B_PHY_HDR_LEN 6
-
-#define D11B_PHY_TX_DELAY (3) /**< 3.4 usec */
-
-#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
-#define D11B_PHY_LPRE_TIME (144)
-#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
-
-#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
-#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
-#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
-
-#define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
-#define D11B_PLCP_SIGNAL_LE (1 << 7)
-
-/* AMPDUXXX: move to ht header file once it is ready: Mimo PLCP */
-#define MIMO_PLCP_MCS_MASK 0x7f /**< mcs index */
-#define MIMO_PLCP_40MHZ 0x80 /**< 40 Hz frame */
-#define MIMO_PLCP_AMPDU 0x08 /**< ampdu */
-
-#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
-#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
-#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
- plcp[1] = len & 0xff; plcp[2] = ((len >> 8) & 0xff);
-
-#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
-#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
-#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
-
-/**
- * The dot11a PLCP header is 5 bytes. To simplify the software (so that we don't need eg different
- * tx DMA headers for 11a and 11b), the PLCP header has padding added in the ucode.
- */
-#define D11_PHY_HDR_LEN 6u
-
-/** For the AC phy PLCP is 12 bytes and not all bytes are used for all the modulations */
-#define D11AC_PHY_HDR_LEN 12
-#define D11AC_PHY_VHT_PLCP_OFFSET 0
-#define D11AC_PHY_HTMM_PLCP_OFFSET 0
-#define D11AC_PHY_HTGF_PLCP_OFFSET 3
-#define D11AC_PHY_OFDM_PLCP_OFFSET 3
-#define D11AC_PHY_CCK_PLCP_OFFSET 6
-#define D11AC_PHY_BEACON_PLCP_OFFSET 0
-
-#define D11_PHY_RXPLCP_LEN(rev) (D11_PHY_HDR_LEN)
-#define D11_PHY_RXPLCP_OFF(rev) (0)
-
-/** TX descriptor - pre40 */
-typedef struct d11txh_pre40 d11txh_pre40_t;
-BWL_PRE_PACKED_STRUCT struct d11txh_pre40 {
- uint16 MacTxControlLow; /* 0x0 */
- uint16 MacTxControlHigh; /* 0x1 */
- uint16 MacFrameControl; /* 0x2 */
- uint16 TxFesTimeNormal; /* 0x3 */
- uint16 PhyTxControlWord; /* 0x4 */
- uint16 PhyTxControlWord_1; /* 0x5 */
- uint16 PhyTxControlWord_1_Fbr; /* 0x6 */
- uint16 PhyTxControlWord_1_Rts; /* 0x7 */
- uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */
- uint16 MainRates; /* 0x9 */
- uint16 XtraFrameTypes; /* 0xa */
- uint8 IV[16]; /* 0x0b - 0x12 */
- uint8 TxFrameRA[6]; /* 0x13 - 0x15 */
- uint16 TxFesTimeFallback; /* 0x16 */
- uint8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
- uint16 RTSDurFallback; /* 0x1a */
- uint8 FragPLCPFallback[6]; /* 0x1b - 1d */
- uint16 FragDurFallback; /* 0x1e */
- uint16 MModeLen; /* 0x1f */
- uint16 MModeFbrLen; /* 0x20 */
- uint16 TstampLow; /* 0x21 */
- uint16 TstampHigh; /* 0x22 */
- uint16 ABI_MimoAntSel; /* 0x23 */
- uint16 PreloadSize; /* 0x24 */
- uint16 AmpduSeqCtl; /* 0x25 */
- uint16 TxFrameID; /* 0x26 */
- uint16 TxStatus; /* 0x27 */
- uint16 MaxNMpdus; /* 0x28 corerev >=16 */
- BWL_PRE_PACKED_STRUCT union {
- uint16 MaxAggDur; /* 0x29 corerev >=16 */
- uint16 MaxAggLen;
- } BWL_POST_PACKED_STRUCT u1;
- BWL_PRE_PACKED_STRUCT union {
- BWL_PRE_PACKED_STRUCT struct { /* 0x29 corerev >=16 */
- uint8 MaxRNum;
- uint8 MaxAggBytes; /* Max Agg Bytes in power of 2 */
- } BWL_POST_PACKED_STRUCT s1;
- uint16 MaxAggLen_FBR;
- } BWL_POST_PACKED_STRUCT u2;
- uint16 MinMBytes; /* 0x2b corerev >=16 */
- uint8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
- struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
- uint16 pad; /* 0x37 */
-} BWL_POST_PACKED_STRUCT;
-
-#define D11_TXH_LEN 112 /**< bytes */
-
-/* Frame Types */
-#define FT_LEGACY (-1)
-#define FT_CCK 0
-#define FT_OFDM 1
-#define FT_HT 2
-#define FT_VHT 3
-#define FT_HE 4
-#define FT_EHT 6
-
-/* HE PPDU type */
-#define HE_SU_PPDU 0
-#define HE_SU_RE_PPDU 1
-#define HE_MU_PPDU 2
-#define HE_TRIG_PPDU 3
-
-/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
-#define TXC_AMPDU_SHIFT 9 /**< shift for ampdu settings */
-#define TXC_AMPDU_NONE 0 /**< Regular MPDU, not an A-MPDU */
-#define TXC_AMPDU_FIRST 1 /**< first MPDU of an A-MPDU */
-#define TXC_AMPDU_MIDDLE 2 /**< intermediate MPDU of an A-MPDU */
-#define TXC_AMPDU_LAST 3 /**< last (or single) MPDU of an A-MPDU */
-
-/* MacTxControlLow */
-#define TXC_AMIC 0x8000
-#define TXC_USERIFS 0x4000
-#define TXC_LIFETIME 0x2000
-#define TXC_FRAMEBURST 0x1000
-#define TXC_SENDCTS 0x0800
-#define TXC_AMPDU_MASK 0x0600
-#define TXC_BW_40 0x0100
-#define TXC_FREQBAND_5G 0x0080
-#define TXC_DFCS 0x0040
-#define TXC_IGNOREPMQ 0x0020
-#define TXC_HWSEQ 0x0010
-#define TXC_STARTMSDU 0x0008
-#define TXC_SENDRTS 0x0004
-#define TXC_LONGFRAME 0x0002
-#define TXC_IMMEDACK 0x0001
-
-/* MacTxControlHigh */
-#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
-#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
-#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /**< Main fallback rate preamble type
- * 1 = SHORT for OFDM/GF for MIMO
- * 0 = LONG for CCK/MM for MIMO
- */
-/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
-#define TXC_AMPDU_FBR 0x1000 /**< use fallback rate for this AMPDU */
-#define TXC_SECKEY_MASK 0x0FF0
-#define TXC_SECKEY_SHIFT 4
-#define TXC_ALT_TXPWR 0x0008 /**< Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
-#define TXC_SECTYPE_MASK 0x0007
-#define TXC_SECTYPE_SHIFT 0
-
-/* Null delimiter for Fallback rate */
-#define AMPDU_FBR_NULL_DELIM 5 /**< Location of Null delimiter count for AMPDU */
-
-/* PhyTxControl for Mimophy */
-#define PHY_TXC_PWR_MASK 0xFC00
-#define PHY_TXC_PWR_SHIFT 10
-#define PHY_TXC_ANT_MASK 0x03C0 /**< bit 6, 7, 8, 9 */
-#define PHY_TXC_ANT_SHIFT 6
-#define PHY_TXC_ANT_0_1 0x00C0 /**< auto, last rx */
-#define PHY_TXC_LPPHY_ANT_LAST 0x0000
-#define PHY_TXC_ANT_3 0x0200 /**< virtual antenna 3 */
-#define PHY_TXC_ANT_2 0x0100 /**< virtual antenna 2 */
-#define PHY_TXC_ANT_1 0x0080 /**< virtual antenna 1 */
-#define PHY_TXC_ANT_0 0x0040 /**< virtual antenna 0 */
-
-#define PHY_TXC_SHORT_HDR 0x0010
-#define PHY_TXC_FT_MASK 0x0003
-
-#define PHY_TXC_FT_CCK 0x0000
-#define PHY_TXC_FT_OFDM 0x0001
-#define PHY_TXC_FT_HT 0x0002
-#define PHY_TXC_FT_VHT 0x0003
-#define PHY_TXC_FT_HE 0x0004
-#define PHY_TXC_FT_EHT 0x0006
-
-#define PHY_TXC_OLD_ANT_0 0x0000
-#define PHY_TXC_OLD_ANT_1 0x0100
-#define PHY_TXC_OLD_ANT_LAST 0x0300
-
-/** PhyTxControl_1 for Mimophy */
-#define PHY_TXC1_BW_MASK 0x0007
-#define PHY_TXC1_BW_10MHZ 0
-#define PHY_TXC1_BW_10MHZ_UP 1
-#define PHY_TXC1_BW_20MHZ 2
-#define PHY_TXC1_BW_20MHZ_UP 3
-#define PHY_TXC1_BW_40MHZ 4
-#define PHY_TXC1_BW_40MHZ_DUP 5
-#define PHY_TXC1_MODE_SHIFT 3
-#define PHY_TXC1_MODE_MASK 0x0038
-#define PHY_TXC1_MODE_SISO 0
-#define PHY_TXC1_MODE_CDD 1
-#define PHY_TXC1_MODE_STBC 2
-#define PHY_TXC1_MODE_SDM 3
-#define PHY_TXC1_CODE_RATE_SHIFT 8
-#define PHY_TXC1_CODE_RATE_MASK 0x0700
-#define PHY_TXC1_CODE_RATE_1_2 0
-#define PHY_TXC1_CODE_RATE_2_3 1
-#define PHY_TXC1_CODE_RATE_3_4 2
-#define PHY_TXC1_CODE_RATE_4_5 3
-#define PHY_TXC1_CODE_RATE_5_6 4
-#define PHY_TXC1_CODE_RATE_7_8 6
-#define PHY_TXC1_MOD_SCHEME_SHIFT 11
-#define PHY_TXC1_MOD_SCHEME_MASK 0x3800
-#define PHY_TXC1_MOD_SCHEME_BPSK 0
-#define PHY_TXC1_MOD_SCHEME_QPSK 1
-#define PHY_TXC1_MOD_SCHEME_QAM16 2
-#define PHY_TXC1_MOD_SCHEME_QAM64 3
-#define PHY_TXC1_MOD_SCHEME_QAM256 4
-
-/* PhyTxControl for HTphy that are different from Mimophy */
-#define PHY_TXC_HTANT_MASK 0x3fC0 /**< bit 6, 7, 8, 9, 10, 11, 12, 13 */
-#define PHY_TXC_HTCORE_MASK 0x03C0 /**< core enable core3:core0, 1=enable, 0=disable */
-#define PHY_TXC_HTCORE_SHIFT 6 /**< bit 6, 7, 8, 9 */
-#define PHY_TXC_HTANT_IDX_MASK 0x3C00 /**< 4-bit, 16 possible antenna configuration */
-#define PHY_TXC_HTANT_IDX_SHIFT 10
-#define PHY_TXC_HTANT_IDX0 0
-#define PHY_TXC_HTANT_IDX1 1
-#define PHY_TXC_HTANT_IDX2 2
-#define PHY_TXC_HTANT_IDX3 3
-
-/* PhyTxControl_1 for HTphy that are different from Mimophy */
-#define PHY_TXC1_HTSPARTIAL_MAP_MASK 0x7C00 /**< bit 14:10 */
-#define PHY_TXC1_HTSPARTIAL_MAP_SHIFT 10
-#define PHY_TXC1_HTTXPWR_OFFSET_MASK 0x01f8 /**< bit 8:3 */
-#define PHY_TXC1_HTTXPWR_OFFSET_SHIFT 3
-
-/* TxControl word follows new interface for AX */
-/* PhyTxControl_6 for AXphy */
-#define PHY_TXC5_AXTXPWR_OFFSET_C0_MASK 0xff00 /**< bit 15:8 */
-#define PHY_TXC5_AXTXPWR_OFFSET_C0_SHIFT 8
-#define PHY_TXC6_AXTXPWR_OFFSET_C1_MASK 0x00ff /**< bit 7:0 */
-#define PHY_TXC6_AXTXPWR_OFFSET_C1_SHIFT 0
-#define PHY_TXC5_AXTXPWR_OFFSET_C2_MASK 0x00ff /**< bit 7:0 */
-#define PHY_TXC5_AXTXPWR_OFFSET_C2_SHIFT 0
-
-/* XtraFrameTypes */
-#define XFTS_RTS_FT_SHIFT 2
-#define XFTS_FBRRTS_FT_SHIFT 4
-#define XFTS_CHANNEL_SHIFT 8
-
-/** Antenna diversity bit in ant_wr_settle */
-#define PHY_AWS_ANTDIV 0x2000
-
-/* IFS ctl */
-#define IFS_USEEDCF (1 << 2)
-
-/* IFS ctl1 */
-#define IFS_CTL1_EDCRS (1 << 3)
-#define IFS_CTL1_EDCRS_20L (1 << 4)
-#define IFS_CTL1_EDCRS_40 (1 << 5)
-#define IFS_EDCRS_MASK (IFS_CTL1_EDCRS | IFS_CTL1_EDCRS_20L | IFS_CTL1_EDCRS_40)
-#define IFS_EDCRS_SHIFT 3
-
-/* IFS ctl sel pricrs */
-#define IFS_CTL_CRS_SEL_20LL 1
-#define IFS_CTL_CRS_SEL_20LU 2
-#define IFS_CTL_CRS_SEL_20UL 4
-#define IFS_CTL_CRS_SEL_20UU 8
-#define IFS_CTL_CRS_SEL_MASK (IFS_CTL_CRS_SEL_20LL | IFS_CTL_CRS_SEL_20LU | \
- IFS_CTL_CRS_SEL_20UL | IFS_CTL_CRS_SEL_20UU)
-#define IFS_CTL_ED_SEL_20LL (1 << 8)
-#define IFS_CTL_ED_SEL_20LU (1 << 9)
-#define IFS_CTL_ED_SEL_20UL (1 << 10)
-#define IFS_CTL_ED_SEL_20UU (1 << 11)
-#define IFS_CTL_ED_SEL_MASK (IFS_CTL_ED_SEL_20LL | IFS_CTL_ED_SEL_20LU | \
- IFS_CTL_ED_SEL_20UL | IFS_CTL_ED_SEL_20UU)
-
-/* ABI_MimoAntSel */
-#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
-#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
-#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
-#define ABI_MAS_FBR_ANT_PTN_SHIFT 4
-#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
-
-#ifdef WLAWDL
-#define ABI_MAS_AWDL_TS_INSERT 0x1000 /**< bit 12 */
-#endif
-
-#define ABI_MAS_TIMBC_TSF 0x2000 /**< Enable TIMBC tsf field present */
-
-/* MinMBytes */
-#define MINMBYTES_PKT_LEN_MASK 0x0300
-#define MINMBYTES_FBRATE_PWROFFSET_MASK 0xFC00
-#define MINMBYTES_FBRATE_PWROFFSET_SHIFT 10
-
-/* Rev40 template constants */
-
-/** templates include a longer PLCP header that matches the MAC / PHY interface */
-#define D11_VHT_PLCP_LEN 12
-
-/* 11AC TX DMA buffer header */
-
-#define D11AC_TXH_NUM_RATES 4
-
-/** per rate info - rev40 */
-typedef struct d11actxh_rate d11actxh_rate_t;
-BWL_PRE_PACKED_STRUCT struct d11actxh_rate {
- uint16 PhyTxControlWord_0; /* 0 - 1 */
- uint16 PhyTxControlWord_1; /* 2 - 3 */
- uint16 PhyTxControlWord_2; /* 4 - 5 */
- uint8 plcp[D11_PHY_HDR_LEN]; /* 6 - 11 */
- uint16 FbwInfo; /* 12 -13, fall back bandwidth info */
- uint16 TxRate; /* 14 */
- uint16 RtsCtsControl; /* 16 */
- uint16 Bfm0; /* 18 */
-} BWL_POST_PACKED_STRUCT;
-
-/* Bit definition for FbwInfo field */
-#define FBW_BW_MASK 3
-#define FBW_BW_SHIFT 0
-#define FBW_TXBF 4
-#define FBW_TXBF_SHIFT 2
-/* this needs to be re-visited if we want to use this feature */
-#define FBW_BFM0_TXPWR_MASK 0x1F8
-#define FBW_BFM0_TXPWR_SHIFT 3
-#define FBW_BFM_TXPWR_MASK 0x7E00
-#define FBW_BFM_TXPWR_SHIFT 9
-
-/* Bit definition for Bfm0 field */
-#define BFM0_TXPWR_MASK 0x3f
-#define BFM0_STBC_SHIFT 6
-#define BFM0_STBC (1 << BFM0_STBC_SHIFT)
-/* should find a chance to converge the two */
-#define D11AC2_BFM0_TXPWR_MASK 0x7f
-#define D11AC2_BFM0_STBC_SHIFT 7
-#define D11AC2_BFM0_STBC (1 << D11AC2_BFM0_STBC_SHIFT)
-
-/* per packet info */
-typedef struct d11pktinfo_common d11pktinfo_common_t;
-typedef struct d11pktinfo_common d11actxh_pkt_t;
-BWL_PRE_PACKED_STRUCT struct d11pktinfo_common {
- /* Per pkt info */
- uint16 TSOInfo; /* 0 */
- uint16 MacTxControlLow; /* 2 */
- uint16 MacTxControlHigh; /* 4 */
- uint16 Chanspec; /* 6 */
- uint8 IVOffset; /* 8 */
- uint8 PktCacheLen; /* 9 */
- uint16 FrameLen; /* 10. In [bytes] units. */
- uint16 TxFrameID; /* 12 */
- uint16 Seq; /* 14 */
- uint16 Tstamp; /* 16 */
- uint16 TxStatus; /* 18 */
-} BWL_POST_PACKED_STRUCT;
-
-/* common cache info between rev40 and rev80 formats */
-typedef struct d11txh_cache_common d11txh_cache_common_t;
-BWL_PRE_PACKED_STRUCT struct d11txh_cache_common {
- uint8 BssIdEncAlg; /* 0 */
- uint8 KeyIdx; /* 1 */
- uint8 PrimeMpduMax; /* 2 */
- uint8 FallbackMpduMax; /* 3 */
- uint16 AmpduDur; /* 4 - 5 */
- uint8 BAWin; /* 6 */
- uint8 MaxAggLen; /* 7 */
-} BWL_POST_PACKED_STRUCT;
-
-/** Per cache info - rev40 */
-typedef struct d11actxh_cache d11actxh_cache_t;
-BWL_PRE_PACKED_STRUCT struct d11actxh_cache {
- d11txh_cache_common_t common; /* 0 - 7 */
- uint8 TkipPH1Key[10]; /* 8 - 17 */
- uint8 TSCPN[6]; /* 18 - 23 */
-} BWL_POST_PACKED_STRUCT;
-
-/** Long format tx descriptor - rev40 */
-typedef struct d11actxh d11actxh_t;
-BWL_PRE_PACKED_STRUCT struct d11actxh {
- /* Per pkt info */
- d11actxh_pkt_t PktInfo; /* 0 - 19 */
-
- union {
-
- /** Rev 40 to rev 63 layout */
- struct {
- /** Per rate info */
- d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 20 - 99 */
-
- /** Per cache info */
- d11actxh_cache_t CacheInfo; /* 100 - 123 */
- } rev40;
-
- /** Rev >= 64 layout */
- struct {
- /** Per cache info */
- d11actxh_cache_t CacheInfo; /* 20 - 43 */
-
- /** Per rate info */
- d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 44 - 123 */
- } rev64;
-
- };
-} BWL_POST_PACKED_STRUCT;
-
-#define D11AC_TXH_LEN sizeof(d11actxh_t) /* 124 bytes */
-
-/* Short format tx descriptor only has per packet info */
-#define D11AC_TXH_SHORT_LEN sizeof(d11actxh_pkt_t) /* 20 bytes */
-
-/* -TXDC-TxH Excluding Rate Info 41 bytes (Note 1 byte of RATEINFO is removed */
-#define D11AC_TXH_SHORT_EXT_LEN (sizeof(d11txh_rev80_t) - 1)
-
-/* Retry limit regs */
-/* Current retries for the fallback rates are hardcoded */
-#define D11AC_TXDC_SRL_FB (3u) /* Short Retry Limit - Fallback */
-#define D11AC_TXDC_LRL_FB (2u) /* Long Retry Limit - Fallback */
-
-#define D11AC_TXDC_RET_LIM_MASK (0x000Fu)
-#define D11AC_TXDC_SRL_SHIFT (0u) /* Short Retry Limit */
-#define D11AC_TXDC_SRL_FB_SHIFT (4u) /* Short Retry Limit - Fallback */
-#define D11AC_TXDC_LRL_SHIFT (8u) /* Long Retry Limit */
-#define D11AC_TXDC_LRL_FB_SHIFT (12u) /* Long Retry Limit - Fallback */
-
-/* MacTxControlLow */
-#define D11AC_TXC_HDR_FMT_SHORT 0x0001 /**< 0: long format, 1: short format */
-#define D11AC_TXC_UPD_CACHE 0x0002
-#define D11AC_TXC_CACHE_IDX_MASK 0x003C /**< Cache index 0 .. 15 */
-#define D11AC_TXC_CACHE_IDX_SHIFT 2
-
-#define D11AC_TXDC_IDX_SHIFT 1
-#define D11AC_TXDC_CPG_SHIFT 5
-#define D11REV80_TXDC_RIB_CPG 0x0020 /**< Cache Index CPG (Bit 5) -TXDC- */
-#define D11REV80_TXDC_RIB_DEL_MASK 0x001E /**< Cache index CIPX 0 .. 15 (Bit 1-4 -TXDC- */
-#define D11REV80_TXDC_RIB_IMM_MASK 0x003E /**< Cache index CIPX 0 .. 31 (Bit 1-5) -TXDC- */
-#define D11AC_TXC_AMPDU 0x0040 /**< Is aggregate-able */
-#define D11AC_TXC_IACK 0x0080 /**< Expect immediate ACK */
-#define D11AC_TXC_LFRM 0x0100 /**< Use long/short retry frame count/limit */
-#define D11AC_TXC_IPMQ 0x0200 /**< Ignore PMQ */
-#define D11AC_TXC_MBURST 0x0400 /**< Burst mode */
-#define D11AC_TXC_ASEQ 0x0800 /**< Add ucode generated seq num */
-#define D11AC_TXC_AGING 0x1000 /**< Use lifetime */
-#define D11AC_TXC_AMIC 0x2000 /**< Compute and add TKIP MIC */
-#define D11AC_TXC_STMSDU 0x4000 /**< First MSDU */
-#define D11AC_TXC_URIFS 0x8000 /**< Use RIFS */
-
-/* MacTxControlHigh */
-#define D11AC_TXC_DISFCS 0x0001 /**< Discard FCS */
-#define D11AC_TXC_FIX_RATE 0x0002 /**< Use primary rate only */
-#define D11AC_TXC_SVHT 0x0004 /**< Single VHT mpdu ampdu */
-#define D11AC_TXC_PPS 0x0008 /**< Enable PS Pretend feature */
-#define D11AC_TXC_UCODE_SEQ 0x0010 /* Sequence counter for BK traffic, for offloads */
-#define D11AC_TXC_TIMBC_TSF 0x0020 /**< Enable TIMBC tsf field present */
-#define D11AC_TXC_TCPACK 0x0040
-#define D11AC_TXC_AWDL_PHYTT 0x0080 /**< Fill in PHY Transmission Time for AWDL action frames */
-#define D11AC_TXC_TOF 0x0100 /**< Enable wifi ranging processing for rxd frames */
-#define D11AC_TXC_MU 0x0200 /**< MU Tx data */
-#define D11AC_TXC_BFIX 0x0800 /**< BFI from SHMx */
-#define D11AC_TXC_NORETRY 0x0800 /**< Disable retry for tsync frames */
-#define D11AC_TXC_UFP 0x1000 /**< UFP */
-#define D11AC_TXC_OVERRIDE_NAV 0x1000 /**< if set, ucode will tx without honoring NAV */
-#define D11AC_TXC_DYNBW 0x2000 /**< Dynamic BW */
-#define D11AC_TXC_TXPROF_EN 0x8000 /**< TxProfile Enable TODO: support multiple idx */
-#define D11AC_TXC_SLTF 0x8000 /**< 11az Secure Ranging frame */
-
-#define D11AC_TSTAMP_SHIFT 8 /**< Tstamp in 256us units */
-
-/* PhyTxControlWord_0 */
-#define D11AC_PHY_TXC_FT_MASK 0x0003
-
-/* vht txctl0 */
-#define D11AC_PHY_TXC_NON_SOUNDING 0x0004
-#define D11AC_PHY_TXC_BFM 0x0008
-#define D11AC_PHY_TXC_SHORT_PREAMBLE 0x0010
-#define D11AC2_PHY_TXC_STBC 0x0020
-#define D11AC_PHY_TXC_ANT_MASK 0x3FC0
-#define D11AC_PHY_TXC_CORE_MASK 0x03C0
-#define D11AC_PHY_TXC_CORE_SHIFT 6
-#define D11AC_PHY_TXC_ANT_IDX_MASK 0x3C00
-#define D11AC_PHY_TXC_ANT_IDX_SHIFT 10
-#define D11AC_PHY_TXC_BW_MASK 0xC000
-#define D11AC_PHY_TXC_BW_SHIFT 14
-#define D11AC_PHY_TXC_BW_20MHZ 0x0000
-#define D11AC_PHY_TXC_BW_40MHZ 0x4000
-#define D11AC_PHY_TXC_BW_80MHZ 0x8000
-#define D11AC_PHY_TXC_BW_160MHZ 0xC000
-
-/* PhyTxControlWord_1 */
-#define D11AC_PHY_TXC_PRIM_SUBBAND_MASK 0x0007
-#define D11AC_PHY_TXC_PRIM_SUBBAND_LLL 0x0000
-#define D11AC_PHY_TXC_PRIM_SUBBAND_LLU 0x0001
-#define D11AC_PHY_TXC_PRIM_SUBBAND_LUL 0x0002
-#define D11AC_PHY_TXC_PRIM_SUBBAND_LUU 0x0003
-#define D11AC_PHY_TXC_PRIM_SUBBAND_ULL 0x0004
-#define D11AC_PHY_TXC_PRIM_SUBBAND_ULU 0x0005
-#define D11AC_PHY_TXC_PRIM_SUBBAND_UUL 0x0006
-#define D11AC_PHY_TXC_PRIM_SUBBAND_UUU 0x0007
-#define D11AC_PHY_TXC_TXPWR_OFFSET_MASK 0x01F8
-#define D11AC_PHY_TXC_TXPWR_OFFSET_SHIFT 3
-#define D11AC2_PHY_TXC_TXPWR_OFFSET_MASK 0x03F8
-#define D11AC2_PHY_TXC_TXPWR_OFFSET_SHIFT 3
-#define D11AC_PHY_TXC_TXBF_USER_IDX_MASK 0x7C00
-#define D11AC_PHY_TXC_TXBF_USER_IDX_SHIFT 10
-#define D11AC2_PHY_TXC_DELTA_TXPWR_OFFSET_MASK 0x7C00
-#define D11AC2_PHY_TXC_DELTA_TXPWR_OFFSET_SHIFT 10
-/* Rather awkward bit mapping to keep pctl1 word same as legacy, for proprietary 11n rate support */
-#define D11AC_PHY_TXC_11N_PROP_MCS 0x8000 /* this represents bit mcs[6] */
-#define D11AC2_PHY_TXC_MU 0x8000
-
-/* PhyTxControlWord_2 phy rate */
-#define D11AC_PHY_TXC_PHY_RATE_MASK 0x003F
-#define D11AC2_PHY_TXC_PHY_RATE_MASK 0x007F
-
-/* 11b phy rate */
-#define D11AC_PHY_TXC_11B_PHY_RATE_MASK 0x0003
-#define D11AC_PHY_TXC_11B_PHY_RATE_1 0x0000
-#define D11AC_PHY_TXC_11B_PHY_RATE_2 0x0001
-#define D11AC_PHY_TXC_11B_PHY_RATE_5_5 0x0002
-#define D11AC_PHY_TXC_11B_PHY_RATE_11 0x0003
-
-/* 11a/g phy rate */
-#define D11AC_PHY_TXC_11AG_PHY_RATE_MASK 0x0007
-#define D11AC_PHY_TXC_11AG_PHY_RATE_6 0x0000
-#define D11AC_PHY_TXC_11AG_PHY_RATE_9 0x0001
-#define D11AC_PHY_TXC_11AG_PHY_RATE_12 0x0002
-#define D11AC_PHY_TXC_11AG_PHY_RATE_18 0x0003
-#define D11AC_PHY_TXC_11AG_PHY_RATE_24 0x0004
-#define D11AC_PHY_TXC_11AG_PHY_RATE_36 0x0005
-#define D11AC_PHY_TXC_11AG_PHY_RATE_48 0x0006
-#define D11AC_PHY_TXC_11AG_PHY_RATE_54 0x0007
-
-/* 11ac phy rate */
-#define D11AC_PHY_TXC_11AC_MCS_MASK 0x000F
-#define D11AC_PHY_TXC_11AC_NSS_MASK 0x0030
-#define D11AC_PHY_TXC_11AC_NSS_SHIFT 4
-
-/* 11n phy rate */
-#define D11AC_PHY_TXC_11N_MCS_MASK 0x003F
-#define D11AC2_PHY_TXC_11N_MCS_MASK 0x007F
-#define D11AC2_PHY_TXC_11N_PROP_MCS 0x0040 /* this represents bit mcs[6] */
-
-/* PhyTxControlWord_2 rest */
-#define D11AC_PHY_TXC_STBC 0x0040
-#define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_PRESENT 0x0080
-#define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_DYNAMIC 0x0100
-#define D11AC2_PHY_TXC_TXBF_USER_IDX_MASK 0xFE00
-#define D11AC2_PHY_TXC_TXBF_USER_IDX_SHIFT 9
-
-/* RtsCtsControl */
-#define D11AC_RTSCTS_FRM_TYPE_MASK 0x0001 /**< frame type */
-#define D11AC_RTSCTS_FRM_TYPE_11B 0x0000 /**< 11b */
-#define D11AC_RTSCTS_FRM_TYPE_11AG 0x0001 /**< 11a/g */
-#define D11AC_RTSCTS_USE_RTS 0x0004 /**< Use RTS */
-#define D11AC_RTSCTS_USE_CTS 0x0008 /**< Use CTS */
-#define D11AC_RTSCTS_SHORT_PREAMBLE 0x0010 /**< Long/short preamble: 0 - long, 1 - short? */
-#define D11AC_RTSCTS_LAST_RATE 0x0020 /**< this is last rate */
-#define D11AC_RTSCTS_IMBF 0x0040 /**< Implicit TxBF */
-#define D11AC_RTSCTS_MIMOPS_RTS 0x8000 /**< Use RTS for mimops */
-#define D11AC_RTSCTS_DPCU_VALID 0x0080 /**< DPCU Valid : Same bitfield as above */
-#define D11AC_RTSCTS_BF_IDX_MASK 0xF000 /**< 4-bit index to the beamforming block */
-#define D11AC_RTSCTS_BF_IDX_SHIFT 12
-#define D11AC_RTSCTS_RATE_MASK 0x0F00 /**< Rate table offset: bit 3-0 of PLCP byte 0 */
-#define D11AC_RTSCTS_USE_RATE_SHIFT 8
-
-/* BssIdEncAlg */
-#define D11AC_BSSID_MASK 0x000F /**< BSS index */
-#define D11AC_BSSID_SHIFT 0
-#define D11AC_ENCRYPT_ALG_MASK 0x00F0 /**< Encryption algoritm */
-#define D11AC_ENCRYPT_ALG_SHIFT 4
-#define D11AC_ENCRYPT_ALG_NOSEC 0x0000 /**< No security */
-#define D11AC_ENCRYPT_ALG_WEP 0x0010 /**< WEP */
-#define D11AC_ENCRYPT_ALG_TKIP 0x0020 /**< TKIP */
-#define D11AC_ENCRYPT_ALG_AES 0x0030 /**< AES */
-#define D11AC_ENCRYPT_ALG_WEP128 0x0040 /**< WEP128 */
-#define D11AC_ENCRYPT_ALG_NA 0x0050 /**< N/A */
-#define D11AC_ENCRYPT_ALG_WAPI 0x0060 /**< WAPI */
-
-/* AmpduDur */
-#define D11AC_AMPDU_MIN_DUR_IDX_MASK 0x000F /**< AMPDU minimum duration index */
-#define D11AC_AMPDU_MIN_DUR_IDX_SHIFT 0
-#define D11AC_AMPDU_MAX_DUR_MASK 0xFFF0 /**< AMPDU maximum duration in unit 16 usec */
-#define D11AC_AMPDU_MAX_DUR_SHIFT 4
-
-/**
- * TX Descriptor definitions for supporting rev80 (HE)
- */
-/* Maximum number of TX fallback rates per packet */
-#define D11_REV80_TXH_NUM_RATES 4
-#define D11_REV80_TXH_PHYTXCTL_MIN_LENGTH 1
-
-/** per rate info - fixed portion - rev80 */
-typedef struct d11txh_rev80_rate_fixed d11txh_rev80_rate_fixed_t;
-BWL_PRE_PACKED_STRUCT struct d11txh_rev80_rate_fixed {
- uint16 TxRate; /* rate in 500Kbps */
- uint16 RtsCtsControl; /* RTS - CTS control */
- uint8 plcp[D11_PHY_HDR_LEN]; /* 6 bytes */
-} BWL_POST_PACKED_STRUCT;
-
-/* rev80 specific per packet info fields */
-typedef struct d11pktinfo_rev80 d11pktinfo_rev80_t;
-BWL_PRE_PACKED_STRUCT struct d11pktinfo_rev80 {
- uint16 HEModeControl; /* 20 */
- uint16 length; /* 22 - length of txd in bytes */
-} BWL_POST_PACKED_STRUCT;
-
-#define D11_REV80_TXH_TX_MODE_SHIFT 0 /* Bits 2:0 of HeModeControl */
-#define D11_REV80_TXH_TX_MODE_MASK 0x3
-#define D11_REV80_TXH_HTC_OFFSET_SHIFT 4 /* Bits 8:4 of HeModeControl */
-#define D11_REV80_TXH_HTC_OFFSET_MASK 0x01F0u
-#define D11_REV80_TXH_TWT_EOSP 0x0200u /* bit 9 indicate TWT EOSP */
-#define D11_REV80_TXH_QSZ_QOS_CTL_IND_SHIFT 10 /* Bit 10 of HeModeControl */
-#define D11_REV80_TXH_QSZ_QOS_CTL_IND_MASK (1 << D11_REV80_TXH_QSZ_QOS_CTL_IND_SHIFT)
-#define D11_REV80_TXH_USE_BSSCOLOR_SHM_SHIFT 15 /* Bit 15 of HEModeControl */
-#define D11_REV80_TXH_USE_BSSCOLOR_SHM_MASK (1 << D11_REV80_TXH_USE_BSSCOLOR_SHM_SHIFT)
-
-/* Calculate Length for short format TXD */
-#define D11_TXH_SHORT_LEN(__corerev__) (D11REV_GE(__corerev__, 80) ? \
- D11_REV80_TXH_SHORT_LEN : \
- D11AC_TXH_SHORT_LEN)
-
-/* Calculate Length for short format TXD (TXDC and/or FMF) */
-#define D11_TXH_SHORT_EX_LEN(__corerev__) (D11REV_GE(__corerev__, 80) ? \
- D11_REV80_TXH_SHORT_EX_LEN : \
- D11AC_TXH_SHORT_LEN)
-
-#define D11_REV80_TXH_IS_HE_AMPDU_SHIFT 11 /* Bit 11 of HeModeControl */
-#define D11_REV80_TXH_IS_HE_AMPDU_MASK (1 << D11_REV80_TXH_IS_HE_AMPDU_SHIFT)
-
-#define D11_REV80_PHY_TXC_EDCA 0x00
-#define D11_REV80_PHY_TXC_OFDMA_RA 0x01 /* Use Random Access Trigger for Tx */
-#define D11_REV80_PHY_TXC_OFDMA_DT 0x02 /* Use Directed Trigger for Tx */
-#define D11_REV80_PHY_TXC_OFDMA_ET 0x03 /* Use earliest Trigger Opportunity */
-
-/** Per cache info - rev80 */
-typedef struct d11txh_rev80_cache d11txh_rev80_cache_t;
-BWL_PRE_PACKED_STRUCT struct d11txh_rev80_cache {
- d11txh_cache_common_t common; /* 0 - 7 */
- uint16 ampdu_mpdu_all; /* 8 - 9 */
- uint16 aggid; /* 10 - 11 */
- uint8 tkipph1_index; /* 12 */
- uint8 pktext; /* 13 */
- uint16 hebid_map; /* 14 -15: HEB ID bitmap */
-} BWL_POST_PACKED_STRUCT;
-
-/** Fixed size portion of TX descriptor - rev80 */
-typedef struct d11txh_rev80 d11txh_rev80_t;
-BWL_PRE_PACKED_STRUCT struct d11txh_rev80 {
- /**
- * Per pkt info fields (common + rev80 specific)
- *
- * Note : Ensure that PktInfo field is always the first member
- * of the d11txh_rev80 struct (that is at OFFSET - 0)
- */
- d11pktinfo_common_t PktInfo; /* 0 - 19 */
- d11pktinfo_rev80_t PktInfoExt; /* 20 - 23 */
-
- /** Per cache info */
- d11txh_rev80_cache_t CacheInfo; /* 24 - 39 */
-
- /**
- * D11_REV80_TXH_NUM_RATES number of Rate Info blocks
- * contribute to the variable size portion of the TXD.
- * Each Rate Info element (block) is a funtion of
- * (N_PwrOffset, N_RU, N_User).
- */
- uint8 RateInfoBlock[1];
-} BWL_POST_PACKED_STRUCT;
-
-/* Size of fixed portion in TX descriptor (without CacheInfo(Link info) and RateInfoBlock)
- * this portion never change regardless of TXDC/FMF support.
- */
-/* OFFSETOF() is available in bcmutils.h but including it will cause
- * recursive inclusion of d11.h specifically on NDIS platforms.
- */
-#ifdef BCMFUZZ
- /* use 0x10 offset to avoid undefined behavior error due to NULL access */
-#define D11_REV80_TXH_FIXED_LEN (((uint)(uintptr)&((d11txh_rev80_t *)0x10)->CacheInfo) - 0x10)
-#else
-#define D11_REV80_TXH_FIXED_LEN ((uint)(uintptr)&((d11txh_rev80_t *)0)->CacheInfo)
-#endif /* BCMFUZZ */
-
-/* Short format tx descriptor only has per packet info (24 bytes) */
-#define D11_REV80_TXH_SHORT_LEN (sizeof(d11pktinfo_common_t) + sizeof(d11pktinfo_rev80_t))
-
-/* Size of CacheInfo(Link info) in TX descriptor */
-#define D11_REV80_TXH_LINK_INFO_LEN (sizeof(d11txh_rev80_cache_t))
-
-/* Size of Short format TX descriptor
- * with TXDC - Short TXD(40 bytes) shall include PktInfo and Cache info without Rate info
- * with TXDC+FMF - Short TXD(24 bytes) shall include PktInfo only without Link info and Rate info
- * do NOT use D11_REV80_TXH_SHORT_EX_LEN to calculate long TXD length, value depends on FMF feature
- */
-#if defined(FMF_LIT) && !defined(FMF_LIT_DISABLED)
-#define D11_REV80_TXH_SHORT_EX_LEN D11_REV80_TXH_FIXED_LEN
-#else
-#define D11_REV80_TXH_SHORT_EX_LEN (D11_REV80_TXH_FIXED_LEN + D11_REV80_TXH_LINK_INFO_LEN)
-#endif /* FMF_LIT && !FMF_LIT_DISABLED */
-
-/* Length of BFM0 field in RateInfo Blk */
-#define D11_REV80_TXH_BFM0_FIXED_LEN(pwr_offs) 2u
-
-/**
- * Length of FBWInfo field in RateInfo Blk
- *
- * Note : for now return fixed length of 1 word
- */
-#define D11_REV80_TXH_FBWINFO_FIXED_LEN(pwr_offs) 2
-
-#define D11_REV80_TXH_FIXED_RATEINFO_LEN sizeof(d11txh_rev80_rate_fixed_t)
-
-/**
- * Macros to find size of N-RUs field in the PhyTxCtlWord.
- */
-#define D11_REV80_TXH_TXC_N_RUs_FIELD_SIZE 1
-#define D11_REV80_TXH_TXC_PER_RU_INFO_SIZE 4
-#define D11_REV80_TXH_TXC_PER_RU_MIN_SIZE 2
-
-#define D11_REV80_TXH_TXC_RU_FIELD_SIZE(n_rus) ((n_rus == 1) ? \
- (D11_REV80_TXH_TXC_PER_RU_MIN_SIZE) : \
- ((D11_REV80_TXH_TXC_N_RUs_FIELD_SIZE) + \
- ((n_rus) * D11_REV80_TXH_TXC_PER_RU_INFO_SIZE)))
-
-/**
- * Macros to find size of N-Users field in the TXCTL_EXT
- */
-#define D11_REV80_TXH_TXC_EXT_N_USERs_FIELD_SIZE 1
-#define D11_REV80_TXH_TXC_EXT_PER_USER_INFO_SIZE 4
-
-#define D11_REV80_TXH_TXC_N_USERs_FIELD_SIZE(n_users) \
- ((n_users) ? \
- (((n_users) * \
- (D11_REV80_TXH_TXC_EXT_PER_USER_INFO_SIZE)) + \
- (D11_REV80_TXH_TXC_EXT_N_USERs_FIELD_SIZE)) : \
- (n_users))
-
-/**
- * Size of each Tx Power Offset field in PhyTxCtlWord.
- */
-#define D11_REV80_TXH_TXC_PWR_OFFSET_SIZE 1u
-
-/**
- * Size of fixed / static fields in PhyTxCtlWord (all fields except N-RUs, N-Users and Pwr offsets)
- */
-#define D11_REV80_TXH_TXC_CONST_FIELDS_SIZE 6u
-
-/**
- * Macros used for filling PhyTxCtlWord
- */
-
-/* PhyTxCtl Byte 0 */
-#define D11_REV80_PHY_TXC_FT_MASK 0x0007u
-#define D11_REV80_PHY_TXC_HE_FMT_MASK 0x0018u
-#define D11_REV80_PHY_TXC_SOFT_AP_MODE 0x0020u
-#define D11_REV80_PHY_TXC_NON_SOUNDING 0x0040u
-#define D11_REV80_PHY_TXC_SHORT_PREAMBLE 0x0080u
-#define D11_REV80_PHY_TXC_FRAME_TYPE_VHT 0X0003u
-#define D11_REV80_PHY_TXC_FRAME_TYPE_HT 0X0002u
-#define D11_REV80_PHY_TXC_FRAME_TYPE_LEG 0X0001u
-
-#define D11_REV80_PHY_TXC_HE_FMT_SHIFT 3u
-
-/* PhyTxCtl Byte 1 */
-#define D11_REV80_PHY_TXC_STBC 0x0080u
-
-/* PhyTxCtl Word 1 (Bytes 2 - 3) */
-#define D11_REV80_PHY_TXC_DPCU_SUBBAND_SHIFT 5u
-#define D11_REV80_PHY_TXC_DYNBW_PRESENT 0x2000u
-#define D11_REV80_PHY_TXC_DYNBW_MODE 0x4000u
-#define D11_REV80_PHY_TXC_MU 0x8000u
-#define D11_REV80_PHY_TXC_BW_MASK 0x0003u
-#define D11_REV80_PHY_TXC_BW_20MHZ 0x0000u
-#define D11_REV80_PHY_TXC_BW_40MHZ 0x0001u
-#define D11_REV80_PHY_TXC_BW_80MHZ 0x0002u
-#define D11_REV80_PHY_TXC_BW_160MHZ 0x0003u
-/* PhyTxCtl Word 2 (Bytes 4 -5) */
-/* Though the width antennacfg, coremask fields are 8-bits,
- * only 4 bits is valid for 4369a0, hence masking only 4 bits
- */
-#define D11_REV80_PHY_TXC_ANT_CONFIG_MASK 0x00F0u
-#define D11_REV80_PHY_TXC_CORE_MASK 0x000Fu
-#define D11_REV80_PHY_TXC_ANT_CONFIG_SHIFT 4u
-/* upper byte- Ant. cfg, lower byte - Core */
-#define D11_REV80_PHY_TXC_ANT_CORE_MASK 0x0F0Fu
-
-/* PhyTxCtl BFM field */
-#define D11_REV80_PHY_TXC_BFM 0x80u
-
-/* PhyTxCtl power offsets */
-#define D11_REV80_PHY_TXC_PWROFS0_BYTE_POS 6u
-
-/* Phytx Ctl Sub band location */
-#define D11_REV80_PHY_TXC_SB_SHIFT 2u
-#define D11_REV80_PHY_TXC_SB_MASK 0x001Cu
-
-/* 11n phy rate */
-#define D11_REV80_PHY_TXC_11N_MCS_MASK 0x003Fu
-#define D11_REV80_PHY_TXC_11N_PROP_MCS 0x0040u /* this represents bit mcs[6] */
-
-/* 11ac phy rate */
-#define D11_REV80_PHY_TXC_11AC_NSS_SHIFT 4u
-
-/* PhyTxCtl Word0 */
-#define D11_REV80_PHY_TXC_MCS_NSS_MASK 0x7F00u
-#define D11_REV80_PHY_TXC_MCS_MASK 0xF00u
-#define D11_REV80_PHY_TXC_MCS_NSS_SHIFT 8u
-
-/* 11ax phy rate */
-#define D11_REV80_PHY_TXC_11AX_NSS_SHIFT 4u
-
-#define D11_PHY_TXC_FT_MASK(corerev) ((D11REV_GE(corerev, 80)) ? D11_REV80_PHY_TXC_FT_MASK : \
- D11AC_PHY_TXC_FT_MASK)
-
-/* PhyTxCtl Word 4 */
-#define D11_REV80_PHY_TXC_HEHL_ENABLE 0x2000u
-
-/* PhyTxCtl Word 5 */
-#define D11_REV80_PHY_TXC_CORE0_PWR_OFFSET_SHIFT 8u
-#define D11_REV80_PHY_TXC_CORE0_PWR_OFFSET_MASK 0xFF00u
-/* PhyTxCtl Word 6 */
-#define D11_REV80_PHY_TXC_CORE1_PWR_OFFSET_MASK 0x00FFu
-/* Number of RU assigned */
-#define D11_REV80_PHY_TXC_NRU 0x0100u
-
-/* A wrapper structure for all versions of TxD/d11txh structures */
-typedef union d11txhdr {
- d11txh_pre40_t pre40;
- d11actxh_t rev40;
- d11txh_rev80_t rev80;
-} d11txhdr_t;
-
-/**
- * Generic tx status packet for software use. This is independent of hardware
- * structure for a particular core. Hardware structure should be read and converted
- * to this structure before being sent for the sofware consumption.
- */
-typedef struct tx_status tx_status_t;
-typedef struct tx_status_macinfo tx_status_macinfo_t;
-
-BWL_PRE_PACKED_STRUCT struct tx_status_macinfo {
- int8 pad0;
- int8 is_intermediate;
- int8 pm_indicated;
- int8 pad1;
- uint8 suppr_ind;
- int8 was_acked;
- uint16 rts_tx_cnt;
- uint16 frag_tx_cnt;
- uint16 cts_rx_cnt;
- uint16 raw_bits;
- uint32 s3;
- uint32 s4;
- uint32 s5;
- uint32 s8;
- uint32 s9;
- uint32 s10;
- uint32 s11;
- uint32 s12;
- uint32 s13;
- uint32 s14;
- /* 128BA support */
- uint16 ncons_ext;
- uint16 s15;
- uint32 ack_map[8];
- /* pktlat */
- uint16 pkt_fetch_ts; /* PSM Packet Fetch Time */
- uint16 med_acc_dly; /* Medium Access Delay */
- uint16 rx_dur; /* Rx duration */
- uint16 mac_susp_dur; /* Mac Suspend Duration */
- uint16 txstatus_ts; /* TxStatus Time */
- uint16 tx_en_cnt; /* Number of times Tx was enabled */
- uint16 oac_txs_cnt; /* Other AC TxStatus count */
- uint16 data_retx_cnt; /* DataRetry count */
- uint16 pktlat_rsvd; /* reserved */
-} BWL_POST_PACKED_STRUCT;
-
-BWL_PRE_PACKED_STRUCT struct tx_status {
- uint16 framelen;
- uint16 frameid;
- uint16 sequence;
- uint16 phyerr;
- uint32 lasttxtime;
- uint16 ackphyrxsh;
- uint16 procflags; /* tx status processing flags */
- uint32 dequeuetime;
- tx_status_macinfo_t status;
-} BWL_POST_PACKED_STRUCT;
-
-/* Bits in struct tx_status procflags */
-#define TXS_PROCFLAG_AMPDU_BA_PKG2_READ_REQD 0x1 /* AMPDU BA txs pkg2 read required */
-
-/* status field bit definitions */
-#define TX_STATUS_FRM_RTX_MASK 0xF000
-#define TX_STATUS_FRM_RTX_SHIFT 12
-#define TX_STATUS_RTS_RTX_MASK 0x0F00
-#define TX_STATUS_RTS_RTX_SHIFT 8
-#define TX_STATUS_MASK 0x00FE
-#define TX_STATUS_PMINDCTD (1 << 7) /**< PM mode indicated to AP */
-#define TX_STATUS_INTERMEDIATE (1 << 6) /**< intermediate or 1st ampdu pkg */
-#define TX_STATUS_AMPDU (1 << 5) /**< AMPDU status */
-#define TX_STATUS_SUPR_MASK 0x1C /**< suppress status bits (4:2) */
-#define TX_STATUS_SUPR_SHIFT 2
-#define TX_STATUS_ACK_RCV (1 << 1) /**< ACK received */
-#define TX_STATUS_VALID (1 << 0) /**< Tx status valid (corerev >= 5) */
-#define TX_STATUS_NO_ACK 0
-#define TX_STATUS_BE (TX_STATUS_ACK_RCV | TX_STATUS_PMINDCTD)
-
-/* TX_STATUS for fw initiated pktfree event */
-#define TX_STATUS_SW_Q_FLUSH 0x10000
-
-/* status field bit definitions phy rev > 40 */
-#define TX_STATUS40_FIRST 0x0002
-#define TX_STATUS40_INTERMEDIATE 0x0004
-#define TX_STATUS40_PMINDCTD 0x0008
-
-#define TX_STATUS40_SUPR 0x00f0
-#define TX_STATUS40_SUPR_SHIFT 4
-
-#define TX_STATUS40_NCONS 0x7f00
-
-#define TX_STATUS40_NCONS_SHIFT 8
-
-#define TX_STATUS40_ACK_RCV 0x8000
-
-/* tx status bytes 8-16 */
-#define TX_STATUS40_TXCNT_RATE0_MASK 0x000000ff
-#define TX_STATUS40_TXCNT_RATE0_SHIFT 0
-
-#define TX_STATUS40_TXCNT_RATE1_MASK 0x00ff0000
-#define TX_STATUS40_TXCNT_RATE1_SHIFT 16
-
-#define TX_STATUS40_MEDIUM_DELAY_MASK 0xFFFF
-
-#define TX_STATUS40_TXCNT(s3, s4) \
- (((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \
- ((s3 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT) + \
- ((s4 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \
- ((s4 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT))
-
-#define TX_STATUS40_TXCNT_RT0(s3) \
- ((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT)
-
-#define TX_STATUS_EXTBA_TXCNT_BITS 0x3u
-#define TX_STATUS_EXTBA_TXSUCCNT_BITS 0x1u
-#define TX_STATUS_EXTBA_TXSIZE_RT 0x4u
-
-#define TX_STATUS_EXTBA_TXCNT_RATE_MASK 0x7u
-#define TX_STATUS_EXTBA_TXSUCCNT_RATE_MASK 0x8u
-
-#define TX_STATUS_EXTBA_TXCNT_RATE_SHIFT 0x8u
-#define TX_STATUS_EXTBA_TXSUCCNT_RATE_SHIFT 0x8u
-
-#define TX_STATUS_EXTBA_TXCNT_RT(s15, rt) \
- ((((s15) & (TX_STATUS_EXTBA_TXCNT_RATE_MASK << ((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) >> \
- ((rt) * TX_STATUS_EXTBA_TXSIZE_RT)) << TX_STATUS_EXTBA_TXCNT_RATE_SHIFT)
-
-#define TX_STATUS_EXTBA_TXSUCCNT_RT(s15, rt) \
- ((((s15) & (TX_STATUS_EXTBA_TXSUCCNT_RATE_MASK << ((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) >> \
- (((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) << TX_STATUS_EXTBA_TXSUCCNT_RATE_SHIFT)
-
-#define TX_STATUS40_TX_MEDIUM_DELAY(txs) ((txs)->status.s8 & TX_STATUS40_MEDIUM_DELAY_MASK)
-
-/* chip rev 40 pkg 2 fields */
-#define TX_STATUS40_IMPBF_MASK 0x0000000Cu /* implicit bf applied */
-#define TX_STATUS40_IMPBF_BAD_MASK 0x00000010u /* impl bf applied but ack frm has no bfm */
-#define TX_STATUS40_IMPBF_LOW_MASK 0x00000020u /* ack received with low rssi */
-#define TX_STATUS40_BFTX 0x00000040u /* Beamformed pkt TXed */
-/* pkt two status field bit definitions mac rev > 64 */
-#define TX_STATUS64_MUTX 0x00000080u /* Not used in STA-dongle chips */
-
-/* pkt two status field bit definitions mac rev > 80 */
-
-/* TXS rate cookie contains
- * mac rev 81/82 : RIT idx in bit[4:0] of RIB CtrlStat[0]
- * mac rev >= 83 : RIB version in bit[4:0] of RIB CtrlStat[1]
- */
-#define TX_STATUS80_RATE_COOKIE_MASK 0x00003E00u
-#define TX_STATUS80_RATE_COOKIE_SHIFT 9u
-#define TX_STATUS80_NAV_HDR 0x00004000u /* NAV Overriden */
-
-#define TX_STATUS80_TBPPDU_MASK 0x00000040u /* Indicates TBPPDU TX */
-#define TX_STATUS80_TBPPDU_SHIFT 6u
-#define TX_STATUS40_RTS_RTX_MASK 0x00ff0000u
-#define TX_STATUS40_RTS_RTX_SHIFT 16u
-#define TX_STATUS40_CTS_RRX_MASK 0xff000000u
-#define TX_STATUS40_CTS_RRX_SHIFT 24u
-
-/*
- * Intermediate status for TBPPDU (for stats purposes)
- * First uint16 word (word0 - status): VALID, !FIRST, INTERMEDIATE
- * Remaining word0 bits (3 - 15) are unasisgned
- */
-#define TX_ITBSTATUS(status) \
- (((status) & (TX_STATUS40_FIRST | TX_STATUS40_INTERMEDIATE)) == TX_STATUS40_INTERMEDIATE)
-/* Remainder of first uint32 (words 0 and 1) */
-#define TX_ITBSTATUS_LSIG_MASK 0x0000fff0u
-#define TX_ITBSTATUS_LSIG_SHIFT 4u
-#define TX_ITBSTATUS_TXPOWER_MASK 0xffff0000u
-#define TX_ITBSTATUS_TXPOWER_SHIFT 16u
-/* Second uint32 (words 2 and 3) */
-#define TX_ITBSTATUS_NULL_DELIMS_MASK 0x0007ffffu /* 19 bits * 4B => ~2M bytes */
-#define TX_ITBSTATUS_NULL_DELIMS_SHIFT 0u
-#define TX_ITBSTATUS_ACKED_MPDUS_MASK 0x3ff80000u /* 11 bits: 0-2047 */
-#define TX_ITBSTATUS_ACKED_MPDUS_SHIFT 19u
-/* Third uint32 (words 4 and 5) */
-#define TX_ITBSTATUS_SENT_MPDUS_MASK 0x0000ffe0u /* 11 bits: 0-2047 */
-#define TX_ITBSTATUS_SENT_MPDUS_SHIFT 5u
-#define TX_ITBSTATUS_APTXPWR_MASK 0x003f0000u /* 0-60 => -20 - 40 */
-#define TX_ITBSTATUS_APTXPWR_SHIFT 16u
-#define TX_ITBSTATUS_ULPKTEXT_MASK 0x01c00000u
-#define TX_ITBSTATUS_ULPKTEXT_SHIFT 22u
-#define TX_ITBSTATUS_MORETF_MASK 0x02000000u
-#define TX_ITBSTATUS_MORETF_SHIFT 25u
-#define TX_ITBSTATUS_CSREQ_MASK 0x04000000u
-#define TX_ITBSTATUS_CSREQ_SHIFT 26u
-#define TX_ITBSTATUS_ULBW_MASK 0x18000000u
-#define TX_ITBSTATUS_ULBW_SHIFT 27u
-#define TX_ITBSTATUS_GI_LTF_MASK 0x60000000u
-#define TX_ITBSTATUS_GI_LTF_SHIFT 29u
-#define TX_ITBSTATUS_MUMIMO_LTF_MASK 0x80000000u
-#define TX_ITBSTATUS_MUMIMO_LTF_SHIFT 30u
-/* Fourth uint32 (words 6 and 7) */
-#define TX_ITBSTATUS_CODING_TYPE_MASK 0x00000001u
-#define TX_ITBSTATUS_CODING_TYPE_SHIFT 0u
-#define TX_ITBSTATUS_MCS_MASK 0x0000001eu
-#define TX_ITBSTATUS_MCS_SHIFT 1u
-#define TX_ITBSTATUS_DCM_MASK 0x00000020u
-#define TX_ITBSTATUS_DCM_SHIFT 5u
-#define TX_ITBSTATUS_RU_ALLOC_MASK 0x00003fc0u
-#define TX_ITBSTATUS_RU_ALLOC_SHIFT 6u
-/* Bits 14 and 15 unassigned */
-#define TX_ITBSTATUS_NSS_MASK 0x00030000u
-#define TX_ITBSTATUS_NSS_SHIFT 16u
-#define TX_ITBSTATUS_TARGET_RSSI_MASK 0x03fc0000u
-#define TX_ITBSTATUS_TARGET_RSSI_SHIFT 18u
-#define TX_ITBSTATUS_RA_RU_MASK 0x04000000u
-#define TX_ITBSTATUS_RA_RU_SHIFT 26u
-/* Bits 27 through 31 unassigned */
-/* End of intermediate TBPPDU txstatus definitions */
-
-/* MU group info txstatus field (s3 b[31:16]) */
-#define TX_STATUS64_MU_GID_MASK 0x003f0000u
-#define TX_STATUS64_MU_GID_SHIFT 16u
-#define TX_STATUS64_MU_BW_MASK 0x00c00000u
-#define TX_STATUS64_MU_BW_SHIFT 22u
-#define TX_STATUS64_MU_TXPWR_MASK 0x7f000000u
-#define TX_STATUS64_MU_TXPWR_SHIFT 24u
-#define TX_STATUS64_MU_SGI_MASK 0x80000080u
-#define TX_STATUS64_MU_SGI_SHIFT 31u
-#define TX_STATUS64_INTERM_MUTXCNT(s3) \
- ((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT)
-
-#define TX_STATUS64_MU_GID(s3) ((s3 & TX_STATUS64_MU_GID_MASK) >> TX_STATUS64_MU_GID_SHIFT)
-#define TX_STATUS64_MU_BW(s3) ((s3 & TX_STATUS64_MU_BW_MASK) >> TX_STATUS64_MU_BW_SHIFT)
-#define TX_STATUS64_MU_TXPWR(s3) ((s3 & TX_STATUS64_MU_TXPWR_MASK) >> TX_STATUS64_MU_TXPWR_SHIFT)
-#define TX_STATUS64_MU_SGI(s3) ((s3 & TX_STATUS64_MU_SGI_MASK) >> TX_STATUS64_MU_SGI_SHIFT)
-
-/* MU user info0 txstatus field (s4 b[15:0]) */
-#define TX_STATUS64_MU_MCS_MASK 0x0000000f
-#define TX_STATUS64_MU_MCS_SHIFT 0
-#define TX_STATUS64_MU_NSS_MASK 0x00000070
-#define TX_STATUS64_MU_NSS_SHIFT 4
-#define TX_STATUS64_MU_SNR_MASK 0x0000ff00
-#define TX_STATUS64_MU_SNR_SHIFT 8
-
-#define TX_STATUS64_MU_MCS(s4) ((s4 & TX_STATUS64_MU_MCS_MASK) >> TX_STATUS64_MU_MCS_SHIFT)
-#define TX_STATUS64_MU_NSS(s4) ((s4 & TX_STATUS64_MU_NSS_MASK) >> TX_STATUS64_MU_NSS_SHIFT)
-#define TX_STATUS64_MU_SNR(s4) ((s4 & TX_STATUS64_MU_SNR_MASK) >> TX_STATUS64_MU_SNR_SHIFT)
-
-/* MU txstatus rspec field (NSS | MCS) */
-#define TX_STATUS64_MU_RSPEC_MASK (TX_STATUS64_MU_NSS_MASK | TX_STATUS64_MU_MCS_MASK)
-#define TX_STATUS64_MU_RSPEC_SHIFT 0
-
-#define TX_STATUS64_MU_RSPEC(s4) ((s4 & TX_STATUS64_MU_RSPEC_MASK) >> TX_STATUS64_MU_RSPEC_SHIFT)
-
-/* MU user info0 txstatus field (s4 b[31:16]) */
-#define TX_STATUS64_MU_GBMP_MASK 0x000f0000
-#define TX_STATUS64_MU_GBMP_SHIFT 16
-#define TX_STATUS64_MU_GPOS_MASK 0x00300000
-#define TX_STATUS64_MU_GPOS_SHIFT 20
-#define TX_STATUS64_MU_TXCNT_MASK 0x0fc00000
-#define TX_STATUS64_MU_TXCNT_SHIFT 22
-
-#define TX_STATUS64_MU_GBMP(s4) ((s4 & TX_STATUS64_MU_GBMP_MASK) >> TX_STATUS64_MU_GBMP_SHIFT)
-#define TX_STATUS64_MU_GPOS(s4) ((s4 & TX_STATUS64_MU_GPOS_MASK) >> TX_STATUS64_MU_GPOS_SHIFT)
-#define TX_STATUS64_MU_TXCNT(s4) ((s4 & TX_STATUS64_MU_TXCNT_MASK) >> TX_STATUS64_MU_TXCNT_SHIFT)
-
-#define HE_MU_APTX_PWR_MAX 60u
-#define HE_TXS_MU_APTX_PWR_DBM(aptx_pwr) ((aptx_pwr) - 20u)
-
-#define HE_TXS_MU_TARGET_RSSI_RANG 90
-#define HE_TXS_MU_TARGET_RSSI_MAX_PWR 127
-#define HE_TXS_MU_TARGET_RSSI_DBM(rssi) ((rssi) - 110)
-
-#define HE_TXS_W4_MU_GET_RU_INDEX(index) ((index <= HE_MAX_26_TONE_RU_INDX) ? 0u : \
- ((index) <= HE_MAX_52_TONE_RU_INDX) ? 1u : \
- ((index) <= HE_MAX_106_TONE_RU_INDX) ? 2u : \
- ((index) <= HE_MAX_242_TONE_RU_INDX) ? 3u : \
- ((index) <= HE_MAX_484_TONE_RU_INDX) ? 4u :\
- ((index) <= HE_MAX_996_TONE_RU_INDX) ? 5u : 6u)
-
-/* Bit 8 indicates upper 80 MHz */
-#define HE_TXS_W4_MU_RU_INDEX_RU_INDEX_MASK 0x7Fu
-#define HE_TXS_W4_MU_RU_INDEX_TONE(index) HE_TXS_W4_MU_GET_RU_INDEX(((index) & \
- HE_TXS_W4_MU_RU_INDEX_RU_INDEX_MASK))
-
-#define HE_TXS_W3_MU_APTX_PWR_MASK 0x003F0000u
-#define HE_TXS_W3_MU_APTX_PWR_SHIFT 16u
-#define HE_TXS_W3_MU_PKT_EXT_MASK 0x01C00000u
-#define HE_TXS_W3_MU_PKT_EXT_SHIFT 22u
-#define HE_TXS_W3_MU_MORE_TF_MASK 0x02000000u
-#define HE_TXS_W3_MU_MORE_TF_SHIFT 25u
-#define HE_TXS_W3_MU_CS_REQ_MASK 0x04000000u
-#define HE_TXS_W3_MU_CS_REQ_SHIFT 26u
-#define HE_TXS_W3_MU_UL_BW_MASK 0x18000000u
-#define HE_TXS_W3_MU_UL_BW_SHIFT 27u
-#define HE_TXS_W3_MU_GI_LTF_MASK 0x60000000u
-#define HE_TXS_W3_MU_GI_LTF_SHIFT 29u
-#define HE_TXS_W3_MU_MIMO_LTF_MASK 0x80000000u
-#define HE_TXS_W3_MU_MIMO_LTF_SHIFT 31u
-
-#define HE_TXS_W3_MU_APTX_PWR(s3) (((s3) & HE_TXS_W3_MU_APTX_PWR_MASK) >> \
- HE_TXS_W3_MU_APTX_PWR_SHIFT)
-#define HE_TXS_W3_MU_PKT_EXT(s3) (((s3) & HE_TXS_W3_MU_PKT_EXT_MASK) >> \
- HE_TXS_W3_MU_PKT_EXT_SHIFT)
-#define HE_TXS_W3_MU_MORE_TF(s3) (((s3) & HE_TXS_W3_MU_MORE_TF_MASK) >> \
- HE_TXS_W3_MU_MORE_TF_SHIFT)
-#define HE_TXS_W3_MU_CS_REQ(s3) (((s3) & HE_TXS_W3_MU_CS_REQ_MASK) >> \
- HE_TXS_W3_MU_CS_REQ_SHIFT)
-#define HE_TXS_W3_MU_UL_BW(s3) (((s3) & HE_TXS_W3_MU_UL_BW_MASK) >> \
- HE_TXS_W3_MU_UL_BW_SHIFT)
-#define HE_TXS_W3_MU_GI_LTF(s3) (((s3) & HE_TXS_W3_MU_GI_LTF_MASK) >> \
- HE_TXS_W3_MU_GI_LTF_SHIFT)
-#define HE_TXS_W3_MU_MIMO_LT(s3) (((s3) & HE_TXS_W3_MU_MIMO_LTF_MASK) >> \
- HE_TXS_W3_MU_MIMO_LTF_SHIFT)
-
-#define HE_TXS_W4_MU_CODINF_TYPE_MASK 0x00000001u
-#define HE_TXS_W4_MU_CODINF_TYPE_SHIFT 0u
-#define HE_TXS_W4_MU_MCS_MASK 0x0000001Eu
-#define HE_TXS_W4_MU_MCS_SHIFT 1u
-#define HE_TXS_W4_MU_DCM_MASK 0x00000020u
-#define HE_TXS_W4_MU_DCM_SHIFT 5u
-#define HE_TXS_W4_RU_ALLOCATION_MASK 0x00003FC0u
-#define HE_TXS_W4_RU_ALLOCATION_SHIFT 6u
-
-#define HE_TXS_W4_MU_CODINF_TYPE(s4) (((s4) & HE_TXS_W4_MU_CODINF_TYPE_MASK) >> \
- HE_TXS_W4_MU_CODINF_TYPE_SHIFT)
-#define HE_TXS_W4_MU_MCS(s4) (((s4) & HE_TXS_W4_MU_MCS_MASK) >> \
- HE_TXS_W4_MU_MCS_SHIFT)
-#define HE_TXS_W4_MU_DCM(s4) (((s4) & HE_TXS_W4_MU_DCM_MASK) >> \
- HE_TXS_W4_MU_DCM_SHIFT)
-#define HE_TXS_W4_RU_ALLOCATION(s4) (((s4) & HE_TXS_W4_RU_ALLOCATION_MASK) >> \
- HE_TXS_W4_RU_ALLOCATION_SHIFT)
-
-#define HE_TXS_W4_MU_NSS_MASK 0x00030000u
-#define HE_TXS_W4_MU_NSS_SHIFT 16u
-#define HE_TXS_W4_MU_TARGET_RSSI_MASK 0x03FC0000u
-#define HE_TXS_W4_MU_TARGET_RSSI_SHIFT 18u
-
-#define HE_TXS_W4_MU_NSS(s4) (((s4) & HE_TXS_W4_MU_NSS_MASK) >> \
- HE_TXS_W4_MU_NSS_SHIFT)
-#define HE_TXS_W4_MU_TARGET_RSSI(s4) (((s4) & HE_TXS_W4_MU_TARGET_RSSI_MASK) >> \
- HE_TXS_W4_MU_TARGET_RSSI_SHIFT)
-
-/* WARNING: Modifying suppress reason codes?
- * Update wlc_tx_status_t and TX_STS_REASON_STRINGS and
- * wlc_tx_status_map_hw_to_sw_supr_code() also
- */
-/* status field bit definitions */
-/** suppress status reason codes */
-enum {
- TX_STATUS_SUPR_NONE = 0,
- TX_STATUS_SUPR_PMQ = 1, /**< PMQ entry */
- TX_STATUS_SUPR_FLUSH = 2, /**< flush request */
- TX_STATUS_SUPR_FRAG = 3, /**< previous frag failure */
- TX_STATUS_SUPR_TBTT = 3, /**< SHARED: Probe response supr for TBTT */
- TX_STATUS_SUPR_BADCH = 4, /**< channel mismatch */
- TX_STATUS_SUPR_EXPTIME = 5, /**< lifetime expiry */
- TX_STATUS_SUPR_UF = 6, /**< underflow */
-#ifdef WLP2P_UCODE
- TX_STATUS_SUPR_NACK_ABS = 7, /**< BSS entered ABSENCE period */
-#endif
- TX_STATUS_SUPR_PPS = 8, /**< Pretend PS */
- TX_STATUS_SUPR_PHASE1_KEY = 9, /**< Request new TKIP phase-1 key */
- TX_STATUS_UNUSED = 10, /**< Unused in trunk */
- TX_STATUS_INT_XFER_ERR = 11, /**< Internal DMA xfer error */
- TX_STATUS_SUPR_TWT_SP_OUT = 12, /**< Suppress Tx outside TWTSP */
- NUM_TX_STATUS_SUPR
-};
-
-/** Unexpected tx status for rate update */
-#define TX_STATUS_UNEXP(status) \
- ((((status.is_intermediate))) && \
- TX_STATUS_UNEXP_AMPDU(status))
-
-/** Unexpected tx status for A-MPDU rate update */
-#ifdef WLP2P_UCODE
-#define TX_STATUS_UNEXP_AMPDU(status) \
- ((((status.suppr_ind)) != TX_STATUS_SUPR_NONE) && \
- (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME) && \
- (((status.suppr_ind)) != TX_STATUS_SUPR_NACK_ABS))
-#else
-#define TX_STATUS_UNEXP_AMPDU(status) \
- ((((status.suppr_ind)) != TX_STATUS_SUPR_NONE) && \
- (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME))
-#endif
-
-/**
- * This defines the collection of supp reasons (including none)
- * for which mac has done its (re-)transmission in any of ucode retx schemes
- * which include ucode/hw/aqm agg
- */
-#define TXS_SUPR_MAGG_DONE_MASK ((1 << TX_STATUS_SUPR_NONE) | \
- (1 << TX_STATUS_SUPR_UF) | \
- (1 << TX_STATUS_SUPR_FRAG) | \
- (1 << TX_STATUS_SUPR_EXPTIME))
-#define TXS_SUPR_MAGG_DONE(suppr_ind) \
- ((1 << (suppr_ind)) & TXS_SUPR_MAGG_DONE_MASK)
-
-#define TX_STATUS_BA_BMAP03_MASK 0xF000 /**< ba bitmap 0:3 in 1st pkg */
-#define TX_STATUS_BA_BMAP03_SHIFT 12 /**< ba bitmap 0:3 in 1st pkg */
-#define TX_STATUS_BA_BMAP47_MASK 0x001E /**< ba bitmap 4:7 in 2nd pkg */
-#define TX_STATUS_BA_BMAP47_SHIFT 3 /**< ba bitmap 4:7 in 2nd pkg */
-
-/* RXE (Receive Engine) */
-
-/* RCM_CTL */
-#define RCM_INC_MASK_H 0x0080
-#define RCM_INC_MASK_L 0x0040
-#define RCM_INC_DATA 0x0020
-#define RCM_INDEX_MASK 0x001F
-#define RCM_SIZE 15
-
-#define RCM_MAC_OFFSET 0 /**< current MAC address */
-#define RCM_BSSID_OFFSET 3 /**< current BSSID address */
-#define RCM_F_BSSID_0_OFFSET 6 /**< foreign BSS CFP tracking */
-#define RCM_F_BSSID_1_OFFSET 9 /**< foreign BSS CFP tracking */
-#define RCM_F_BSSID_2_OFFSET 12 /**< foreign BSS CFP tracking */
-
-#define RCM_WEP_TA0_OFFSET 16
-#define RCM_WEP_TA1_OFFSET 19
-#define RCM_WEP_TA2_OFFSET 22
-#define RCM_WEP_TA3_OFFSET 25
-
-/* AMT - Address Match Table */
-
-/* AMT Attribute bits */
-#define AMT_ATTR_VALID 0x8000 /**< Mark the table entry valid */
-#define AMT_ATTR_A1 0x0008 /**< Match for A1 */
-#define AMT_ATTR_A2 0x0004 /**< Match for A2 */
-#define AMT_ATTR_A3 0x0002 /**< Match for A3 */
-
-/* AMT Index defines */
-#define AMT_SIZE_64 64 /* number of AMT entries */
-#define AMT_SIZE_128 128 /* number of AMT entries for corerev >= 64 */
-#define AMT_IDX_MAC 63 /**< device MAC */
-#define AMT_IDX_BSSID 62 /**< BSSID match */
-#define AMT_IDX_TRANSMITTED_BSSID 60 /**< transmitted BSSID in multiple BSSID set */
-#define AMT_WORD_CNT 2 /* Number of word count per AMT entry */
-
-#define AMT_SIZE(_corerev) (D11REV_GE(_corerev, 64) ? \
- (D11REV_GE(_corerev, 80) ? AMT_SIZE_64 : AMT_SIZE_128) : \
- AMT_SIZE_64)
-
-/* RMC entries */
-#define AMT_IDX_MCAST_ADDR 61 /**< MCAST address for Reliable Mcast feature */
-#define AMT_IDX_MCAST_ADDR1 59 /**< MCAST address for Reliable Mcast feature */
-#define AMT_IDX_MCAST_ADDR2 58 /**< MCAST address for Reliable Mcast feature */
-#define AMT_IDX_MCAST_ADDR3 57 /**< MCAST address for Reliable Mcast feature */
-
-#ifdef WLMESH
-/* note: this is max supported by ucode. But ARM-driver can
- * only mesh_info->mesh_max_peers which should be <= this value.
- */
-
-#define AMT_MAX_MESH_PEER 10
-#define AMT_MAXIDX_MESH_PEER 60
-#define AMT_MAXIDX_P2P_USE \
- (AMT_MAXIDX_MESH_PEER - AMT_MAX_MESH_PEER)
-#else
-#define AMT_MAXIDX_P2P_USE 60 /**< Max P2P entry to use */
-#endif /* WL_STA_MONITOR */
-#define AMT_MAX_TXBF_ENTRIES 7 /**< Max tx beamforming entry */
-/* PSTA AWARE AP: Max PSTA Tx beamforming entry */
-#define AMT_MAX_TXBF_PSTA_ENTRIES 20
-
-/* M_AMT_INFO SHM bit field definition */
-#define AMTINFO_BMP_IBSS (1u << 0u) /* IBSS Station */
-#define AMTINFO_BMP_MESH (1u << 1u) /* MESH Station */
-#define AMTINFO_BMP_BSSID (1u << 2u) /* BSSID-only */
-#define AMTINFO_BMP_IS_WAPI (1u << 3u) /* For WAPI keyid extraction */
-#define AMTINFO_BMP_IS_HE (1u << 13u) /* For HE peer indication */
-
-#define AUXPMQ_ENTRIES 64 /* number of AUX PMQ entries */
-#define AUXPMQ_ENTRY_SIZE 8
-
-/* PSM Block */
-
-/* psm_phy_hdr_param bits */
-#define MAC_PHY_RESET 1
-#define MAC_PHY_CLOCK_EN 2
-#define MAC_PHY_FORCE_CLK 4
-#define MAC_IHRP_CLOCK_EN 15
-
-/* PSMCoreControlStatus (IHR Address 0x078) bit definitions */
-#define PSM_CORE_CTL_AR (1 << 0)
-#define PSM_CORE_CTL_HR (1 << 1)
-#define PSM_CORE_CTL_IR (1 << 2)
-#define PSM_CORE_CTL_AAR (1 << 3)
-#define PSM_CORE_CTL_HAR (1 << 4)
-#define PSM_CORE_CTL_PPAR (1 << 5)
-#define PSM_CORE_CTL_SS (1 << 6)
-#define PSM_CORE_CTL_REHE (1 << 7)
-#define PSM_CORE_CTL_PPAS (1 << 13)
-#define PSM_CORE_CTL_AAS (1 << 14)
-#define PSM_CORE_CTL_HAS (1 << 15)
-
-#define PSM_CORE_CTL_LTR_BIT 9
-#define PSM_CORE_CTL_LTR_MASK 0x3
-
-#define PSM_SBACCESS_FIFO_MODE (1 << 1)
-#define PSM_SBACCESS_EXT_ERR (1 << 11)
-
-/* WEP Block */
-
-/* WEP_WKEY */
-#define WKEY_START (1 << 8)
-#define WKEY_SEL_MASK 0x1F
-
-/* WEP data formats */
-
-/* the number of RCMTA entries */
-#define RCMTA_SIZE 50
-
-/* max keys in M_TKMICKEYS_BLK - 96 * sizeof(uint16) */
-#define WSEC_MAX_TKMIC_ENGINE_KEYS(_corerev) ((D11REV_GE(_corerev, 64)) ? \
- AMT_SIZE(_corerev) : 12) /* 8 + 4 default - 2 mic keys 8 bytes each */
-
-/* max keys in M_WAPIMICKEYS_BLK - 64 * sizeof(uint16) */
-#define WSEC_MAX_SMS4MIC_ENGINE_KEYS(_corerev) ((D11REV_GE(_corerev, 64)) ? \
- AMT_SIZE(_corerev) : 8) /* 4 + 4 default - 16 bytes each */
-
-/* max RXE match registers */
-#define WSEC_MAX_RXE_KEYS 4
-
-/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
-/* SKL (Security Key Lookup) */
-#define SKL_POST80_ALGO_MASK 0x000F
-#define SKL_PRE80_ALGO_MASK 0x0007
-#define SKL_ALGO_SHIFT 0
-
-#define SKL_ALGO_MASK(_corerev) (D11REV_GE(_corerev, 80) ? SKL_POST80_ALGO_MASK : \
- SKL_PRE80_ALGO_MASK)
-
-#define SKL_WAPI_KEYID_MASK 0x8000
-#define SKL_WAPI_KEYID_SHIFT 15
-#define SKL_INDEX_SHIFT 4
-
-#define SKL_PRE80_WAPI_KEYID_MASK 0x0008
-#define SKL_PRE80_WAPI_KEYID_SHIFT 3
-
-#define SKL_INDEX_MASK(_corerev) ((D11REV_GE(_corerev, 64)) ? \
- (0x0FF0) : (0x03F0))
-#define SKL_GRP_ALGO_MASK(_corerev) ((D11REV_GE(_corerev, 64)) ? \
- ((D11REV_GE(_corerev, 80)) ? (0xE000) : (0x7000)) : (0x1c00))
-#define SKL_GRP_ALGO_SHIFT(_corerev) ((D11REV_GE(_corerev, 64)) ? \
- ((D11REV_GE(_corerev, 80)) ? (13) : (12)) : (10))
-
-#define SKL_STAMON_NBIT 0x8000 /* STA monitor bit */
-
-/* additional bits defined for IBSS group key support */
-#define SKL_IBSS_INDEX_MASK 0x01F0
-#define SKL_IBSS_INDEX_SHIFT 4
-#define SKL_IBSS_KEYID1_MASK 0x0600
-#define SKL_IBSS_KEYID1_SHIFT 9
-#define SKL_IBSS_KEYID2_MASK 0x1800
-#define SKL_IBSS_KEYID2_SHIFT 11
-#define SKL_IBSS_KEYALGO_MASK 0xE000
-#define SKL_IBSS_KEYALGO_SHIFT 13
-
-#define WSEC_MODE_OFF 0
-#define WSEC_MODE_HW 1
-#define WSEC_MODE_SW 2
-
-/* Mapped as per HW_ALGO */
-#define WSEC_ALGO_OFF 0
-#define WSEC_ALGO_WEP1 1
-#define WSEC_ALGO_TKIP 2
-#define WSEC_ALGO_WEP128 3
-#define WSEC_ALGO_AES_LEGACY 4
-#define WSEC_ALGO_AES 5
-#define WSEC_ALGO_SMS4 6
-#define WSEC_ALGO_SMS4_DFT_2005_09_07 7 /**< Not used right now */
-#define WSEC_ALGO_NALG 8
-
-/* For CORE_REV 80 */
-#define WSEC_ALGO_AES_GCM 8
-#define WSEC_ALGO_AES_GCM256 9
-
-/* For CORE_REV Less than 80 and */
-#define WSEC_ALGO_AES_PRE80_GCM 6
-#define WSEC_ALGO_AES_PRE80_GCM256 8
-
-/* D11 MAX TTAK INDEX */
-#define TSC_TTAK_PRE80_MAX_INDEX 50
-#define TSC_TTAK_MAX_INDEX 8
-/* D11 COREREV 80 TTAK KEY INDEX SHIFT */
-#define SKL_TTAK_INDEX_SHIFT 13
-#define SKL_TTAK_INDEX_MASK 0xE000
-
-/* D11 PRECOREREV 40 Hw algos...changed from corerev 40 */
-#define D11_PRE40_WSEC_ALGO_AES 3
-#define D11_PRE40_WSEC_ALGO_WEP128 4
-#define D11_PRE40_WSEC_ALGO_AES_LEGACY 5
-#define D11_PRE40_WSEC_ALGO_SMS4 6
-#define D11_PRE40_WSEC_ALGO_NALG 7
-
-#define D11_WSEC_ALGO_AES(_corerev) WSEC_ALGO_AES
-
-#define AES_MODE_NONE 0
-#define AES_MODE_CCM 1
-#define AES_MODE_OCB_MSDU 2
-#define AES_MODE_OCB_MPDU 3
-#define AES_MODE_CMAC 4
-#define AES_MODE_GCM 5
-#define AES_MODE_GMAC 6
-
-/* WEP_CTL (Rev 0) */
-#define WECR0_KEYREG_SHIFT 0
-#define WECR0_KEYREG_MASK 0x7
-#define WECR0_DECRYPT (1 << 3)
-#define WECR0_IVINLINE (1 << 4)
-#define WECR0_WEPALG_SHIFT 5
-#define WECR0_WEPALG_MASK (0x7 << 5)
-#define WECR0_WKEYSEL_SHIFT 8
-#define WECR0_WKEYSEL_MASK (0x7 << 8)
-#define WECR0_WKEYSTART (1 << 11)
-#define WECR0_WEPINIT (1 << 14)
-#define WECR0_ICVERR (1 << 15)
-
-/* Frame template map byte offsets */
-#define T_ACTS_TPL_BASE (0)
-#define T_NULL_TPL_BASE (0xc * 2)
-#define T_QNULL_TPL_BASE (0x1c * 2)
-#define T_RR_TPL_BASE (0x2c * 2)
-#define T_BCN0_TPL_BASE (0x34 * 2)
-#define T_PRS_TPL_BASE (0x134 * 2)
-#define T_BCN1_TPL_BASE (0x234 * 2)
-#define T_P2P_NULL_TPL_BASE (0x340 * 2)
-#define T_P2P_NULL_TPL_SIZE (32)
-#define T_TRIG_TPL_BASE (0x90 * 2)
-
-/* FCBS base addresses and sizes in BM */
-
-#define FCBS_DS0_BM_CMD_SZ_CORE0 0x0200 /* 512 bytes */
-#define FCBS_DS0_BM_DAT_SZ_CORE0 0x0200 /* 512 bytes */
-
-#ifndef FCBS_DS0_BM_CMDPTR_BASE_CORE0
-#define FCBS_DS0_BM_CMDPTR_BASE_CORE0 0x3000
-#endif
-#define FCBS_DS0_BM_DATPTR_BASE_CORE0 (FCBS_DS0_BM_CMDPTR_BASE_CORE0 + FCBS_DS0_BM_CMD_SZ_CORE0)
-
-#define FCBS_DS0_BM_CMD_SZ_CORE1 0x0200 /* 512 bytes */
-#define FCBS_DS0_BM_DAT_SZ_CORE1 0x0200 /* 512 bytes */
-
-#ifndef FCBS_DS0_BM_CMDPTR_BASE_CORE1
-#define FCBS_DS0_BM_CMDPTR_BASE_CORE1 0x2400
-#endif
-#define FCBS_DS0_BM_DATPTR_BASE_CORE1 (FCBS_DS0_BM_CMDPTR_BASE_CORE1 + FCBS_DS0_BM_CMD_SZ_CORE1)
-
-#define FCBS_DS0_BM_CMD_SZ_CORE2 0x0200 /* 512 bytes */
-#define FCBS_DS0_BM_DAT_SZ_CORE2 0x0200 /* 512 bytes */
-
-#define FCBS_DS1_BM_CMD_SZ_CORE0 0x2000 /* Not used */
-#define FCBS_DS1_BM_DAT_SZ_CORE0 0x2000 /* Not used */
-
-#define FCBS_DS1_BM_CMDPTR_BASE_CORE0 0x17B4
-#define FCBS_DS1_BM_DATPTR_BASE_CORE0 (FCBS_DS1_BM_CMDPTR_BASE_CORE0 + FCBS_DS1_BM_CMD_SZ_CORE0)
-
-#define FCBS_DS1_BM_CMD_SZ_CORE1 0x2000 /* Not used */
-#define FCBS_DS1_BM_DAT_SZ_CORE1 0x2000 /* Not used */
-
-#define FCBS_DS1_BM_CMDPTR_BASE_CORE1 0x17B4
-#define FCBS_DS1_BM_DATPTR_BASE_CORE1 (FCBS_DS1_BM_CMDPTR_BASE_CORE1 + FCBS_DS1_BM_CMD_SZ_CORE1)
-
-#define T_BA_TPL_BASE T_QNULL_TPL_BASE /**< template area for BA */
-
-#define T_RAM_ACCESS_SZ 4 /**< template ram is 4 byte access only */
-
-#define TPLBLKS_PER_BCN_NUM 2
-#define TPLBLKS_AC_PER_BCN_NUM 1
-
-#if defined(WLLPRS) && defined(MBSS)
-#define TPLBLKS_PER_PRS_NUM 4
-#define TPLBLKS_AC_PER_PRS_NUM 2
-#else
-#define TPLBLKS_PER_PRS_NUM 2
-#define TPLBLKS_AC_PER_PRS_NUM 1
-#endif /* WLLPRS && MBSS */
-
-/* MAC Sample Collect Params */
-
-/* SampleCapture set-up options in
- * different registers based on CoreRev
- */
-/* CoreRev >= 50, use SMP_CTRL in TXE_IHR */
-#define SC_SRC_MAC 2 /* MAC as Sample Collect Src */
-#define SC_SRC_SHIFT 3 /* SC_SRC bits [3:4] */
-#define SC_TRIG_SHIFT 5
-#define SC_TRANS_SHIFT 6
-#define SC_MATCH_SHIFT 7
-#define SC_STORE_SHIFT 8
-
-#define SC_STRT 1
-#define SC_TRIG_EN (1 << SC_TRIG_SHIFT)
-#define SC_TRANS_EN (1 << SC_TRANS_SHIFT)
-#define SC_MATCH_EN (1 << SC_MATCH_SHIFT)
-#define SC_STORE_EN (1 << SC_STORE_SHIFT)
-
-/* CoreRev < 50, use PHY_CTL in PSM_IHR */
-#define PHYCTL_PHYCLKEN (1 << 1)
-#define PHYCTL_FORCE_GATED_CLK_ON (1 << 2)
-#define PHYCTL_SC_STRT (1 << 4)
-#define PHYCTL_SC_SRC_LB (1 << 7)
-#define PHYCTL_SC_TRIG_EN (1 << 8)
-#define PHYCTL_SC_TRANS_EN (1 << 9)
-#define PHYCTL_SC_STR_EN (1 << 10)
-#define PHYCTL_IHRP_CLK_EN (1 << 15)
-/* End MAC Sample Collect Params */
-
-#define ANTSEL_CLKDIV_4MHZ 6
-#define MIMO_ANTSEL_BUSY 0x4000 /**< bit 14 (busy) */
-#define MIMO_ANTSEL_SEL 0x8000 /**< bit 15 write the value */
-#define MIMO_ANTSEL_WAIT 50 /**< 50us wait */
-#define MIMO_ANTSEL_OVERRIDE 0x8000 /**< flag */
-
-typedef struct shm_acparams shm_acparams_t;
-BWL_PRE_PACKED_STRUCT struct shm_acparams {
- uint16 txop;
- uint16 cwmin;
- uint16 cwmax;
- uint16 cwcur;
- uint16 aifs;
- uint16 bslots;
- uint16 reggap;
- uint16 status;
- uint16 txcnt;
- uint16 rsvd[7];
-} BWL_POST_PACKED_STRUCT;
-
-#define WME_STATUS_NEWAC (1 << 8)
-
-/* M_HOST_FLAGS */
-#define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */
-#define MHF1 0 /* Hostflag 1 index */
-#define MHF2 1 /* Hostflag 2 index */
-#define MHF3 2 /* Hostflag 3 index */
-#define MHF4 3 /* Hostflag 4 index */
-#define MHF5 4 /* Hostflag 5 index */
-
-#define MXHFMAX 1 /* Number of valid PSMx hostflag half-word (uint16) */
-#define MXHF0 64 /* PSMx Hostflag 0 index */
-
-/* Flags in M_HOST_FLAGS */
-#define MHF1_D11AC_DYNBW 0x0001 /**< dynamic bw */
-#define MHF1_WLAN_CRITICAL 0x0002 /**< WLAN is in critical state */
-#define MHF1_MBSS_EN 0x0004 /**< Enable MBSS: RXPUWAR deprecated for rev >= 9 */
-#define MHF1_BTCOEXIST 0x0010 /**< Enable Bluetooth / WLAN coexistence */
-#define MHF1_P2P_SKIP_TIME_UPD 0x0020 /**< Skip P2P SHM updates and P2P event generations */
-#define MHF1_TXMUTE_WAR 0x0040 /**< ucode based Tx mute */
-#define MHF1_RXFIFO1 0x0080 /**< Switch data reception from RX fifo 0 to fifo 1 */
-#define MHF1_EDCF 0x0100 /**< Enable EDCF access control */
-#define MHF1_ULP 0x0200 /**< Force Ucode to put chip in low power state */
-#define MHF1_FORCE_SEND_BCN 0x0800 /**< Force send bcn, even if rcvd from peer STA (IBSS) */
-#define MHF1_TIMBC_EN 0x1000 /**< Enable Target TIM Transmission Time function */
-#define MHF1_RADARWAR 0x2000 /**< Enable Radar Detect WAR PR 16559 */
-#define MHF1_DEFKEYVALID 0x4000 /**< Enable use of the default keys */
-#define MHF1_CTS2SELF 0x8000 /**< Enable CTS to self full phy bw protection */
-
-/* Flags in M_HOST_FLAGS2 */
-#define MHF2_DISABLE_PRB_RESP 0x0001 /**< disable Probe Response in ucode */
-#define MHF2_HIB_FEATURE_ENABLE 0x0008 /* Enable HIB feature in ucode (60<=rev<80) */
-#define MHF2_SKIP_ADJTSF 0x0010 /**< skip TSF update when receiving bcn/probeRsp */
-#define MHF2_RSPBW20 0x0020 /**< Uses bw20 for response frames ack/ba/cts */
-#define MHF2_TXBCMC_NOW 0x0040 /**< Flush BCMC FIFO immediately */
-#define MHF2_PPR_HWPWRCTL 0x0080 /**< TSSI_DIV WAR (rev<80) */
-#define MHF2_BTC2WIRE_ALTGPIO 0x0100 /**< BTC 2wire in alternate pins */
-#define MHF2_BTCPREMPT 0x0200 /**< BTC enable bluetooth check during tx */
-#define MHF2_SKIP_CFP_UPDATE 0x0400 /**< Skip CFP update ; for d11 rev <= 80 */
-#define MHF2_TX_TMSTMP 0x0800 /**< Enable passing tx-timestamps in tx-status */
-#define MHF2_UFC_GE84 0x2000 /**< Enable UFC in CT mode */
-#define MHF2_NAV_NORST_WAR 0x4000 /**< WAR to use rogue NAV duration */
-#define MHF2_BTCANTMODE 0x4000 // OBSOLETE (TO BE REMOVED)
-
-/* Flags in M_HOST_FLAGS3 */
-#define MHF3_ANTSEL_EN 0x0001 /**< enabled mimo antenna selection (REV<80) */
-#define MHF3_TKIP_FRAG_WAR 0x0001 /**< TKIP fragment corrupt WAR (REV>=80) */
-#define MHF3_TXSHAPER_EN 0x0002 /** enable tx shaper for non-OFDM-A frames */
-#define MHF3_ANTSEL_MODE 0x0002 /**< antenna selection mode: 0: 2x3, 1: 2x4 (REV<80) */
-#define MHF3_BTCX_DEF_BT 0x0004 /**< corerev >= 13 BT Coex. */
-#define MHF3_BTCX_ACTIVE_PROT 0x0008 /**< corerev >= 13 BT Coex. */
-#define MHF3_PKTENG_PROMISC 0x0010 /**< pass frames to driver in packet engine Rx mode */
-#define MHF3_SCANCORE_PM_EN 0x0040 /**< enable ScanCore PM from ucode */
-#define MHF3_PM_BCNRX 0x0080 /**< PM single core beacon RX for power reduction */
-#define MHF3_BTCX_SIM_RSP 0x0100 /**< allow limited lwo power tx when BT is active */
-#define MHF3_BTCX_PS_PROTECT 0x0200 /**< use PS mode to protect BT activity */
-#define MHF3_BTCX_SIM_TX_LP 0x0400 /**< use low power for simultaneous tx responses */
-#define MHF3_SELECT_RXF1 0x0800 /**< enable frame classification in pcie FD */
-#define MHF3_BTCX_ECI 0x1000 /**< Enable BTCX ECI interface */
-#define MHF3_NOISECAL_ENHANCE 0x2000
-
-/* Flags in M_HOST_FLAGS4 */
-#define MHF4_RCMTA_BSSID_EN 0x0002 /**< BTAMP: multiSta BSSIDs matching in RCMTA area */
-#define MHF4_SC_MIX_EN 0x0002 /**< set to enable 4389a0 specific changes */
-#define MHF4_BCN_ROT_RR 0x0004 /**< MBSSID: beacon rotate in round-robin fashion */
-#define MHF4_OPT_SLEEP 0x0008 /**< enable opportunistic sleep (REV<80) */
-#define MHF4_PM_OFFLOAD 0x0008 /**< enable PM offload */
-#define MHF4_PROXY_STA 0x0010 /**< enable proxy-STA feature */
-#define MHF4_AGING 0x0020 /**< Enable aging threshold for RF awareness */
-#define MHF4_STOP_BA_ON_NDP 0x0080 /**< Stop BlockAck to AP to get chance to send NULL data */
-#define MHF4_NOPHYHANGWAR 0x0100 /**< disable ucode WAR for idletssi cal (rev=61) */
-#define MHF4_WMAC_ACKTMOUT 0x0200 /**< reserved for WMAC testing */
-#define MHF4_NAPPING_ENABLE 0x0400 /**< Napping enable (REV<80) */
-#define MHF4_IBSS_SEC 0x0800 /**< IBSS WPA2-PSK operating mode */
-#define MHF4_SISO_BCMC_RX 0x1000 /* Disable switch to MIMO on recving multicast TIM */
-#define MHF4_RSDB_CR1_MINIPMU_CAL_EN 0x8000 /* for 4349B0. JIRA:SW4349-1469 */
-
-/* Flags in M_HOST_FLAGS5 */
-#define MHF5_BTCX_LIGHT 0x0002 /**< light coex mode, off txpu only for critical BT */
-#define MHF5_BTCX_PARALLEL 0x0004 /**< BT and WLAN run in parallel. */
-#define MHF5_BTCX_DEFANT 0x0008 /**< default position for shared antenna */
-#define MHF5_P2P_MODE 0x0010 /**< Enable P2P mode */
-#define MHF5_LEGACY_PRS 0x0020 /**< Enable legacy probe resp support */
-#define MHF5_HWRSSI_EN 0x0800 /**< Enable HW RSSI (ac) */
-#define MHF5_HIBERNATE 0x1000 /**< Force ucode to power save until wake-bit */
-#define MHF5_BTCX_GPIO_DEBUG 0x4000 /**< Enable gpio pins for btcoex ECI signals */
-#define MHF5_SUPPRESS_PRB_REQ 0x8000 /**< Suppress probe requests at ucode level */
-
-/* Flags in M_HOST_FLAGS6 */
-#define MHF6_TXPWRCAP_RST_EN 0x0001 /** < Ucode clear phyreg after each tx */
-#define MHF6_TXPWRCAP_EN 0x0002 /** < Enable TX power capping in ucode */
-#define MHF6_TSYNC_AVB 0x0004 /** Enable AVB for timestamping */
-#define MHF6_TSYNC_3PKG 0x0020 /** < Enable 3rd txstatus package */
-#define MHF6_TDMTX 0x0040 /** < Enable SDB TDM in ucode */
-#define MHF6_TSYNC_NODEEPSLP 0x0080 /** < Disable deep sleep to keep AVB clock */
-#define MHF6_TSYNC_CAL 0x0100 /** < Enable Tsync cal in ucode */
-#define MHF6_TXPWRCAP_IOS_NBIT 0x0200 /** < Enable IOS mode of operation for Txpwrcap (REV>=80) */
-#define MHF6_MULBSSID_NBIT 0x0400 /** < associated to AP belonging to a multiple BSSID set */
-#define MHF6_HEBCN_TX_NBIT 0x0800 /** < HE BCN-TX */
-#define MHF6_LATENCY_EN 0x2000 /** < Enable Latency instrumentation in ucode */
-#define MHF6_PTMSTS_EN 0x4000 /** < Enable PTM Status */
-
-/* MX_HOST_FLAGS */
-/* Flags for MX_HOST_FLAGS0 */
-#define MXHF0_RSV0 0x0001 /* ucode internal, not exposed yet */
-#define MXHF0_TXDRATE 0x0002 /* mu txrate to use rate from txd */
-#define MXHF0_CHKFID 0x0004 /* check if frameid->fifo matches hw txfifo idx */
-#define MXHF0_DISWAR 0x0008 /* disable some WAR. */
-
-/* M_AXC_HOST_FLAGS0 */
-#define MAXCHF0_WAIT_TRIG 0x0001 /* Hold frames till trigger frame is rxed */
-#define MAXCHF0_HTC_SUPPORT 0x0002 /* 11AX HTC field support */
-#define MAXCHF0_AX_ASSOC_SHIFT 0x0003 /* 11AX association indicator */
-#define MAXCHF0_HEB_CONFIG 0x0004 /* HEB configuration */
-#define MAXCHF0_ACI_DET 0x0008 /* ACI detect soft enable */
-#define MAXCHF0_TRIGRES_LP 0x0010 /* Lite-Point testing */
-#define MAXCHF0_HDRCONV_SHIFT 5u /* Enable header conversion */
-#define MAXCHF0_HDRCONV (1 << MAXCHF0_HDRCONV_SHIFT)
-#define MAXCHF0_FORCE_ZERO_PPR_SHIFT 6u /* Force PPR value to 0 for ULTPC */
-#define MAXCHF0_FORCE_ZERO_PPR (1 << MAXCHF0_FORCE_ZERO_PPR_SHIFT)
-#define MAXCHF0_DISABLE_PYLDECWAR_SHIFT 7u /* Disable WAR for Paydecode issue */
-#define MAXCHF0_DISABLE_PYLDECWAR (1 << MAXCHF0_DISABLE_PYLDECWAR_SHIFT)
-#define MAXCHF0_BSR_SUPPORT_SHIFT 8u /* BSR is supported */
-#define MAXCHF0_BSR_SUPPORT (1 << MAXCHF0_BSR_SUPPORT_SHIFT)
-#define MAXCHF0_MUEDCA_VALID_SHIFT 9u /* MUEDCA information is valid */
-#define MAXCHF0_MUEDCA_VALID (1 << MAXCHF0_MUEDCA_VALID_SHIFT)
-/* Bit 10 definition missing? */
-#define MAXCHF0_TWT_PKTSUPP_SHIFT 11u /* Enable pkt suppress outside TWT SP */
-#define MAXCHF0_TWT_PKTSUPP_EN (1 << MAXCHF0_TWT_PKTSUPP_SHIFT)
-#define MAXCHF0_TBPPDU_STATUS_SHIFT 12u
-#define MAXCHF0_TBPPDU_STATUS_EN (1 << MAXCHF0_TBPPDU_STATUS_SHIFT)
-#define MAXCHF0_11AX_TXSTATUS_EXT_SHIFT 13u /* Enable 128 BA pkg in TX status */
-#define MAXCHF0_11AX_TXSTATUS_EXT_EN (1u << MAXCHF0_11AX_TXSTATUS_EXT_SHIFT)
-#define MAXCHF1_11AX_TXSTATUS_EXT_SHIFT 0u /* Enable 256 BA pkg in TX status */
-#define MAXCHF1_11AX_TXSTATUS_EXT_EN (1u << MAXCHF1_11AX_TXSTATUS_EXT_SHIFT)
-/* Bit 14 for UORA_EN */
-#define MAXCHF0_11AX_UORA_SHIFT 14u /* Enable UORA support */
-#define MAXCHF0_11AX_UORA_EN (1u << MAXCHF0_11AX_UORA_SHIFT)
-
-/* M_AXC_HOST_FLAGS1 */
-#define MAXCHF1_ITXSTATUS_EN 0x0004u /* Enable intermediate txs for TB PPDU */
-#define MAXCHF1_OBSSHWSTATS_EN 0x0008u /* Enable ucode OBSS stats monitoring */
-
-/* M_SC_HOST_FLAGS */
-#define C_SCCX_STATS_EN 0x0001u /* Enable SC stats */
-#define C_SC_BTMC_COEX_EN 0x0002u /* Enable WLSC-BTMC coex */
-
-/** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev61.1 */
-typedef struct d11rxhdrshort_rev61_1 d11rxhdrshort_rev61_1_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_rev61_1 {
- uint16 RxFrameSize; /**< Actual byte length of the frame data received */
-
- /* These two 8-bit fields remain in the same order regardless of
- * processor byte order.
- */
- uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */
- uint8 fifo; /**< rx fifo number */
- uint16 mrxs; /**< MAC Rx Status */
- uint16 RxFrameSize0; /**< rxframesize for fifo-0 (in bytes). */
- uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */
- uint16 RxTSFTimeL; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
- uint16 RxTSFTimeH; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
- uint16 aux_status; /**< DMA writes into this field. ucode treats as reserved. */
-} BWL_POST_PACKED_STRUCT;
-
-/** Short version of receive frame status. Only used for non-last MSDU of AMSDU - pre80 */
-typedef struct d11rxhdrshort_lt80 d11rxhdrshort_lt80_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_lt80 {
- uint16 RxFrameSize; /**< Actual byte length of the frame data received */
-
- /* These two 8-bit fields remain in the same order regardless of
- * processor byte order.
- */
- uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */
- uint8 fifo; /**< rx fifo number */
- uint16 mrxs; /**< MAC Rx Status */
- uint16 RxTSFTime; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
- uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */
- uint16 aux_status; /**< DMA writes into this field. ucode treats as reserved. */
-} BWL_POST_PACKED_STRUCT;
-
-/* Errflag bits for ge80 */
-#define ERRFLAGS_ERR_STATE 0x0003u
-#define ERRFLAGS_GREATER_MSDU_LEN 0x0001u
-#define ERRFLAGS_AMSDU_TRUNCATED 0x0002u
-#define ERRFLAGS_HDRCONV_MASK 0x00F0u
-#define ERRFLAGS_HDRCONV_SHIFT 4u
-#define ERRFLAGS_CSI_LEN_64K 0x0100u
-#define ERRFLAGS_MESH_FMT_ERR 0x0200u
-
-/* Register 'D11_RXE_ERRVAL' bits for ge80 */
-#define RXEERR_GREATER_MSDU_LEN (1u << 6)
-
-/* 128 BA configuration */
-/* Register D11_TXBA_DataSel bits for ge80 */
-#define TXBA_DATASEL_WSIZE_BITMAP_LEN_ENC_SEL (1u << 0u)
-
-/* Register D11_TXBA_Data bits (ge80) */
-#define TXBA_DATA_WSIZE_256 (0x100u)
-#define TXBA_DATA_WSIZE_128 (0x80u)
-#define TXBA_DATA_WSIZE_64 (0x40u)
-
-/* HW optimisation to generate bitmap based on start SSN & max SSN */
-#define TXBA_DATA_HW_CONST (0xfu << 12)
-
-/* Register D11_RXE_BA_LEN bits (ge80) */
-#define RXE_BA_LEN_RXBA_64 (0x0u)
-#define RXE_BA_LEN_RXBA_128 (0x1u)
-#define RXE_BA_LEN_RXBA_256 (0x2u)
-#define RXE_BA_LEN_TID0_SHIFT (0u)
-#define RXE_BA_LEN_TID1_SHIFT (2u)
-#define RXE_BA_LEN_TID2_SHIFT (4u)
-#define RXE_BA_LEN_TID3_SHIFT (6u)
-#define RXE_BA_LEN_TID4_SHIFT (8u)
-#define RXE_BA_LEN_TID5_SHIFT (10u)
-#define RXE_BA_LEN_TID6_SHIFT (12u)
-#define RXE_BA_LEN_TID7_SHIFT (14u)
-
-/* Register D11_RXE_BA_LEN_ENC bits (ge80) */
-#define RXE_BA_LEN_ENC_BA32_VAL (0x3u << 0u)
-#define RXE_BA_LEN_ENC_BA64_VAL (0x0u << 2u)
-#define RXE_BA_LEN_ENC_BA128_VAL (0x1u << 4u)
-#define RXE_BA_LEN_ENC_BA256_VAL (0x2u << 6u)
-
-/* Register D11_RXE_TXBA_CTL2 (ge80) */
-#define RXE_TXBA_CTL2_CONIG_SINGLE_TID (0x0u << 0u)
-#define RXE_TXBA_CTL2_CONIG_ALL_TID (0x1u << 0u)
-#define RXE_TXBA_CTL2_SEL_TID0 (0x0u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID1 (0x1u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID2 (0x2u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID3 (0x3u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID4 (0x4u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID5 (0x5u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID6 (0x6u << 12u)
-#define RXE_TXBA_CTL2_SEL_TID7 (0x7u << 12u)
-
-/**
- * Special Notes
- * #1: dma_flags, fifo
- * These two 8-bit fields remain in the same order regardless of
- * processor byte order.
- * #2: pktclass
- * 16 bit bitmap is a result of Packet (or Flow ) Classification.
- *
- * 0 : Flow ID Different
- * 1,2,3 : A1, A2, A3 Different
- * 4 : TID Different
- * 5, 6 : DA, SA from AMSDU SubFrame Different
- * 7 : FC Different
- * 8 : AMPDU boundary
- * 9 - 15 : Reserved
- * #3: errflags
- * These bits indicate specific errors detected by the HW on the Rx Path.
- * However, these will be relevant for Last MSDU Status only.
- *
- * Whenever there is an error at any MSDU, HW treats it as last
- * MSDU and send out last MSDU status.
- */
-
-#define D11RXHDR_HW_STATUS_GE80 \
- uint16 RxFrameSize; /**< Actual byte length of the frame data received */ \
- /* For comments see special note #1 above */\
- uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */ \
- uint8 fifo; /**< rx fifo number */ \
- \
- uint16 mrxs; /**< MAC Rx Status */ \
- uint16 RxFrameSize0; /**< rxframesize for fifo-0 (in bytes). */ \
- uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */ \
- uint16 pktclass; \
- uint32 filtermap; /**< 32 bit bitmap indicates which "Filters" have matched. */ \
- /* For comments see special note #2 above */ \
- uint16 flowid; /**< result of Flow ID Look Up performed by the HW. */ \
- /* For comments see special note #3 above */\
- uint16 errflags;
-
-#define D11RXHDR_UCODE_STATUS_GE80 \
- /**< Ucode Generated Status (16 Bytes) */ \
- uint16 RxStatus1; /**< MAC Rx Status */ \
- uint16 RxStatus2; /**< extended MAC Rx status */ \
- uint16 RxChan; /**< Rx channel info or chanspec */ \
- uint16 AvbRxTimeL; /**< AVB RX timestamp low16 */ \
- uint16 AvbRxTimeH; /**< AVB RX timestamp high16 */ \
- uint16 RxTSFTime; /**< Lower 16 bits of Rx timestamp */ \
- uint16 RxTsfTimeH; /**< Higher 16 bits of Rx timestamp */ \
- uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */
-
-#define D11RXHDR_HW_STATUS_GE87_1 /**< HW Generated 24 bytes RX Status */ \
- D11RXHDR_HW_STATUS_GE80 /**< First 20 bytes are same as mac rev >= 80 */ \
- uint16 roe_hw_sts; /**< ROE HW status */ \
- uint16 roe_err_flags; /**< ROE error flags */
-
-#define D11RXHDR_UCODE_STATUS_GE87_1 /**< Ucode Generated Status (22 Bytes) */ \
- uint16 RxStatus1; /**< MAC Rx Status */ \
- uint16 RxStatus2; /**< extended MAC Rx status */ \
- uint16 RxChan; /**< Rx channel info or chanspec */ \
- uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */ \
- uint32 AVBRxTime; /**< 32 bit AVB timestamp */ \
- uint32 TSFRxTime; /**< 32 bit TSF timestamp */ \
- uint64 PTMRxTime; /**< 64 bit PTM timestamp */
-
- /**< HW Generated Status (20 Bytes) */
-/** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev80 */
-typedef struct d11rxhdrshort_ge87_1 d11rxhdrshort_ge87_1_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_ge87_1 {
-
- D11RXHDR_HW_STATUS_GE87_1
-
-} BWL_POST_PACKED_STRUCT;
-
-/** Mid version of receive frame status. Only used for MPDU of AMPDU - rev80 */
-typedef struct d11rxhdrmid_ge87_1 d11rxhdrmid_ge87_1_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrmid_ge87_1 {
-
- D11RXHDR_HW_STATUS_GE87_1
- D11RXHDR_UCODE_STATUS_GE87_1
-} BWL_POST_PACKED_STRUCT;
-
-/** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev80 */
-typedef struct d11rxhdrshort_ge80 d11rxhdrshort_ge80_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_ge80 {
-
- D11RXHDR_HW_STATUS_GE80
-
-} BWL_POST_PACKED_STRUCT;
-
-/** Mid version of receive frame status. Only used for MPDU of AMPDU - rev80 */
-typedef struct d11rxhdrmid_ge80 d11rxhdrmid_ge80_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdrmid_ge80 {
-
- D11RXHDR_HW_STATUS_GE80
- D11RXHDR_UCODE_STATUS_GE80
-
-} BWL_POST_PACKED_STRUCT;
-
-/** Receive Frame Data Header - pre80 */
-typedef struct d11rxhdr_lt80 d11rxhdr_lt80_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdr_lt80 {
- uint16 RxFrameSize; /**< Actual byte length of the frame data received */
-
- /**
- * These two 8-bit fields remain in the same order regardless of
- * processor byte order.
- */
- uint8 dma_flags; /* bit 0 indicates short or long rx status. 1 == short. */
- uint8 fifo; /* rx fifo number */
-
- uint16 PhyRxStatus_0; /**< PhyRxStatus 15:0 */
- uint16 PhyRxStatus_1; /**< PhyRxStatus 31:16 */
- uint16 PhyRxStatus_2; /**< PhyRxStatus 47:32 */
- uint16 PhyRxStatus_3; /**< PhyRxStatus 63:48 */
- uint16 PhyRxStatus_4; /**< PhyRxStatus 79:64 */
- uint16 PhyRxStatus_5; /**< PhyRxStatus 95:80 */
- uint16 RxStatus1; /**< MAC Rx Status */
- uint16 RxStatus2; /**< extended MAC Rx status */
-
- /**
- * - RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY
- */
- uint16 RxTSFTime;
-
- uint16 RxChan; /**< Rx channel info or chanspec */
- uint16 RxFrameSize0; /**< size of rx-frame in fifo-0 in case frame is copied to fifo-1 */
- uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */
- uint16 AvbRxTimeL; /**< AVB RX timestamp low16 */
- uint16 AvbRxTimeH; /**< AVB RX timestamp high16 */
- uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */
- /**
- * These bits indicate specific errors detected by the HW on the Rx Path.
- * However, these will be relevant for Last MSDU Status only.
- *
- * Whenever there is an error at any MSDU, HW treats it as last
- * MSDU and send out last MSDU status.
- */
- uint16 errflags;
-} BWL_POST_PACKED_STRUCT;
-
-#define N_PRXS_GE80 16 /* Total number of PhyRx status words for corerev >= 80 */
-#define N_PRXS_LT80 6 /* Total number of PhyRx status words for corerev < 80 */
-
-/* number of PhyRx status words newly added for (corerev >= 80) */
-#define N_PRXS_REM_GE80 (N_PRXS_GE80 - N_PRXS_LT80)
-
-/** RX Hdr definition - rev80 */
-typedef struct d11rxhdr_ge80 d11rxhdr_ge80_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge80 {
- /**
- * Even though rxhdr can be in short or long format, always declare it here
- * to be in long format. So the offsets for the other fields are always the same.
- */
-
- /**< HW Generated Status (20 Bytes) */
- D11RXHDR_HW_STATUS_GE80
- D11RXHDR_UCODE_STATUS_GE80
-
- /**< PHY Generated Status (32 Bytes) */
- uint16 PhyRxStatus_0; /**< PhyRxStatus 15:0 */
- uint16 PhyRxStatus_1; /**< PhyRxStatus 31:16 */
- uint16 PhyRxStatus_2; /**< PhyRxStatus 47:32 */
- uint16 PhyRxStatus_3; /**< PhyRxStatus 63:48 */
- uint16 PhyRxStatus_4; /**< PhyRxStatus 79:64 */
- uint16 PhyRxStatus_5; /**< PhyRxStatus 95:80 */
- uint16 phyrxs_rem[N_PRXS_REM_GE80]; /**< 20 bytes of remaining prxs (corerev >= 80) */
- /* Currently only 6 words are being pushed out of uCode: 6, 9, 16, 17, 21, 23 */
-} BWL_POST_PACKED_STRUCT;
-
-#define N_PRXS_GE85 32u // total number of PhyRxStatus BYTEs for rev >= 85
-
-typedef struct d11rxhdr_ge87_1 d11rxhdr_ge87_1_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge87_1 {
- /**
- * Even though rxhdr can be in short or long format, always declare it here
- * to be in long format. So the offsets for the other fields are always the same.
- */
-
- D11RXHDR_HW_STATUS_GE87_1 /**< HW Generated Status (24 Bytes) */
- D11RXHDR_UCODE_STATUS_GE87_1 /**< uCode Generated Status (24 Bytes) */
- uint8 PHYRXSTATUS[N_PRXS_GE85]; /**< PHY Generated Status (32 Bytes) */
-} BWL_POST_PACKED_STRUCT;
-
-/* A wrapper structure for all versions of d11rxh short structures */
-typedef struct d11rxhdr_ge85 d11rxhdr_ge85_t;
-BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge85 {
- /**
- * Even though rxhdr can be in short or long format, always declare it here
- * to be in long format. So the offsets for the other fields are always the same.
- */
-
- /**< HW Generated Status (20 Bytes) */
- D11RXHDR_HW_STATUS_GE80
- D11RXHDR_UCODE_STATUS_GE80
-
- /**< PHY Generated Status (32 Bytes) */
- uint8 PHYRXSTATUS[N_PRXS_GE85];
-} BWL_POST_PACKED_STRUCT;
-
-/* A wrapper structure for all versions of d11rxh short structures */
-typedef union d11rxhdrshort {
- d11rxhdrshort_rev61_1_t rev61_1;
- d11rxhdrshort_lt80_t lt80;
- d11rxhdrshort_ge80_t ge80;
- d11rxhdrshort_ge87_1_t ge87_1;
-} d11rxhdrshort_t;
-
-/* A wrapper structure for all versions of d11rxh mid structures */
-typedef union d11rxhdrmid {
- d11rxhdrmid_ge80_t ge80;
- d11rxhdrmid_ge87_1_t ge87_1;
-} d11rxhdrmid_t;
-
-/* A wrapper structure for all versions of d11rxh structures */
-typedef union d11rxhdr {
- d11rxhdr_lt80_t lt80;
- d11rxhdr_ge80_t ge80;
- d11rxhdr_ge85_t ge85;
- d11rxhdr_ge87_1_t ge87_1;
-} d11rxhdr_t;
-
-#define D11RXHDRSHORT_GE87_1_ACCESS_REF(srxh, member) \
- (&((((d11rxhdrshort_t *)(srxh))->ge87_1).member))
-
-#define D11RXHDRMID_GE87_1_ACCESS_REF(mrxh, member) \
- (&((((d11rxhdrmid_t *)(mrxh))->ge87_1).member))
-
-#define D11RXHDRSHORT_GE87_1_ACCESS_VAL(srxh, member) \
- ((((d11rxhdrshort_t *)(srxh))->ge87_1).member)
-
-#define D11RXHDRMID_GE87_1_ACCESS_VAL(mrxh, member) \
- ((((d11rxhdrmid_t *)(mrxh))->ge87_1).member)
-
-#define D11RXHDR_GE87_1_ACCESS_REF(rxh, member) \
- (&((rxh)->ge87_1).member)
-
-#define D11RXHDR_GE87_1_ACCESS_VAL(rxh, member) \
- (((rxh)->ge87_1).member)
-
-#define D11RXHDR_GE87_1_SET_VAL(rxh, member, value) \
- (((rxh)->ge87_1).member = value)
-
-#define D11RXHDRSHORT_GE80_ACCESS_REF(srxh, member) \
- (&((((d11rxhdrshort_t *)(srxh))->ge80).member))
-
-#define D11RXHDRMID_GE80_ACCESS_REF(mrxh, member) \
- (&((((d11rxhdrmid_t *)(mrxh))->ge80).member))
-
-#define D11RXHDRSHORT_LT80_ACCESS_REF(srxh, member) \
- (&((((d11rxhdrshort_t *)(srxh))->lt80).member))
-
-#define D11RXHDRSHORT_GE80_ACCESS_VAL(srxh, member) \
- ((((d11rxhdrshort_t *)(srxh))->ge80).member)
-
-#define D11RXHDRMID_GE80_ACCESS_VAL(mrxh, member) \
- ((((d11rxhdrmid_t *)(mrxh))->ge80).member)
-
-#define D11RXHDRSHORT_LT80_ACCESS_VAL(srxh, member) \
- ((((d11rxhdrshort_t *)(srxh))->lt80).member)
-
-#define D11RXHDR_GE80_ACCESS_REF(rxh, member) \
- (&((rxh)->ge80).member)
-
-#define D11RXHDR_LT80_ACCESS_REF(rxh, member) \
- (&((rxh)->lt80).member)
-
-#define D11RXHDR_GE80_ACCESS_VAL(rxh, member) \
- (((rxh)->ge80).member)
-
-#define D11RXHDR_GE80_SET_VAL(rxh, member, value) \
- (((rxh)->ge80).member = value)
-
-#define D11RXHDR_LT80_ACCESS_VAL(rxh, member) \
- (((rxh)->lt80).member)
-
-#define D11RXHDR_LT80_SET_VAL(rxh, member, value) \
- (((rxh)->lt80).member = value)
-
-/** For accessing members of d11rxhdrshort_t by reference (address of members) */
-#define D11RXHDRSHORT_ACCESS_REF(srxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDRSHORT_GE87_1_ACCESS_REF(srxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDRSHORT_GE80_ACCESS_REF(srxh, member) : \
- D11RXHDRSHORT_LT80_ACCESS_REF(srxh, member))
-
-/** For accessing members of d11rxhdrshort_t by value (only value stored inside members accessed) */
-#define D11RXHDRSHORT_ACCESS_VAL(srxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDRSHORT_GE87_1_ACCESS_VAL(srxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDRSHORT_GE80_ACCESS_VAL(srxh, member) : \
- D11RXHDRSHORT_LT80_ACCESS_VAL(srxh, member))
-
-/** For accessing members of d11rxhdrmid_t by reference (address of members) */
-#define D11RXHDRMID_ACCESS_REF(mrxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDRMID_GE87_1_ACCESS_REF(mrxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDRMID_GE80_ACCESS_REF(mrxh, member) : NULL)
-
-/** For accessing members of d11rxhdrmid_t by value (only value stored inside members accessed) */
-#define D11RXHDRMID_ACCESS_VAL(mrxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDRMID_GE87_1_ACCESS_VAL(mrxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDRMID_GE80_ACCESS_VAL(mrxh, member) : NULL)
-
-/** For accessing members of d11rxhdr_t by reference (address of members) */
-#define D11RXHDR_ACCESS_REF(rxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_REF(rxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_REF(rxh, member) : \
- D11RXHDR_LT80_ACCESS_REF(rxh, member))
-
-/** For accessing members of d11rxhdr_t by value (only value stored inside members accessed) */
-#define D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, member) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, member) : \
- D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, member) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, member))
-
-/** For accessing members of d11rxhdr_t by value (only value stored inside members accessed) */
-#define D11RXHDR_SET_VAL(rxh, corerev, corerev_minor, member, value) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_SET_VAL(rxh, member, value) : \
- D11REV_GE(corerev, 80) ? D11RXHDR_GE80_SET_VAL(rxh, member, value) : \
- D11RXHDR_LT80_SET_VAL(rxh, member, value))
-
-#define D11RXHDR_PTM(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, PTMRxTime) : 0)
-
-#define D11RXHDR_AVB(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- (uint32)D11RXHDR_GE87_1_ACCESS_VAL(rxh, AVBRxTime) : \
- D11REV_GE(corerev, 80) ? ((uint32)D11RXHDR_GE80_ACCESS_VAL(rxh, AvbRxTimeL) | \
- ((uint32)D11RXHDR_GE80_ACCESS_VAL(rxh, AvbRxTimeH) << 16u)) : \
- ((uint32)D11RXHDR_LT80_ACCESS_VAL(rxh, AvbRxTimeL) | \
- ((uint32)D11RXHDR_LT80_ACCESS_VAL(rxh, AvbRxTimeH) << 16u)))
-
-#define D11RXHDR_TSF_REF(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_REF(rxh, TSFRxTime) : \
- D11REV_GE(corerev, 80) ? (uint32*)D11RXHDR_GE80_ACCESS_REF(rxh, RxTSFTime) : \
- (uint32*)D11RXHDR_LT80_ACCESS_REF(rxh, RxTSFTime))
-
-#define D11RXHDR_TSF(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, TSFRxTime) : \
- D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, RxTSFTime) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, RxTSFTime))
-
-#define RXS_SHORT_ENAB(rev) (D11REV_GE(rev, 64) || \
- D11REV_IS(rev, 60) || \
- D11REV_IS(rev, 62))
-
-#define RXS_MID_ENAB(rev) (D11REV_GE(rev, 80))
-#define RXS_LONG_ENAB(rev) (D11REV_GE(rev, 80))
-
-#define IS_D11RXHDRSHORT(rxh, rev, rev_min) ((RXS_SHORT_ENAB(rev) && \
- ((D11RXHDR_ACCESS_VAL((rxh), (rev), (rev_min), dma_flags)) & RXS_SHORT_MASK)) != 0)
-
-#define IS_D11RXHDRMID(rxh, rev, rev_min) ((RXS_MID_ENAB(rev) && \
- ((D11RXHDR_ACCESS_VAL((rxh), (rev), (rev_min), dma_flags)) == 0)))
-
-#define IS_D11RXHDRLONG(rxh, rev, rev_min) \
- ((!(IS_D11RXHDRSHORT((rxh), (rev), (rev_min)))) && \
- (!(IS_D11RXHDRMID((rxh), (rev), (rev_min)))))
-
-#define D11RXHDR_HAS_UCODE_STATUS(rxhdr, corerev, corerev_minor) \
- ((!IS_D11RXHDRSHORT((rxhdr), (corerev), (corerev_minor))) || \
- (IS_D11RXHDRMID((rxhdr), (corerev), (corerev_minor))))
-
-#define IS_PHYRXHDR_VALID(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- (D11RXHDR_GE87_1_ACCESS_VAL(rxh, dma_flags) == RXS_PHYRXST_VALID_REV_GE80) : \
- D11REV_GE(corerev, 80) ? \
- (D11RXHDR_GE80_ACCESS_VAL(rxh, dma_flags) == RXS_PHYRXST_VALID_REV_GE80) : \
- (D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_PHYRXST_VALID))
-
-#define RXHDR_GET_PAD_LEN(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- ((((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_PBPRES) != 0) ? HDRCONV_PAD : 0) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- (((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) & \
- RXSS_PBPRES) != 0) ? HDRCONV_PAD : 0) : \
- (((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus1) & RXS_PBPRES) != 0) ? HDRCONV_PAD : 0)))
-
-#define RXHDR_GET_PAD_PRES(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_PBPRES) != 0) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) & \
- RXSS_PBPRES) != 0) : \
- (((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus1) & RXS_PBPRES) != 0))))
-
-#define RXHDR_GET_CONV_TYPE(rxh, corerev, corerev_minor) \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, \
- HdrConvSt) & HDRCONV_ETH_FRAME) != 0) : ((D11RXHDR_ACCESS_VAL(rxh, \
- corerev, corerev_minor, HdrConvSt) & HDRCONV_ETH_FRAME) != 0))
-
-#define RXHDR_GET_ROE_ERR_STS(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_err_flags))) : 0)
-
-#define RXHDR_GET_ROE_L3_TYPE(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L3_PROT_TYPE_MASK) : 0)
-
-#define RXHDR_GET_ROE_L4_TYPE(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L4_PROT_TYPE_MASK) : 0)
-
-#define RXHDR_GET_ROE_L3_STATUS(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L3_CHKSUM_STATUS_MASK) : 0)
-
-#define RXHDR_GET_ROE_L4_STATUS(rxh, corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L4_CHKSUM_STATUS_MASK) : 0)
-
-#define RXHDR_GET_AGG_TYPE(rxh, corerev, corerev_minor) \
- (D11REV_GE(corerev, 80) ? \
- (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_AGGTYPE_MASK) >> RXSS_AGGTYPE_SHIFT) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) \
- & RXSS_AGGTYPE_MASK) >> RXSS_AGGTYPE_SHIFT) : \
- ((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_AGGTYPE_MASK) >> RXS_AGGTYPE_SHIFT)))
-
-#define RXHDR_GET_PBPRS_REF(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_REF(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_REF(rxh, mrxs)) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- ((D11RXHDRSHORT_ACCESS_REF(rxh, corerev, corerev_minor, mrxs))) : \
- (D11RXHDR_LT80_ACCESS_REF(rxh, RxStatus1))))
-
-#define RXHDR_GET_IS_DEFRAG(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- (D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxStatus1) & RXS_IS_DEFRAG) : 0)
-
-#define SET_RXHDR_PBPRS_REF_VAL(rxh, corerev, corerev_minor, val) \
- (D11REV_GE(corerev, 80) ? \
- (*val |= RXSS_PBPRES) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? (*val |= RXSS_PBPRES) : \
- (*val |= RXS_PBPRES)))
-
-#define CLEAR_RXHDR_PBPRS_REF_VAL(rxh, corerev, corerev_minor, val) \
- (D11REV_GE(corerev, 80) ? \
- (*val &= ~RXSS_PBPRES) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? (*val &= ~RXSS_PBPRES) : \
- (*val &= ~RXS_PBPRES)))
-
-#define RXHDR_GET_AMSDU(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_AMSDU_MASK) != 0) : \
- (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, \
- mrxs) & RXSS_AMSDU_MASK) != 0) : \
- ((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_AMSDU_MASK) != 0)))
-
-#ifdef BCMDBG
-#define RXHDR_GET_MSDU_COUNT(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \
- (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \
- D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \
- D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_MSDU_CNT_MASK) >> RXSS_MSDU_CNT_SHIFT) : \
- IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \
- (((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs)) & \
- RXSS_MSDU_CNT_MASK) >> RXSS_MSDU_CNT_SHIFT) : 0)
-
-#endif /* BCMDBG */
-
-/** Length of HW RX status in RxStatus */
-#define HW_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdrshort_ge87_1_t)) /* 24 bytes */
-#define HW_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdrshort_ge80_t)) /* 20 bytes */
-#define HW_RXHDR_LEN_REV_LT80 (sizeof(d11rxhdrshort_lt80_t)) /* 12 bytes */
-#define HW_RXHDR_LEN_REV_61_1 (sizeof(d11rxhdrshort_rev61_1_t)) /* 16 bytes */
-
-/** Length of HW RX status + ucode Rx status in RxStatus */
-#define MID_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdrmid_ge87_1_t)) /* 48 bytes */
-#define MID_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdrmid_ge80_t)) /* 36 bytes */
-
-/** Length of HW RX status + ucode RX status + PHY RX status + padding(if need align) */
-#define D11_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdr_ge87_1_t)) /* 80 bytes */
-#define D11_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdr_ge80_t)) /* 68 bytes */
-#define D11_RXHDR_LEN_REV_LT80 (sizeof(d11rxhdr_lt80_t)) /* 36 bytes */
-
-#define HW_RXHDR_LEN(corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? HW_RXHDR_LEN_REV_GE87_1 : \
- D11REV_GE(corerev, 80) ? HW_RXHDR_LEN_REV_GE80 : HW_RXHDR_LEN_REV_LT80)
-
-#define MID_RXHDR_LEN(corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? MID_RXHDR_LEN_REV_GE87_1 : \
- D11REV_GE(corerev, 80) ? \
- MID_RXHDR_LEN_REV_GE80 : NULL)
-
-#define D11_RXHDR_LEN(corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? D11_RXHDR_LEN_REV_GE87_1 : \
- D11REV_GE(corerev, 80) ? D11_RXHDR_LEN_REV_GE80 : \
- D11_RXHDR_LEN_REV_LT80)
-
-#define FRAMELEN(corerev, corerev_minor, rxh) \
- D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxFrameSize)
-
-#define RXS_SHORT_MASK 0x01 /**< Short vs full rx status in dma_flags field of d11rxhdr */
-
-/** validate chip specific phychain info for MCSSQ snr.
- * should sync with uCode reporting.
- * please add a condition with decending order to avoid any wrong skip
- * Note: this macro can be removed once NEWT no longer needs 4368a0.
- */
-#define IS_MCSSQ_ANT3_VALID_GE80(corerev, corerev_minor) \
- (D11REV_IS(corerev, 83) && (D11MINORREV_IS(corerev_minor, 1)))
-
-/* Header conversion status register bit fields */
-#define HDRCONV_USR_ENAB 0x0001
-#define HDRCONV_ENAB 0x0100
-#define HDRCONV_ETH_FRAME 0x0200
-#define HDRCONV_STATUS_VALID 0x8000
-
-#define ROE_L3_PROT_TYPE_IPV4 (0x10u)
-#define ROE_L3_PROT_TYPE_IPV6 (0x20u)
-#define ROE_L3_PROT_TYPE_MASK (0x30u)
-#define ROE_L3_PROT_TYPE_SHIFT (4u)
-
-#define ROE_L4_PROT_TYPE_TCP (0x40u)
-#define ROE_L4_PROT_TYPE_UDP (0x80u)
-#define ROE_L4_PROT_TYPE_MASK (0xC0u)
-#define ROE_L4_PROT_TYPE_SHIFT (6u)
-
-#define ROE_L3_CHKSUM_STATUS_FAIL (0x100u)
-#define ROE_L3_CHKSUM_STATUS_SUCCESS (0x200u)
-#define ROE_L3_CHKSUM_STATUS_MASK (0x300u)
-#define ROE_L3_CHKSUM_STATUS_SHIFT (8u)
-
-#define ROE_L4_CHKSUM_STATUS_FAIL (0x400u)
-#define ROE_L4_CHKSUM_STATUS_SUCCESS (0x800u)
-#define ROE_L4_CHKSUM_STATUS_MASK (0xC00u)
-#define ROE_L4_CHKSUM_STATUS_SHIFT (10u)
-
-/** NOTE: Due to precommit issue, _d11_autophyrxsts_ will be moved
- * to a separated file when 4387 trunk build is stable
- */
-#ifndef _d11_autophyrxsts_
-#define _d11_autophyrxsts_
-
-#define APRXS_WD0_L_EN_GE85 1u
-#define APRXS_WD0_H_EN_GE85 1u
-#define APRXS_WD1_L_EN_GE85 1u
-#define APRXS_WD1_H_EN_GE85 1u
-#define APRXS_WD2_L_EN_GE85 1u
-#define APRXS_WD2_H_EN_GE85 1u
-#define APRXS_WD3_L_EN_GE85 1u
-#define APRXS_WD3_H_EN_GE85 0u // DO NOT ENABLE WD3_H
-#define APRXS_WD4_L_EN_GE85 1u
-#define APRXS_WD4_H_EN_GE85 1u
-#define APRXS_WD5_L_EN_GE85 1u
-#define APRXS_WD5_H_EN_GE85 1u
-#define APRXS_WD6_L_EN_GE85 0u
-#define APRXS_WD6_H_EN_GE85 0u
-#define APRXS_WD7_L_EN_GE85 0u
-#define APRXS_WD7_H_EN_GE85 0u
-#define APRXS_WD8_L_EN_GE85 0u
-#define APRXS_WD8_H_EN_GE85 1u
-#define APRXS_WD9_L_EN_GE85 0u
-#define APRXS_WD9_H_EN_GE85 0u
-#define APRXS_WD10_L_EN_GE85 0u
-#define APRXS_WD10_H_EN_GE85 0u
-#define APRXS_WD11_L_EN_GE85 0u
-#define APRXS_WD11_H_EN_GE85 0u
-#define APRXS_WD12_L_EN_GE85 0u
-#define APRXS_WD12_H_EN_GE85 0u
-#define APRXS_WD13_L_EN_GE85 0u
-#define APRXS_WD13_H_EN_GE85 0u
-#define APRXS_WD14_L_EN_GE85 0u
-#define APRXS_WD14_H_EN_GE85 0u
-#define APRXS_WD15_L_EN_GE85 0u
-#define APRXS_WD15_H_EN_GE85 0u
-#define APRXS_WD16_L_EN_GE85 1u
-#define APRXS_WD16_H_EN_GE85 0u
-#define APRXS_WD17_L_EN_GE85 0u
-#define APRXS_WD17_H_EN_GE85 0u
-#define APRXS_WD18_L_EN_GE85 1u
-#define APRXS_WD18_H_EN_GE85 0u
-#define APRXS_WD19_L_EN_GE85 0u
-#define APRXS_WD19_H_EN_GE85 0u
-#define APRXS_WD20_L_EN_GE85 1u
-#define APRXS_WD20_H_EN_GE85 1u
-#define APRXS_WD21_L_EN_GE85 0u
-#define APRXS_WD21_H_EN_GE85 1u
-#define APRXS_WD22_L_EN_GE85 1u
-#define APRXS_WD22_H_EN_GE85 1u
-#define APRXS_WD23_L_EN_GE85 1u
-#define APRXS_WD23_H_EN_GE85 1u
-#define APRXS_WD24_L_EN_GE85 0u
-#define APRXS_WD24_H_EN_GE85 0u
-#define APRXS_WD25_L_EN_GE85 0u
-#define APRXS_WD25_H_EN_GE85 0u
-
-enum {
- APRXS_WD0_L_SHIFT = 0, // frameType, unsupportedRate, band, lostCRS, shortPreamble
- APRXS_WD0_H_SHIFT, // PLCPViolation, MFCRSFired, ACCRSFired, MUPPDU, OBSSStat
- APRXS_WD1_L_SHIFT, // coremask, antcfg,
- APRXS_WD1_H_SHIFT, // BWclassification
- APRXS_WD2_L_SHIFT, // RxPwrAnt0
- APRXS_WD2_H_SHIFT, // RxPwrAnt1
- APRXS_WD3_L_SHIFT, // RxPwrAnt2
- APRXS_WD3_H_SHIFT, // RxPwrAnt3, OCL
- APRXS_WD4_L_SHIFT, // RSSI factional bit
- APRXS_WD4_H_SHIFT, // AGC type, ACI mitigation state, ClipCount, DynBWInNonHT
- APRXS_WD5_L_SHIFT, // MCSSQSNRCore0
- APRXS_WD5_H_SHIFT, // MCSSQSNRCore1
- APRXS_WD6_L_SHIFT, // MCSSQSNRCore2
- APRXS_WD6_H_SHIFT, // MCSSQSNRCore3, OCL 1
- APRXS_WD7_L_SHIFT, // MUIntProcessType,
- APRXS_WD7_H_SHIFT, // coarse freq_offset, packet abort
- APRXS_WD8_L_SHIFT = 0, // fine freq offset
- APRXS_WD8_H_SHIFT, // ChBWInNonHT, MLUsed, SINRBasedACIDet
- APRXS_WD9_L_SHIFT, // SpatialSQCnt
- APRXS_WD9_H_SHIFT, // packet gain
- APRXS_WD10_L_SHIFT, // RxPwrAntExt
- APRXS_WD10_H_SHIFT, // coarse freq_offset of 2nd 80mhz
- APRXS_WD11_L_SHIFT, // fine freq_offset of 2nd 80mhz
- APRXS_WD11_H_SHIFT,
- APRXS_WD12_L_SHIFT,
- APRXS_WD12_H_SHIFT,
- APRXS_WD13_L_SHIFT,
- APRXS_WD13_H_SHIFT,
- APRXS_WD14_L_SHIFT,
- APRXS_WD14_H_SHIFT,
- APRXS_WD15_L_SHIFT,
- APRXS_WD15_H_SHIFT,
- APRXS_WD16_L_SHIFT = 0,
- APRXS_WD16_H_SHIFT,
- APRXS_WD17_L_SHIFT,
- APRXS_WD17_H_SHIFT,
- APRXS_WD18_L_SHIFT,
- APRXS_WD18_H_SHIFT,
- APRXS_WD19_L_SHIFT,
- APRXS_WD19_H_SHIFT,
- APRXS_WD20_L_SHIFT,
- APRXS_WD20_H_SHIFT,
- APRXS_WD21_L_SHIFT,
- APRXS_WD21_H_SHIFT,
- APRXS_WD22_L_SHIFT, // STA ID
- APRXS_WD22_H_SHIFT, // STA ID, NSTS, TXBF, DCM
- APRXS_WD23_L_SHIFT,
- APRXS_WD23_H_SHIFT,
- APRXS_WD24_L_SHIFT = 0,
- APRXS_WD24_H_SHIFT,
- APRXS_WD25_L_SHIFT,
- APRXS_WD25_H_SHIFT
-};
-
-#define APRXS_WD0_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD0_L_EN_GE85 : 0)
-#define APRXS_WD0_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD0_H_EN_GE85 : 0)
-#define APRXS_WD1_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD1_L_EN_GE85 : 0)
-#define APRXS_WD1_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD1_H_EN_GE85 : 0)
-#define APRXS_WD2_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD2_L_EN_GE85 : 0)
-#define APRXS_WD2_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD2_H_EN_GE85 : 0)
-#define APRXS_WD3_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD3_L_EN_GE85 : 0)
-#define APRXS_WD3_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD3_H_EN_GE85 : 0)
-#define APRXS_WD4_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD4_L_EN_GE85 : 0)
-#define APRXS_WD4_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD4_H_EN_GE85 : 0)
-#define APRXS_WD5_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD5_L_EN_GE85 : 0)
-#define APRXS_WD5_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD5_H_EN_GE85 : 0)
-#define APRXS_WD6_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD6_L_EN_GE85 : 0)
-#define APRXS_WD6_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD6_H_EN_GE85 : 0)
-#define APRXS_WD7_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD7_L_EN_GE85 : 0)
-#define APRXS_WD7_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD7_H_EN_GE85 : 0)
-#define APRXS_WD8_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD8_L_EN_GE85 : 0)
-#define APRXS_WD8_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD8_H_EN_GE85 : 0)
-#define APRXS_WD9_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD9_L_EN_GE85 : 0)
-#define APRXS_WD9_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD9_H_EN_GE85 : 0)
-#define APRXS_WD10_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD10_L_EN_GE85 : 0)
-#define APRXS_WD10_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD10_H_EN_GE85 : 0)
-#define APRXS_WD11_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD11_L_EN_GE85 : 0)
-#define APRXS_WD11_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD11_H_EN_GE85 : 0)
-#define APRXS_WD12_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD12_L_EN_GE85 : 0)
-#define APRXS_WD12_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD12_H_EN_GE85 : 0)
-#define APRXS_WD13_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD13_L_EN_GE85 : 0)
-#define APRXS_WD13_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD13_H_EN_GE85 : 0)
-#define APRXS_WD14_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD14_L_EN_GE85 : 0)
-#define APRXS_WD14_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD14_H_EN_GE85 : 0)
-#define APRXS_WD15_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD15_L_EN_GE85 : 0)
-#define APRXS_WD15_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD15_H_EN_GE85 : 0)
-#define APRXS_WD16_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD16_L_EN_GE85 : 0)
-#define APRXS_WD16_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD16_H_EN_GE85 : 0)
-#define APRXS_WD17_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD17_L_EN_GE85 : 0)
-#define APRXS_WD17_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD17_H_EN_GE85 : 0)
-#define APRXS_WD18_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD18_L_EN_GE85 : 0)
-#define APRXS_WD18_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD18_H_EN_GE85 : 0)
-#define APRXS_WD19_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD19_L_EN_GE85 : 0)
-#define APRXS_WD19_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD19_H_EN_GE85 : 0)
-#define APRXS_WD20_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD20_L_EN_GE85 : 0)
-#define APRXS_WD20_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD20_H_EN_GE85 : 0)
-#define APRXS_WD21_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD21_L_EN_GE85 : 0)
-#define APRXS_WD21_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD21_H_EN_GE85 : 0)
-#define APRXS_WD22_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD22_L_EN_GE85 : 0)
-#define APRXS_WD22_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD22_H_EN_GE85 : 0)
-#define APRXS_WD23_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD23_L_EN_GE85 : 0)
-#define APRXS_WD23_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD23_H_EN_GE85 : 0)
-#define APRXS_WD24_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD24_L_EN_GE85 : 0)
-#define APRXS_WD24_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD24_H_EN_GE85 : 0)
-#define APRXS_WD25_L_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD25_L_EN_GE85 : 0)
-#define APRXS_WD25_H_EN(rev) ((D11REV_GE(rev, 85)) ? \
- APRXS_WD25_H_EN_GE85 : 0)
-
-#define APRXS_BMAP0(rev) ((APRXS_WD0_L_EN(rev) << APRXS_WD0_L_SHIFT) | \
- (APRXS_WD0_H_EN(rev) << APRXS_WD0_H_SHIFT) |\
- (APRXS_WD1_L_EN(rev) << APRXS_WD1_L_SHIFT) |\
- (APRXS_WD1_H_EN(rev) << APRXS_WD1_H_SHIFT) |\
- (APRXS_WD2_L_EN(rev) << APRXS_WD2_L_SHIFT) |\
- (APRXS_WD2_H_EN(rev) << APRXS_WD2_H_SHIFT) |\
- (APRXS_WD3_L_EN(rev) << APRXS_WD3_L_SHIFT) |\
- (APRXS_WD3_H_EN(rev) << APRXS_WD3_H_SHIFT) |\
- (APRXS_WD4_L_EN(rev) << APRXS_WD4_L_SHIFT) |\
- (APRXS_WD4_H_EN(rev) << APRXS_WD4_H_SHIFT) |\
- (APRXS_WD5_L_EN(rev) << APRXS_WD5_L_SHIFT) |\
- (APRXS_WD5_H_EN(rev) << APRXS_WD5_H_SHIFT) |\
- (APRXS_WD6_L_EN(rev) << APRXS_WD6_L_SHIFT) |\
- (APRXS_WD6_H_EN(rev) << APRXS_WD6_H_SHIFT) |\
- (APRXS_WD7_L_EN(rev) << APRXS_WD7_L_SHIFT) |\
- (APRXS_WD7_H_EN(rev) << APRXS_WD7_H_SHIFT))
-
-#define APRXS_BMAP1(rev) ((APRXS_WD8_L_EN(rev) << APRXS_WD8_L_SHIFT) | \
- (APRXS_WD8_H_EN(rev) << APRXS_WD8_H_SHIFT) |\
- (APRXS_WD9_L_EN(rev) << APRXS_WD9_L_SHIFT) |\
- (APRXS_WD9_H_EN(rev) << APRXS_WD9_H_SHIFT) |\
- (APRXS_WD10_L_EN(rev) << APRXS_WD10_L_SHIFT) |\
- (APRXS_WD10_H_EN(rev) << APRXS_WD10_H_SHIFT) |\
- (APRXS_WD11_L_EN(rev) << APRXS_WD11_L_SHIFT) |\
- (APRXS_WD11_H_EN(rev) << APRXS_WD11_H_SHIFT) |\
- (APRXS_WD12_L_EN(rev) << APRXS_WD12_L_SHIFT) |\
- (APRXS_WD12_H_EN(rev) << APRXS_WD12_H_SHIFT) |\
- (APRXS_WD13_L_EN(rev) << APRXS_WD13_L_SHIFT) |\
- (APRXS_WD13_H_EN(rev) << APRXS_WD13_H_SHIFT) |\
- (APRXS_WD14_L_EN(rev) << APRXS_WD14_L_SHIFT) |\
- (APRXS_WD14_H_EN(rev) << APRXS_WD14_H_SHIFT) |\
- (APRXS_WD15_L_EN(rev) << APRXS_WD15_L_SHIFT) |\
- (APRXS_WD15_H_EN(rev) << APRXS_WD15_H_SHIFT))
-
-#define APRXS_BMAP2(rev) ((APRXS_WD16_L_EN(rev) << APRXS_WD16_L_SHIFT) | \
- (APRXS_WD16_H_EN(rev) << APRXS_WD16_H_SHIFT) |\
- (APRXS_WD17_L_EN(rev) << APRXS_WD17_L_SHIFT) |\
- (APRXS_WD17_H_EN(rev) << APRXS_WD17_H_SHIFT) |\
- (APRXS_WD18_L_EN(rev) << APRXS_WD18_L_SHIFT) |\
- (APRXS_WD18_H_EN(rev) << APRXS_WD18_H_SHIFT) |\
- (APRXS_WD19_L_EN(rev) << APRXS_WD19_L_SHIFT) |\
- (APRXS_WD19_H_EN(rev) << APRXS_WD19_H_SHIFT) |\
- (APRXS_WD20_L_EN(rev) << APRXS_WD20_L_SHIFT) |\
- (APRXS_WD20_H_EN(rev) << APRXS_WD20_H_SHIFT) |\
- (APRXS_WD21_L_EN(rev) << APRXS_WD21_L_SHIFT) |\
- (APRXS_WD21_H_EN(rev) << APRXS_WD21_H_SHIFT) |\
- (APRXS_WD22_L_EN(rev) << APRXS_WD22_L_SHIFT) |\
- (APRXS_WD22_H_EN(rev) << APRXS_WD22_H_SHIFT) |\
- (APRXS_WD23_L_EN(rev) << APRXS_WD23_L_SHIFT) |\
- (APRXS_WD23_H_EN(rev) << APRXS_WD23_H_SHIFT))
-
-#define APRXS_BMAP3(rev) ((APRXS_WD24_L_EN(rev) << APRXS_WD24_L_SHIFT) | \
- (APRXS_WD24_H_EN(rev) << APRXS_WD24_H_SHIFT) |\
- (APRXS_WD25_L_EN(rev) << APRXS_WD25_L_SHIFT) |\
- (APRXS_WD25_H_EN(rev) << APRXS_WD25_H_SHIFT))
-/* byte position */
-#define APRXS_WD0_L_POS(rev) 0u
-#define APRXS_WD0_H_POS(rev) (APRXS_WD0_L_POS(rev) + APRXS_WD0_L_EN(rev)) /* 1 */
-#define APRXS_WD1_L_POS(rev) (APRXS_WD0_H_POS(rev) + APRXS_WD0_H_EN(rev)) /* 2 */
-#define APRXS_WD1_H_POS(rev) (APRXS_WD1_L_POS(rev) + APRXS_WD1_L_EN(rev)) /* 3 */
-#define APRXS_WD2_L_POS(rev) (APRXS_WD1_H_POS(rev) + APRXS_WD1_H_EN(rev)) /* 4 */
-#define APRXS_WD2_H_POS(rev) (APRXS_WD2_L_POS(rev) + APRXS_WD2_L_EN(rev)) /* 5 */
-#define APRXS_WD3_L_POS(rev) (APRXS_WD2_H_POS(rev) + APRXS_WD2_H_EN(rev)) /* 6 */
-#define APRXS_WD3_H_POS(rev) (APRXS_WD3_L_POS(rev) + APRXS_WD3_L_EN(rev)) /* 7 */
-#define APRXS_WD4_L_POS(rev) (APRXS_WD3_H_POS(rev) + APRXS_WD3_H_EN(rev)) /* 7 */
-#define APRXS_WD4_H_POS(rev) (APRXS_WD4_L_POS(rev) + APRXS_WD4_L_EN(rev)) /* 8 */
-#define APRXS_WD5_L_POS(rev) (APRXS_WD4_H_POS(rev) + APRXS_WD4_H_EN(rev)) /* 9 */
-#define APRXS_WD5_H_POS(rev) (APRXS_WD5_L_POS(rev) + APRXS_WD5_L_EN(rev)) /* 10 */
-#define APRXS_WD6_L_POS(rev) (APRXS_WD5_H_POS(rev) + APRXS_WD5_H_EN(rev)) /* 11 */
-#define APRXS_WD6_H_POS(rev) (APRXS_WD6_L_POS(rev) + APRXS_WD6_L_EN(rev)) /* 11 */
-#define APRXS_WD7_L_POS(rev) (APRXS_WD6_H_POS(rev) + APRXS_WD6_H_EN(rev)) /* 11 */
-#define APRXS_WD7_H_POS(rev) (APRXS_WD7_L_POS(rev) + APRXS_WD7_L_EN(rev)) /* 11 */
-#define APRXS_WD8_L_POS(rev) (APRXS_WD7_H_POS(rev) + APRXS_WD7_H_EN(rev)) /* 11 */
-#define APRXS_WD8_H_POS(rev) (APRXS_WD8_L_POS(rev) + APRXS_WD8_L_EN(rev)) /* 11 */
-#define APRXS_WD9_L_POS(rev) (APRXS_WD8_H_POS(rev) + APRXS_WD8_H_EN(rev)) /* 12 */
-#define APRXS_WD9_H_POS(rev) (APRXS_WD9_L_POS(rev) + APRXS_WD9_L_EN(rev)) /* 12 */
-#define APRXS_WD10_L_POS(rev) (APRXS_WD9_H_POS(rev) + APRXS_WD9_H_EN(rev)) /* 12 */
-#define APRXS_WD10_H_POS(rev) (APRXS_WD10_L_POS(rev) + APRXS_WD10_L_EN(rev)) /* 12 */
-#define APRXS_WD11_L_POS(rev) (APRXS_WD10_H_POS(rev) + APRXS_WD10_H_EN(rev)) /* 12 */
-#define APRXS_WD11_H_POS(rev) (APRXS_WD11_L_POS(rev) + APRXS_WD11_L_EN(rev)) /* 12 */
-#define APRXS_WD12_L_POS(rev) (APRXS_WD11_H_POS(rev) + APRXS_WD11_H_EN(rev)) /* 12 */
-#define APRXS_WD12_H_POS(rev) (APRXS_WD12_L_POS(rev) + APRXS_WD12_L_EN(rev)) /* 12 */
-#define APRXS_WD13_L_POS(rev) (APRXS_WD12_H_POS(rev) + APRXS_WD12_H_EN(rev)) /* 12 */
-#define APRXS_WD13_H_POS(rev) (APRXS_WD13_L_POS(rev) + APRXS_WD13_L_EN(rev)) /* 12 */
-#define APRXS_WD14_L_POS(rev) (APRXS_WD13_H_POS(rev) + APRXS_WD13_H_EN(rev)) /* 12 */
-#define APRXS_WD14_H_POS(rev) (APRXS_WD14_L_POS(rev) + APRXS_WD14_L_EN(rev)) /* 12 */
-#define APRXS_WD15_L_POS(rev) (APRXS_WD14_H_POS(rev) + APRXS_WD14_H_EN(rev)) /* 12 */
-#define APRXS_WD15_H_POS(rev) (APRXS_WD15_L_POS(rev) + APRXS_WD15_L_EN(rev)) /* 12 */
-#define APRXS_WD16_L_POS(rev) (APRXS_WD15_H_POS(rev) + APRXS_WD15_H_EN(rev)) /* 12 */
-#define APRXS_WD16_H_POS(rev) (APRXS_WD16_L_POS(rev) + APRXS_WD16_L_EN(rev)) /* 13 */
-#define APRXS_WD17_L_POS(rev) (APRXS_WD16_H_POS(rev) + APRXS_WD16_H_EN(rev)) /* 13 */
-#define APRXS_WD17_H_POS(rev) (APRXS_WD17_L_POS(rev) + APRXS_WD17_L_EN(rev)) /* 13 */
-#define APRXS_WD18_L_POS(rev) (APRXS_WD17_H_POS(rev) + APRXS_WD17_H_EN(rev)) /* 13 */
-#define APRXS_WD18_H_POS(rev) (APRXS_WD18_L_POS(rev) + APRXS_WD18_L_EN(rev)) /* 14 */
-#define APRXS_WD19_L_POS(rev) (APRXS_WD18_H_POS(rev) + APRXS_WD18_H_EN(rev)) /* 14 */
-#define APRXS_WD19_H_POS(rev) (APRXS_WD19_L_POS(rev) + APRXS_WD19_L_EN(rev)) /* 14 */
-#define APRXS_WD20_L_POS(rev) (APRXS_WD19_H_POS(rev) + APRXS_WD19_H_EN(rev)) /* 14 */
-#define APRXS_WD20_H_POS(rev) (APRXS_WD20_L_POS(rev) + APRXS_WD20_L_EN(rev)) /* 15 */
-#define APRXS_WD21_L_POS(rev) (APRXS_WD20_H_POS(rev) + APRXS_WD20_H_EN(rev)) /* 16 */
-#define APRXS_WD21_H_POS(rev) (APRXS_WD21_L_POS(rev) + APRXS_WD21_L_EN(rev)) /* 16 */
-#define APRXS_WD22_L_POS(rev) (APRXS_WD21_H_POS(rev) + APRXS_WD21_H_EN(rev)) /* 17 */
-#define APRXS_WD22_H_POS(rev) (APRXS_WD22_L_POS(rev) + APRXS_WD22_L_EN(rev)) /* 18 */
-#define APRXS_WD23_L_POS(rev) (APRXS_WD22_H_POS(rev) + APRXS_WD22_H_EN(rev)) /* 19 */
-#define APRXS_WD23_H_POS(rev) (APRXS_WD23_L_POS(rev) + APRXS_WD23_L_EN(rev)) /* 20 */
-#define APRXS_WD24_L_POS(rev) (APRXS_WD23_H_POS(rev) + APRXS_WD23_H_EN(rev)) /* 21 */
-#define APRXS_WD24_H_POS(rev) (APRXS_WD24_L_POS(rev) + APRXS_WD24_L_EN(rev)) /* 21 */
-#define APRXS_WD25_L_POS(rev) (APRXS_WD24_H_POS(rev) + APRXS_WD24_H_EN(rev)) /* 22 */
-#define APRXS_WD25_H_POS(rev) (APRXS_WD25_L_POS(rev) + APRXS_WD25_L_EN(rev)) /* 23 */
-
-#define APRXS_NBYTES(rev) (APRXS_WD25_H_POS(rev)) // total number of bytes enabled
-
-// frame type
-#define APRXS_FT_POS(rev) APRXS_WD0_L_POS(rev)
-#define APRXS_FT_MASK 0xFu
-#define APRXS_FT(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_FT_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_FT_POS(rev)]) & \
- APRXS_FT_MASK)
-
-// unsupported rate
-#define APRXS_UNSRATE_POS(rev) APRXS_WD0_L_POS(rev)
-#define APRXS_UNSRATE_MASK 0x10u
-#define APRXS_UNSRATE_SHIFT 4u
-#define APRXS_UNSRATE(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_UNSRATE_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_UNSRATE_POS(rev)]) & \
- APRXS_UNSRATE_MASK) >> APRXS_UNSRATE_SHIFT)
-
-// band
-#define APRXS_BAND_POS(rev) APRXS_WD0_L_POS(rev)
-#define APRXS_BAND_MASK 0x20u
-#define APRXS_BAND_SHIFT 5u
-#define APRXS_BAND(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_BAND_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_BAND_POS(rev)]) & \
- APRXS_BAND_MASK) >> APRXS_BAND_SHIFT)
-
-// lost CRS
-#define APRXS_LOSTCRS_POS(rev) APRXS_WD0_L_POS(rev)
-#define APRXS_LOSTCRS_MASK 0x40u
-#define APRXS_LOSTCRS_SHIFT 6u
-#define APRXS_LOSTCRS(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_LOSTCRS_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_LOSTCRS_POS(rev)]) & \
- APRXS_LOSTCRS_MASK) >> APRXS_LOSTCRS_SHIFT)
-
-// short preamble
-#define APRXS_SHORTH_POS(rev) APRXS_WD0_L_POS(rev)
-#define APRXS_SHORTH_MASK 0x80u
-#define APRXS_SHORTH_SHIFT 7u
-#define APRXS_SHORTH(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_SHORTH_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_SHORTH_POS(rev)]) & \
- APRXS_SHORTH_MASK) >> APRXS_SHORTH_SHIFT)
-
-// plcp format violation
-#define APRXS_PLCPFV_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_PLCPFV_MASK 0x1u
-#define APRXS_PLCPFV(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_PLCPFV_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_PLCPFV_POS(rev)]) & \
- APRXS_PLCPFV_MASK)
-
-// plcp header CRC failed
-#define APRXS_PLCPHCF_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_PLCPHCF_MASK 0x2u
-#define APRXS_PLCPHCF_SHIFT 1u
-#define APRXS_PLCPHCF(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_PLCPHCF_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_PLCPHCF_POS(rev)]) & \
- APRXS_PLCPHCF_MASK) >> APRXS_PLCPHCF_SHIFT)
-
-// MFCRS fired
-#define APRXS_MFCRS_FIRED_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_MFCRS_FIRED_MASK 0x4u
-#define APRXS_MFCRS_FIRED_SHIFT 2u
-#define APRXS_MFCRS_FIRED(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_MFCRS_FIRED_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_MFCRS_FIRED_POS(rev)]) & \
- APRXS_MFCRS_FIRED_MASK) >> APRXS_MFCRS_FIRED_SHIFT)
-
-// ACCRS fired
-#define APRXS_ACCRS_FIRED_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_ACCRS_FIRED_MASK 0x8u
-#define APRXS_ACCRS_FIRED_SHIFT 3u
-#define APRXS_ACCRS_FIRED(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_ACCRS_FIRED_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_ACCRS_FIRED_POS(rev)]) & \
- APRXS_ACCRS_FIRED_MASK) >> APRXS_ACCRS_FIRED_SHIFT)
-
-// MU PPDU
-#define APRXS_MUPPDU_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_MUPPDU_MASK 0x10u
-#define APRXS_MUPPDU_SHIFT 4u
-#define APRXS_MUPPDU(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_MUPPDU_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_MUPPDU_POS(rev)]) & \
- APRXS_MUPPDU_MASK) >> APRXS_MUPPDU_SHIFT)
-
-// OBSS status
-#define APRXS_OBSS_STS_POS(rev) APRXS_WD0_H_POS(rev)
-#define APRXS_OBSS_STS_MASK 0xE0u
-#define APRXS_OBSS_STS_SHIFT 5u
-#define APRXS_OBSS_STS(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_OBSS_STS_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_OBSS_STS_POS(rev)]) & \
- APRXS_OBSS_STS_MASK) >> APRXS_OBSS_STS_SHIFT)
-
-// coremask
-#define APRXS_COREMASK_POS(rev) APRXS_WD1_L_POS(rev)
-#define APRXS_COREMASK_MASK 0xFu
-#define APRXS_COREMASK(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_COREMASK_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_COREMASK_POS(rev)]) & \
- APRXS_COREMASK_MASK)
-
-// antcfg
-#define APRXS_ANTCFG_POS(rev) APRXS_WD1_L_POS(rev)
-#define APRXS_ANTCFG_MASK 0xF0u
-#define APRXS_ANTCFG_SHIFT 4u
-#define APRXS_ANTCFG(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_ANTCFG_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_ANTCFG_POS(rev)]) & \
- APRXS_ANTCFG_MASK) >> APRXS_ANTCFG_SHIFT)
-
-// final BW classification
-#define APRXS_SUBBAND_POS(rev) APRXS_WD1_H_POS(rev)
-#define APRXS_SUBBAND_MASK 0xFFu
-#define APRXS_SUBBAND(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_SUBBAND_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_SUBBAND_POS(rev)]) & \
- APRXS_SUBBAND_MASK)
-
-// Rx power Antenna0
-#define APRXS_RXPWR_ANT0_POS(rev) APRXS_WD2_L_POS(rev)
-#define APRXS_RXPWR_ANT0_MASK 0xFFu
-#define APRXS_RXPWR_ANT0(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT0_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT0_POS(rev)]) & \
- APRXS_RXPWR_ANT0_MASK)
-
-// Rx power Antenna1
-#define APRXS_RXPWR_ANT1_POS(rev) APRXS_WD2_H_POS(rev)
-#define APRXS_RXPWR_ANT1_MASK 0xFFu
-#define APRXS_RXPWR_ANT1(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT1_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT1_POS(rev)]) & \
- APRXS_RXPWR_ANT1_MASK)
-
-// Rx power Antenna2
-#define APRXS_RXPWR_ANT2_POS(rev) APRXS_WD3_L_POS(rev)
-#define APRXS_RXPWR_ANT2_MASK 0xFFu
-#define APRXS_RXPWR_ANT2(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT2_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT2_POS(rev)]) & \
- APRXS_RXPWR_ANT2_MASK)
-
-// Rx power Antenna3
-#define APRXS_RXPWR_ANT3_POS(rev) APRXS_WD3_H_POS(rev)
-#define APRXS_RXPWR_ANT3_MASK 0xFFu
-#define APRXS_RXPWR_ANT3(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT3_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT3_POS(rev)]) & \
- APRXS_RXPWR_ANT3_MASK)
-
-// RX ELNA INDEX ANT0
-#define APRXS_ELNA_IDX_ANT0_POS(rev) APRXS_WD20_L_POS(rev)
-#define APRXS_ELNA_IDX_ANT0_MASK 0x2u
-#define APRXS_ELNA_IDX_ANT0_SHIFT 1u
-#define APRXS_ELNA_IDX_ANT0(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_ELNA_IDX_ANT0_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_ELNA_IDX_ANT0_POS(rev)]) & \
- APRXS_ELNA_IDX_ANT0_MASK) >> APRXS_ELNA_IDX_ANT0_SHIFT)
-
-// RX ELNA INDEX ANT1
-#define APRXS_ELNA_IDX_ANT1_POS(rev) APRXS_WD20_L_POS(rev)
-#define APRXS_ELNA_IDX_ANT1_MASK 0x20u
-#define APRXS_ELNA_IDX_ANT1_SHIFT 5u
-#define APRXS_ELNA_IDX_ANT1(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_ELNA_IDX_ANT1_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_ELNA_IDX_ANT1_POS(rev)]) & \
- APRXS_ELNA_IDX_ANT1_MASK) >> APRXS_ELNA_IDX_ANT1_SHIFT)
-
-// RX TIA INDEX ANT0 LO
-#define APRXS_TIA_IDX_ANT0_POS(rev) APRXS_WD16_L_POS(rev)
-#define APRXS_TIA_IDX_ANT0_MASK 0x1Cu
-#define APRXS_TIA_IDX_ANT0_SHIFT 2u
-#define APRXS_TIA_IDX_ANT0(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_TIA_IDX_ANT0_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_TIA_IDX_ANT0_POS(rev)]) & \
- APRXS_TIA_IDX_ANT0_MASK) >> APRXS_TIA_IDX_ANT0_SHIFT)
-
-// RX TIA INDEX ANT1 LO
-#define APRXS_TIA_IDX_ANT1_POS(rev) APRXS_WD18_L_POS(rev)
-#define APRXS_TIA_IDX_ANT1_MASK 0x1Cu
-#define APRXS_TIA_IDX_ANT1_SHIFT 2u
-#define APRXS_TIA_IDX_ANT1(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_TIA_IDX_ANT1_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_TIA_IDX_ANT1_POS(rev)]) & \
- APRXS_TIA_IDX_ANT1_MASK) >> APRXS_TIA_IDX_ANT1_SHIFT)
-
-// RX VSW INDEX ANT0
-#define APRXS_VSW_IDX_ANT0_POS(rev) APRXS_WD20_L_POS(rev)
-#define APRXS_VSW_IDX_ANT0_MASK 0x8u
-#define APRXS_VSW_IDX_ANT0_SHIFT 3u
-#define APRXS_VSW_IDX_ANT0(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_VSW_IDX_ANT0_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_VSW_IDX_ANT0_POS(rev)]) & \
- APRXS_VSW_IDX_ANT0_MASK) >> APRXS_VSW_IDX_ANT0_SHIFT)
-
-// RX VSW INDEX ANT1
-#define APRXS_VSW_IDX_ANT1_POS(rev) APRXS_WD20_L_POS(rev)
-#define APRXS_VSW_IDX_ANT1_MASK 0x80u
-#define APRXS_VSW_IDX_ANT1_SHIFT 7u
-#define APRXS_VSW_IDX_ANT1(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_VSW_IDX_ANT1_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_VSW_IDX_ANT1_POS(rev)]) & \
- APRXS_VSW_IDX_ANT1_MASK) >> APRXS_VSW_IDX_ANT1_SHIFT)
-
-// RSSI fractional bits
-#define APRXS_RXPWR_FRAC_POS(rev) APRXS_WD4_L_POS(rev)
-#define APRXS_RXPWR_FRAC_MASK 0xFFu
-#define APRXS_RXPWR_FRAC(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_FRAC_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_FRAC_POS(rev)]) & \
- APRXS_RXPWR_FRAC_MASK)
-
-// Ucode overwrites ClipCount with GILTF
-#define APRXS_GILTF_POS(rev) APRXS_WD4_H_POS(rev)
-#define APRXS_GILTF_MASK 0x18u
-#define APRXS_GILTF_SHIFT 3u
-#define APRXS_GILTF(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_GILTF_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_GILTF_POS(rev)]) & \
- APRXS_GILTF_MASK) >> APRXS_GILTF_SHIFT)
-
-#define APRXS_DYNBWINNONHT_POS(rev) APRXS_WD4_H_POS(rev)
-#define APRXS_DYNBWINNONHT_MASK 0x20u
-#define APRXS_DYNBWINNONHT_SHIFT 5u
-#define APRXS_DYNBWINNONHT(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_DYNBWINNONHT_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_DYNBWINNONHT_POS(rev)]) & \
- APRXS_DYNBWINNONHT_MASK) >> APRXS_DYNBWINNONHT_SHIFT)
-
-#define APRXS_MCSSQSNR0_POS(rev) APRXS_WD5_L_POS(rev)
-#define APRXS_MCSSQSNR0_MASK 0xFFu
-#define APRXS_MCSSQSNR0(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR0_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR0_POS(rev)]) & \
- APRXS_MCSSQSNR0_MASK)
-
-#define APRXS_MCSSQSNR1_POS(rev) APRXS_WD5_H_POS(rev)
-#define APRXS_MCSSQSNR1_MASK 0xFFu
-#define APRXS_MCSSQSNR1(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR1_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR1_POS(rev)]) & \
- APRXS_MCSSQSNR1_MASK)
-
-#define APRXS_MCSSQSNR2_POS(rev) APRXS_WD6_L_POS(rev)
-#define APRXS_MCSSQSNR2_MASK 0xFFu
-#define APRXS_MCSSQSNR2(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR2_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR2_POS(rev)]) & \
- APRXS_MCSSQSNR2_MASK)
-
-#define APRXS_CHBWINNONHT_POS(rev) APRXS_WD8_H_POS(rev)
-#define APRXS_CHBWINNONHT_MASK 0x3u
-#define APRXS_CHBWINNONHT(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_CHBWINNONHT_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_CHBWINNONHT_POS(rev)]) & \
- APRXS_CHBWINNONHT_MASK)
-
-// User type
-#define APRXS_USTY_POS(rev) APRXS_WD23_H_POS(rev)
-#define APRXS_USTY_MASK 0xE0u
-#define APRXS_USTY_SHIFT 0x5u
-#define APRXS_USTY(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_USTY_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_USTY_POS(rev)]) & \
- APRXS_USTY_MASK) >> APRXS_USTY_SHIFT)
-
-// 11ax frame format
-#define APRXS_AXFF_POS(rev) APRXS_WD20_H_POS(rev)
-#define APRXS_AXFF_MASK 0x7u
-#define APRXS_AXFF(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_AXFF_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_AXFF_POS(rev)]) & \
- APRXS_AXFF_MASK)
-
-// MCS
-#define APRXS_AXMCS_POS(rev) APRXS_WD21_H_POS(rev)
-#define APRXS_AXMCS_MASK 0xFu
-#define APRXS_AXMCS(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_AXMCS_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_AXMCS_POS(rev)]) & \
- APRXS_AXMCS_MASK)
-
-// Coding
-#define APRXS_CODING_POS(rev) APRXS_WD21_H_POS(rev)
-#define APRXS_CODING_MASK 0x10u
-#define APRXS_CODING_SHIFT 4u
-#define APRXS_CODING(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_CODING_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_CODING_POS(rev)]) & \
- APRXS_CODING_MASK) >> APRXS_CODING_SHIFT)
-
-// STAID
-#define APRXS_AX_STAID_L_POS(rev) APRXS_WD22_L_POS(rev)
-#define APRXS_AX_STAID_L_MASK 0xFFu
-#define APRXS_AX_STAID_L(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_STAID_L_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_AX_STAID_L_POS(rev)]) & \
- APRXS_AX_STAID_L_MASK)
-
-#define APRXS_AX_STAID_H_POS(rev) APRXS_WD22_H_POS(rev)
-#define APRXS_AX_STAID_H_MASK 0x03u
-#define APRXS_AX_STAID_H(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_STAID_H_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_AX_STAID_H_POS(rev)]) & \
- APRXS_AX_STAID_H_MASK)
-
-#define APRXS_AX_STAID(rxh, rev, min_rev) ((APRXS_AX_STAID_H(rxh, rev, min_rev) << 1) |\
- APRXS_AX_STAID_L(rxh, rev, min_rev))
-
-// NSTS
-#define APRXS_NSTS_POS(rev) APRXS_WD22_H_POS(rev)
-#define APRXS_NSTS_MASK 0x38u
-#define APRXS_NSTS_SHIFT 3u
-#define APRXS_NSTS(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_DCM_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_DCM_POS(rev)]) & \
- APRXS_NSTS_MASK) >> APRXS_NSTS_SHIFT)
-
-// TXBF
-#define APRXS_TXBF_POS(rev) APRXS_WD22_H_POS(rev)
-#define APRXS_TXBF_MASK 0x40u
-#define APRXS_TXBF_SHIFT 6u
-#define APRXS_TXBF(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_TXBF_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_TXBF_POS(rev)]) & \
- APRXS_TXBF_MASK) >> APRXS_TXBF_SHIFT)
-
-//DCM
-#define APRXS_DCM_POS(rev) APRXS_WD22_H_POS(rev)
-#define APRXS_DCM_MASK 0x80u
-#define APRXS_DCM_SHIFT 7u
-#define APRXS_DCM(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_DCM_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_DCM_POS(rev)]) & \
- APRXS_DCM_MASK) >> APRXS_DCM_SHIFT)
-
-// RU Offset
-#define APRXS_AX_RUALLOC_POS(rev) APRXS_WD23_L_POS(rev)
-#define APRXS_AX_RUALLOC_MASK 0x7Fu
-#define APRXS_AX_RUALLOC_SHIFT 0u
-#define APRXS_AX_RUALLOC(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_RUALLOC_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_AX_RUALLOC_POS(rev)]) & \
- APRXS_AX_RUALLOC_MASK) >> APRXS_AX_RUALLOC_SHIFT)
-
-#define APRXS_PE_L_POS(rev) APRXS_WD23_L_POS(rev)
-#define APRXS_PE_L_MASK 0x80u
-#define APRXS_PE_L_SHIFT 7u
-#define APRXS_PE_L(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_PE_L_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_PE_L_POS(rev)]) & \
- APRXS_PE_L_MASK) >> APRXS_PE_L_SHIFT)
-
-#define APRXS_PE_H_POS(rev) APRXS_WD23_H_POS(rev)
-#define APRXS_PE_H_MASK 0x3u
-#define APRXS_PE_H(rxh, rev, min_rev) \
- ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_PE_H_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_PE_H_POS(rev)]) & \
- APRXS_PE_H_MASK)
-
-#define APRXS_PE(rxh, rev, rev_min) \
- ((APRXS_PE_H(rxh, rev, rev_min) << 1) | APRXS_PE_L(rxh, rev, rev_min))
-
-#define APRXS_RU_POS(rev) APRXS_WD23_H_POS(rev)
-#define APRXS_RU_MASK 0x1Cu
-#define APRXS_RU_SHIFT 2u
-#define APRXS_RU(rxh, rev, min_rev) \
- (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \
- (rxh)->ge87_1.PHYRXSTATUS[APRXS_RU_POS(rev)] : \
- (rxh)->ge85.PHYRXSTATUS[APRXS_RU_POS(rev)]) & \
- APRXS_RU_MASK) >> APRXS_RU_SHIFT)
-
-#endif /* _d11_autophyrxsts_ */
-
-#if defined(AUTO_PHYRXSTS)
-#define AUTO_PHYRXSTS_ENAB() 1u
-#else
-#define AUTO_PHYRXSTS_ENAB() 0u
-#endif /* AUTO_PHYRXSTS */
-
-/* PhyRxStatus_0: */
-#define PRXS0_FT_MASK 0x0003u /**< [PRE-HE] NPHY only: CCK, OFDM, HT, VHT */
-#define PRXS0_CLIP_MASK 0x000Cu /**< NPHY only: clip count adjustment steps by AGC */
-#define PRXS0_CLIP_SHIFT 2u /**< SHIFT bits for clip count adjustment */
-#define PRXS0_UNSRATE 0x0010u /**< PHY received a frame with unsupported rate */
-#define PRXS0_UNSRATE_SHIFT 4u
-#define PRXS0_RXANT_UPSUBBAND 0x0020u /**< GPHY: rx ant, NPHY: upper sideband */
-#define PRXS0_LCRS 0x0040u /**< CCK frame only: lost crs during cck frame reception */
-#define PRXS0_SHORTH 0x0080u /**< Short Preamble */
-#define PRXS0_SHORTH_SHIFT 7u
-#define PRXS0_PLCPFV 0x0100u /**< PLCP violation */
-#define PRXS0_PLCPFV_SHIFT 8u
-#define PRXS0_PLCPHCF 0x0200u /**< PLCP header integrity check failed */
-#define PRXS0_PLCPHCF_SHIFT 9u
-#define PRXS0_GAIN_CTL 0x4000u /**< legacy PHY gain control */
-#define PRXS0_ANTSEL_MASK 0xF000u /**< NPHY: Antennas used for received frame, bitmask */
-#define PRXS0_ANTSEL_SHIFT 12u /**< SHIFT bits for Antennas used for received frame */
-#define PRXS0_PPDU_MASK 0x1000u /**< PPDU type SU/MU */
-
-/* subfield PRXS0_FT_MASK [PRXS0_PRE_HE_FT_MASK] */
-#define PRXS0_CCK 0x0000u
-#define PRXS0_OFDM 0x0001u /**< valid only for G phy, use rxh->RxChan for A phy */
-#define PRXS0_PREN 0x0002u
-#define PRXS0_STDN 0x0003u
-
-/* subfield PRXS0_ANTSEL_MASK */
-#define PRXS0_ANTSEL_0 0x0u /**< antenna 0 is used */
-#define PRXS0_ANTSEL_1 0x2u /**< antenna 1 is used */
-#define PRXS0_ANTSEL_2 0x4u /**< antenna 2 is used */
-#define PRXS0_ANTSEL_3 0x8u /**< antenna 3 is used */
-
-/* PhyRxStatus_1: */
-#define PRXS1_JSSI_MASK 0x00FFu
-#define PRXS1_JSSI_SHIFT 0u
-#define PRXS1_SQ_MASK 0xFF00u
-#define PRXS1_SQ_SHIFT 8u
-#define PRXS1_COREMAP 0x000Fu /**< core enable bits for core 0/1/2/3 */
-#define PRXS1_ANTCFG 0x00F0u /**< anttenna configuration bits */
-
-#define PHY_COREMAP_LT85(rxh, rev) \
- ((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & \
- PRXS1_COREMAP)
-#define PHY_COREMAP(rev, rev_min, rxh) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_COREMASK(rxh, rev, rev_min) : PHY_COREMAP_LT85(rxh, rev))
-
-#define PHY_ANTMAP_LT85(rxh, corerev) \
- (((D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & \
- PRXS1_ANTCFG) >> 4)
-#define PHY_ANTMAP(rev, rev_min, rxh) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_ANTCFG(rxh, rev, rev_min) : PHY_ANTMAP_LT85(rxh, rev))
-
-/* nphy PhyRxStatus_1: */
-#define PRXS1_nphy_PWR0_MASK 0x00FF
-#define PRXS1_nphy_PWR1_MASK 0xFF00
-
-/* PhyRxStatus_2: */
-#define PRXS2_LNAGN_MASK 0xC000
-#define PRXS2_LNAGN_SHIFT 14
-#define PRXS2_PGAGN_MASK 0x3C00
-#define PRXS2_PGAGN_SHIFT 10
-#define PRXS2_FOFF_MASK 0x03FF
-
-/* nphy PhyRxStatus_2: */
-#define PRXS2_nphy_SQ_ANT0 0x000F /**< nphy overall signal quality for antenna 0 */
-#define PRXS2_nphy_SQ_ANT1 0x00F0 /**< nphy overall signal quality for antenna 0 */
-#define PRXS2_nphy_cck_SQ 0x00FF /**< bphy signal quality(when FT field is 0) */
-#define PRXS3_nphy_SSQ_MASK 0xFF00 /**< spatial conditioning of the two receive channels */
-#define PRXS3_nphy_SSQ_SHIFT 8
-
-/* PhyRxStatus_3: */
-#define PRXS3_DIGGN_MASK 0x1800
-#define PRXS3_DIGGN_SHIFT 11
-#define PRXS3_TRSTATE 0x0400
-
-/* nphy PhyRxStatus_3: */
-#define PRXS3_nphy_MMPLCPLen_MASK 0x0FFF /**< Mixed-mode preamble PLCP length */
-#define PRXS3_nphy_MMPLCP_RATE_MASK 0xF000 /**< Mixed-mode preamble rate field */
-#define PRXS3_nphy_MMPLCP_RATE_SHIFT 12
-
-/* HTPHY Rx Status defines */
-/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
-#define PRXS0_BAND 0x0400 /**< 0 = 2.4G, 1 = 5G */
-#define PRXS0_RSVD 0x0800 /**< reserved; set to 0 */
-#define PRXS0_UNUSED 0xF000 /**< unused and not defined; set to 0 */
-
-/* htphy PhyRxStatus_1: */
-#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /**< Mixmode PLCP Length low byte mask */
-
-/* htphy PhyRxStatus_2: */
-#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /**< Mixmode PLCP Length high byte maskw */
-#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /**< Mixmode PLCP rate mask */
-#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /**< Rx power on core 0 */
-
-/* htphy PhyRxStatus_3: */
-#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /**< Rx power on core 1 */
-#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /**< Rx power on core 2 */
-
-/* htphy PhyRxStatus_4: */
-#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /**< Rx power on core 3 */
-#define PRXS4_HTPHY_CFO 0xFF00 /**< Coarse frequency offset */
-
-/* htphy PhyRxStatus_5: */
-#define PRXS5_HTPHY_FFO 0x00FF /**< Fine frequency offset */
-#define PRXS5_HTPHY_AR 0xFF00 /**< Advance Retard */
-
-/* ACPHY RxStatus defs */
-
-/* ACPHY PhyRxStatus_0: */
-#define PRXS0_ACPHY_FT_MASK 0x0003 /**< CCK, OFDM, HT, VHT */
-#define PRXS0_ACPHY_CLIP_MASK 0x000C /**< clip count adjustment steps by AGC */
-#define PRXS0_ACPHY_CLIP_SHIFT 2
-#define PRXS0_ACPHY_UNSRATE 0x0010 /**< PHY received a frame with unsupported rate */
-#define PRXS0_ACPHY_BAND5G 0x0020 /**< Rx Band indication: 0 -> 2G, 1 -> 5G */
-#define PRXS0_ACPHY_LCRS 0x0040 /**< CCK frame only: lost crs during cck frame reception */
-#define PRXS0_ACPHY_SHORTH 0x0080 /**< Short Preamble (CCK), GF preamble (HT) */
-#define PRXS0_ACPHY_PLCPFV 0x0100 /**< PLCP violation */
-#define PRXS0_ACPHY_PLCPHCF 0x0200 /**< PLCP header integrity check failed */
-#define PRXS0_ACPHY_MFCRS 0x0400 /**< Matched Filter CRS fired */
-#define PRXS0_ACPHY_ACCRS 0x0800 /**< Autocorrelation CRS fired */
-#define PRXS0_ACPHY_SUBBAND_MASK 0xF000 /**< FinalBWClassification:
- * lower nibble Bitfield of sub-bands occupied by Rx frame
- */
-/* ACPHY PhyRxStatus_1: */
-#define PRXS1_ACPHY_ANT_CORE0 0x0001 /* Antenna Config for core 0 */
-#define PRXS1_ACPHY_SUBBAND_MASK_GEN2 0xFF00 /**< FinalBWClassification:
- * lower byte Bitfield of sub-bands occupied by Rx frame
- */
-#define PRXS0_ACPHY_SUBBAND_SHIFT 12
-#define PRXS1_ACPHY_SUBBAND_SHIFT_GEN2 8
-
-/* acphy PhyRxStatus_3: */
-#define PRXS2_ACPHY_RXPWR_ANT0 0xFF00 /**< Rx power on core 1 */
-#define PRXS3_ACPHY_RXPWR_ANT1 0x00FF /**< Rx power on core 1 */
-#define PRXS3_ACPHY_RXPWR_ANT2 0xFF00 /**< Rx power on core 2 */
-#define PRXS3_ACPHY_SNR_ANT0 0xFF00 /* SNR on core 0 */
-
-/* acphy PhyRxStatus_4: */
-/** FinalBWClassification:upper nibble of sub-bands occupied by Rx frame */
-#define PRXS4_ACPHY_SUBBAND_MASK 0x000F
-#define PRXS4_ACPHY_RXPWR_ANT3 0x00FF /**< Rx power on core 3 */
-#define PRXS4_ACPHY_SNR_ANT1 0xFF00 /* SNR on core 1 */
-
-#define PRXS5_ACPHY_CHBWINNONHT_MASK 0x0003
-#define PRXS5_ACPHY_CHBWINNONHT_20MHZ 0
-#define PRXS5_ACPHY_CHBWINNONHT_40MHZ 1
-#define PRXS5_ACPHY_CHBWINNONHT_80MHZ 2
-#define PRXS5_ACPHY_CHBWINNONHT_160MHZ 3 /* includes 80+80 */
-#define PRXS5_ACPHY_DYNBWINNONHT_MASK 0x0004
-
-/** Get Rx power on core 0 */
-#define ACPHY_RXPWR_ANT0(rxs) (((rxs)->lt80.PhyRxStatus_2 & PRXS2_ACPHY_RXPWR_ANT0) >> 8)
-/** Get Rx power on core 1 */
-#define ACPHY_RXPWR_ANT1(rxs) ((rxs)->lt80.PhyRxStatus_3 & PRXS3_ACPHY_RXPWR_ANT1)
-/** Get Rx power on core 2 */
-#define ACPHY_RXPWR_ANT2(rxs) (((rxs)->lt80.PhyRxStatus_3 & PRXS3_ACPHY_RXPWR_ANT2) >> 8)
-/** Get Rx power on core 3 */
-#define ACPHY_RXPWR_ANT3(rxs) ((rxs)->lt80.PhyRxStatus_4 & PRXS4_ACPHY_RXPWR_ANT3)
-
-/** MCSSQSNR location access. MCSSQ usage is limited by chip specific impl,
- * and there is no way to commonize these status location yet.
- * TODO: When the storage locations are settled we need to revisit
- * this defs controls.
- */
-
-/* exception handling */
-#ifdef PHY_CORE_MAX
-#if PHY_CORE_MAX > 4
-#error "PHY_CORE_MAX is exceeded more than MCSSQSNR defs (4)"
-#endif
-#endif /* PHY_CORE_MAX */
-
-/* rev 48/55/59 are obsoleted for SNR in trunk */
-#define D11_PRXS_MCSSQ_SNR_SUPPORT(corerev) (D11REV_GE((corerev), 80))
-
-#define ACPHY_SNR_MASK (0xFF)
-#define ACPHY_SNR_SHIFT (8)
-
-#define PRXS5_ACPHY_DYNBWINNONHT(rxs) ((rxs)->lt80.PhyRxStatus_5 & PRXS5_ACPHY_DYNBWINNONHT_MASK)
-#define PRXS5_ACPHY_CHBWINNONHT(rxs) ((rxs)->lt80.PhyRxStatus_5 & PRXS5_ACPHY_CHBWINNONHT_MASK)
-
-#define D11N_MMPLCPLen(rxs) ((rxs)->lt80.PhyRxStatus_3 & PRXS3_nphy_MMPLCPLen_MASK)
-#define D11HT_MMPLCPLen(rxs) ((((rxs)->lt80.PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
- (((rxs)->lt80.PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
-
-/* REV80 Defintions (corerev >= 80) */
-
-/** Dma_flags Masks */
-#define RXS_PHYRXST_VALID_REV_GE80 0x02
-
-/** Get RxStatus1 */
-#define RXSTATUS1_REV_GE87_1(rxs) ((rxs)->ge87_1.RxStatus1)
-#define RXSTATUS1_REV_GE80(rxs) ((rxs)->ge80.RxStatus1)
-#define RXSTATUS1_REV_LT80(rxs) ((rxs)->lt80.RxStatus1)
-
-#define PHY_RXSTATUS1(corerev, corerev_minor, rxs) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? RXSTATUS1_REV_GE87_1(rxs) : \
- D11REV_GE(corerev, 80) ? RXSTATUS1_REV_GE80(rxs) : \
- RXSTATUS1_REV_LT80(rxs))
-
-/* (FT Mask) PhyRxStatus_0: */
-#define PRXS0_FT_MASK_REV_LT80 PRXS0_FT_MASK /**< (corerev < 80) frame type field mask */
-
-#define PRXS0_FT_SHIFT_REV_GE80 8
-#define PRXS0_FT_MASK_REV_GE80 0x0700 /**
- * (corerev >= 80) frame type field mask.
- *
- * 0 = CCK, 1 = 11a/g legacy OFDM,
- * 2 = HT, 3 = VHT, 4 = 11ah, 5 = HE,
- * 6-15 Rsvd.
- */
-
-/* *
-* Macro to find Frame type from RX Hdr based on corerev.
-*
-* Note: From rev80 onwards frame type is indicated only
-* in the phyrxstatus, which is valid only for the last
-* MPDU of an AMPDU. Since FT is required for every MPDU,
-* frametype for core-revs >= 80, shall be
-* provided in bits (8:10) of MuRate field in RXH.
-*
-*/
-#define D11PPDU_FT(rxh, rev) (\
- (D11REV_GE(rev, 80) ? \
- ((D11RXHDR_ACCESS_VAL(rxh, rev, 0, MuRate) & PRXS_FT_MASK(rev)) >> \
- (PRXS0_FT_SHIFT_REV_GE80)) : \
- (D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0) & PRXS_FT_MASK(rev))))
-
-#define PRXS_UNSRATE_LT85(rxh, rev) \
- (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \
- PRXS0_UNSRATE) >> PRXS0_UNSRATE_SHIFT)
-
-#define PRXS_UNSRATE(rxh, rev, min_rev) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_UNSRATE(rxh, rev, min_rev) : PRXS_UNSRATE_LT85(rxh, rev))
-
-// 1: short (or GF) preamble, 0: long (or MM) preamble
-#define PRXS_SHORTH_LT85(rxh, rev) \
- (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \
- PRXS0_SHORTH) >> PRXS0_SHORTH_SHIFT)
-#define PRXS_SHORTH(rxh, rev, min_rev) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_SHORTH(rxh, rev, min_rev) : \
- PRXS_SHORTH_LT85(rxh, rev))
-
-#define PRXS_PLCPFV_LT85(rxh, rev) \
- (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \
- PRXS0_PLCPFV) >> PRXS0_PLCPFV_SHIFT)
-#define PRXS_PLCPFV(rxh, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_PLCPFV(rxh, rev, rev_min) : PRXS_PLCPFV_LT85(rxh, rev))
-
-#define PRXS_PLCPHCF_LT85(rxh, rev) \
- (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \
- PRXS0_PLCPHCF) >> PRXS0_PLCPHCF_SHIFT)
-#define PRXS_PLCPHCF(rxh, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_PLCPHCF(rxh, rev, rev_min) : PRXS_PLCPHCF_LT85(rxh, rev))
-
-// final BW classification
-#define PRXS_SUBBAND_ACPHY(rxh, rev, rev_min) \
- (((D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0) & \
- PRXS0_ACPHY_SUBBAND_MASK) >> PRXS0_ACPHY_SUBBAND_SHIFT) | \
- ((D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_4) & \
- PRXS4_ACPHY_SUBBAND_MASK) << 4))
-#define PRXS_SUBBAND_ACPHY2(rxh, rev, rev_min) \
- (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \
- D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & PRXS1_ACPHY2_SUBBAND_MASK) >> \
- PRXS1_ACPHY2_SUBBAND_SHIFT)
-
-#define PRXS_SUBBAND(rxh, rev, rev_min, phyrev) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_SUBBAND(rxh, rev, rev_min) : (ACREV_GE(phyrev, 32) ? \
- PRXS_SUBBAND_ACPHY2(rxh, rev, rev_min) : \
- PRXS_SUBBAND_ACPHY(rxh, rev, rev_min)))
-
-/* Macros to access MCS, NSTS and MU valididity from MuRate field in corerev > 80 RXH */
-#define RXS_MU_VALID_MASK_REV80 0x0080
-#define RXS_MU_VALID_SHIFT_REV80 7
-#define RXS_MCS_MASK_REV80 0x000F
-#define RXS_MCS_SHIFT_REV80 0
-#define RXS_NSTS_MASK_REV80 0x0070
-#define RXS_NSTS_SHIFT_REV80 4
-
-#define D11PPDU_ISMU_REV80(rxh, corerev, corerev_minor) \
- ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \
- (RXS_MU_VALID_MASK_REV80)) >> RXS_MU_VALID_SHIFT_REV80)
-#define D11RXHDR_GE80_GET_MCS(rxh, corerev, corerev_minor) \
- ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \
- (RXS_MCS_MASK_REV80)) >> RXS_MCS_SHIFT_REV80)
-#define D11RXHDR_GE80_GET_NSTS(rxh, corerev, corerev_minor) \
- ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \
- (RXS_NSTS_MASK_REV80)) >> RXS_NSTS_SHIFT_REV80)
-
-/* subfield PRXS0_FT_MASK_REV_GE80 */
-#define PRXS0_HE 0x0004 /**< HE frame type */
-
-/* (Corerev >= 80) PhyRxStatus_2: */
-#define PRXS2_RXPWR_ANT0_REV_GE80 0x00FF /**< (corerev >= 80) Rx power on first antenna */
-#define PRXS2_RXPWR_ANT1_REV_GE80 0xFF00 /**< (corerev >= 80) Rx power on second antenna */
-
-/* (Corerev >= 80) PhyRxStatus_3: */
-#define PRXS3_RXPWR_ANT2_REV_GE80 0x00FF /**< (corerev >= 80) Rx power on third antenna */
-#define PRXS3_RXPWR_ANT3_REV_GE80 0xFF00 /**
- * (corerev >= 80) Rx power on fourth antenna.
- *
- * Note: For PHY revs 3 and > 4, OCL Status
- * byte 0 will be reported if PHY register
- * OCL_RxStatus_Ctrl is set to 0x2 or 0x6.
- */
-#define PRXS3_RXPWR_FRAC_REV_GE80 0xFFu
-
-/** Get Rx power on ANT 0 */
-#define RXPWR_ANT0_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_2 & \
- (PRXS2_RXPWR_ANT0_REV_GE80))
-
-#define PHY_RXPWR_ANT0(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_RXPWR_ANT0(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- RXPWR_ANT0_REV_GE80(rxs) : ACPHY_RXPWR_ANT0(rxs)))
-
-/** Get Rx power on ANT 1 */
-#define RXPWR_ANT1_REV_GE80(rxs) (((rxs)->ge80.PhyRxStatus_2 & \
- (PRXS2_RXPWR_ANT1_REV_GE80)) >> 8)
-
-#define PHY_RXPWR_ANT1(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_RXPWR_ANT1(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- RXPWR_ANT1_REV_GE80(rxs) : ACPHY_RXPWR_ANT1(rxs)))
-
-/** Get Rx power on ANT 2 */
-#define RXPWR_ANT2_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_3 & \
- (PRXS3_RXPWR_ANT2_REV_GE80))
-
-#define PHY_RXPWR_ANT2(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_RXPWR_ANT2(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- RXPWR_ANT2_REV_GE80(rxs) : ACPHY_RXPWR_ANT2(rxs)))
-
-/** Get Rx power on ANT 3 */
-#define RXPWR_ANT3_REV_GE80(rxs) (((rxs)->ge80.PhyRxStatus_3 & \
- (PRXS3_RXPWR_ANT3_REV_GE80)) >> 8)
-
-#define PHY_RXPWR_ANT3(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_RXPWR_ANT3(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- RXPWR_ANT3_REV_GE80(rxs) : ACPHY_RXPWR_ANT3(rxs)))
-
-/* Get the following entries from RXStatus bytes
-* for RSSI compensation
-* based on factory calibration
-* TIA Index
-* eLNA Index
-* V_path Switch
-*/
-#define PHY_ELNA_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_ELNA_IDX_ANT0(rxs, corerev, corerev_min)
-#define PHY_ELNA_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_ELNA_IDX_ANT1(rxs, corerev, corerev_min)
-#define PHY_TIA_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_TIA_IDX_ANT0(rxs, corerev, corerev_min)
-#define PHY_TIA_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_TIA_IDX_ANT1(rxs, corerev, corerev_min)
-#define PHY_VSW_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_VSW_IDX_ANT0(rxs, corerev, corerev_min)
-#define PHY_VSW_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \
- APRXS_VSW_IDX_ANT1(rxs, corerev, corerev_min)
-
-/** Get RSSI fractional bits */
-#define RXPWR_FRAC_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_4 & \
- (PRXS3_RXPWR_FRAC_REV_GE80))
-
-#define RXPWR_FRAC(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_RXPWR_FRAC(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- RXPWR_FRAC_REV_GE80(rxs) : 0))
-
-/* HECAPPHY PhyRxStatus_4: */
-#define PRXS4_DYNBWINNONHT_MASK_REV_GE80 0x1000
-#define PRXS4_DYNBWINNONHT_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_4 & \
- PRXS4_DYNBWINNONHT_MASK_REV_GE80)
-
-#define PRXS_PHY_DYNBWINNONHT(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_DYNBWINNONHT(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- PRXS4_DYNBWINNONHT_REV_GE80(rxs) : PRXS5_ACPHY_DYNBWINNONHT(rxs)))
-
-/** (corerev >= 80) PhyRxStatus_5: MCSSQ SNR for core 0 and 1 */
-#define PRXS5_MCSSQ_SHIFT (8u)
-#define PRXS5_MCSSQ_CORE0_REV_GE80 (0x00FF)
-#define PRXS5_MCSSQ_CORE1_REV_GE80 (0xFF00)
-
-#define MCSSQ_SNR_ANT0_GE80(rxs) ((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE0_REV_GE80)
-#define MCSSQ_SNR_ANT0(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_MCSSQSNR0(rxs, rev, rev_min) : \
- ((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE0_REV_GE80))
-
-#define MCSSQ_SNR_ANT1_GE80(rxs) (((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE1_REV_GE80) \
- >> PRXS5_MCSSQ_SHIFT)
-#define MCSSQ_SNR_ANT1(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_MCSSQSNR1(rxs, rev, rev_min) : \
- (((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE1_REV_GE80) \
- >> PRXS5_MCSSQ_SHIFT))
-
-/** (corerev >= 80) PhyRxStatus_6: MCSSQ SNR for core 2 and 3 */
-#define PRXS6_MCSSQ_SHIFT (8u)
-#define PRXS6_MCSSQ_CORE2_REV_GE80 (0x00FF)
-#define PRXS6_MCSSQ_CORE3_REV_GE80 (0xFF00)
-
-#define MCSSQ_SNR_ANT2_GE80(rxs) (((rxs)->ge80.phyrxs_rem[0] & \
- PRXS6_MCSSQ_CORE2_REV_GE80))
-#define MCSSQ_SNR_ANT2(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_MCSSQSNR2(rxs, rev, rev_min) : \
- (((rxs)->ge80.phyrxs_rem[0] & PRXS6_MCSSQ_CORE2_REV_GE80)))
-
-/* HECAPPHY PhyRxStatus_8 (part of phyrxs_rem[2]) : */
-#define PRXS8_CHBWINNONHT_MASK_REV_GE80 0x0100
-#define PRXS8_CHBWINNONHT_REV_GE80(rxs) ((rxs)->ge80.phyrxs_rem[2] & \
- PRXS8_CHBWINNONHT_MASK_REV_GE80)
-
-#define PRXS_PHY_CHBWINNONHT(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_CHBWINNONHT(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \
- PRXS8_CHBWINNONHT_REV_GE80(rxs) : PRXS5_ACPHY_CHBWINNONHT(rxs)))
-
-/* HE phyrxs_rem[4] */
-#define PRXS_REM4_PE_MASK_REV80 0x0380
-#define PRXS_REM4_PE_SHIFT_REV80 7u
-#define PRXS_REM4_RU_TYPE_MASK_REV80 0x1c00
-#define PRXS_REM4_RU_TYPE_SHIFT_REV80 10u
-#define PRXS_REM4_NUM_USER_SHIFT_REV80 13u
-#define PRXS_REM4_NUM_USER_BIT_MASK_REV80 0xe000
-
-/* HE phyrxs_rem[5] */
-#define PRXS_REM5_GI_LTF_MASK_REV80 0x0003
-#define PRXS_REM5_GI_LTF_SHIFT_REV80 0u
-#define PRXS_REM5_11AX_FF_MASK_REV80 0x0700
-#define PRXS_REM5_11AX_FF_SHIFT_REV80 8u
-
-/* HE phyrxs_rem[6] */
-#define PRXS_REM6_MCS_MASK_REV80 0x0f00
-#define PRXS_REM6_MCS_SHIFT_REV80 8u
-#define PRXS_REM6_CODING_MASK_REV80 0x1000
-#define PRXS_REM6_CODING_SHIFT_REV80 12u
-
-/* HE phyrxs_rem[7] */
-#define PRXS_REM7_DCM_MASK_REV80 0x8000
-#define PRXS_REM7_DCM_SHIFT_REV80 15u
-#define PRXS_REM7_TXBF_MASK_REV80 0x4000
-#define PRXS_REM7_TXBF_SHIFT_REV80 14u
-#define PRXS_REM7_NSTS_MASK_REV80 0x3800
-#define PRXS_REM7_NSTS_SHIFT_REV80 11u
-#define PRXS_REM7_RU_ALLOC_MASK_REV80 0x007f
-#define PRXS_REM7_RU_ALLOC_SHIFT_REV80 0u
-
-#define PRXS_STAID_MASK 0x07ff
-#define PRXS_STAID_SHIFT 0u
-
-enum {
- HE_RU_TYPE_26T = 0, /* 26 tone RU, 0 - 36 */
- HE_RU_TYPE_52T = 1, /* 52 tone RU, 37 - 52 */
- HE_RU_TYPE_106T = 2, /* 106 tone RU, 53 - 60 */
- HE_RU_TYPE_242T = 3, /* 242 tone RU, 61 - 64 */
- HE_RU_TYPE_484T = 4, /* 484 tone RU, 65 - 66 */
- HE_RU_TYPE_996T = 5, /* 996 tone RU, 67 - 68 */
- HE_RU_TYPE_2x996T = 6, /* 2x996 tone RU, 69 */
- HE_RU_TYPE_LAST = 7 /* Reserved, Invalid */
-};
-
-#define HE_RU_TYPE_MAX 6
-
-/* received PE duration is present in phyrxs_rem[4] bit position [7-9] */
-#define D11PPDU_PE_GE80(rxh, corerev) ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \
- (PRXS_REM4_PE_MASK_REV80)) >> PRXS_REM4_PE_SHIFT_REV80)
-
-#define D11PPDU_PE(rxh, corerev, corerev_minor) (AUTO_PHYRXSTS_ENAB() ? \
- APRXS_PE(rxh, corerev, corerev_minor) : D11PPDU_PE_GE80(rxh, corerev))
-
-/* received RU type is present in phyrxs_rem[4] bit position [10-11] */
-#define D11PPDU_RU_TYPE(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_RU(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \
- (PRXS_REM4_RU_TYPE_MASK_REV80)) >> PRXS_REM4_RU_TYPE_SHIFT_REV80) : 0))
-
-/* received he num of user type is present in phyrxs_rem[4] bit position [13-15] */
-#define D11PPDU_HE_NUM_USER_TYPE(rxh, corerev, corerev_min) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_USTY(rxh, corerev, corerev_min) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \
- (PRXS_REM4_NUM_USER_BIT_MASK_REV80)) >> PRXS_REM4_NUM_USER_SHIFT_REV80) : 0))
-
-#define D11PPDU_FF_TYPE(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_AXFF(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[5]) & \
- (PRXS_REM5_11AX_FF_MASK_REV80)) >> PRXS_REM5_11AX_FF_SHIFT_REV80) : 0))
-
-/* DCM is present in phyrxs_rem[7] byte 27, bit position [7] */
-#define D11PPDU_DCM(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_DCM(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \
- (PRXS_REM7_DCM_MASK_REV80)) >> PRXS_REM7_DCM_SHIFT_REV80) : 0))
-
-/* coding used is present in phyrxs_rem[6] byte:25, bit position [12] */
-#define D11PPDU_CODING(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_CODING(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[6]) & \
- (PRXS_REM6_CODING_MASK_REV80)) >> PRXS_REM6_CODING_SHIFT_REV80) : 0))
-
-/* spatial reuse 2 / STA-ID */
-#define D11PPDU_STAID(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_AX_STAID(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \
- (PRXS_STAID_MASK)) >> PRXS_STAID_SHIFT) : 0))
-
-#define D11PPDU_TXBF(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_TXBF(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \
- (PRXS_REM7_TXBF_MASK_REV80)) >> PRXS_REM7_TXBF_SHIFT_REV80) : 0))
-
-/* GI_LTF is present in phyrxs_rem[5] bit position [0-1] */
-#define D11PPDU_GI_LTF(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_GILTF(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[5]) & \
- (PRXS_REM5_GI_LTF_MASK_REV80)) >> PRXS_REM5_GI_LTF_SHIFT_REV80) : 0))
-
-/* MCS is present in phyrxs_rem[6] - byte 25, bit position [8-11] */
-#define D11PPDU_MCS(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_AXMCS(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[6]) & \
- (PRXS_REM6_MCS_MASK_REV80)) >> PRXS_REM6_MCS_SHIFT_REV80) : 0))
-
-/* NSTS present in phyrxs_rem[7] bit position [11-13] */
-#define D11PPDU_NSTS(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_NSTS(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \
- (PRXS_REM7_NSTS_MASK_REV80)) >> PRXS_REM7_NSTS_SHIFT_REV80) : 0))
-
-/* RU ALLOC present in phyrxs_rem[7]- byte 26; bit position [6:0] */
-#define D11PPDU_RU_ALLOC(rxh, corerev, corerev_minor) \
- (AUTO_PHYRXSTS_ENAB() ? APRXS_AX_RUALLOC(rxh, corerev, corerev_minor) : \
- (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \
- (PRXS_REM7_RU_ALLOC_MASK_REV80)) >> PRXS_REM7_RU_ALLOC_SHIFT_REV80) : 0)
-
-/* PHY RX status "Frame Type" field mask. */
-#define PRXS_FT_MASK(corerev) \
- (D11REV_GE(corerev, 80) ? (PRXS0_FT_MASK_REV_GE80) : \
- (PRXS0_FT_MASK_REV_LT80))
-
-/**
- * ACPHY PhyRxStatus0 SubBand (FinalBWClassification) bit defs
- * FinalBWClassification is a 4 bit field, each bit representing one 20MHz sub-band
- * of a channel.
- */
-enum prxs_subband {
- PRXS_SUBBAND_20LL = 0x0001,
- PRXS_SUBBAND_20LU = 0x0002,
- PRXS_SUBBAND_20UL = 0x0004,
- PRXS_SUBBAND_20UU = 0x0008,
- PRXS_SUBBAND_40L = 0x0003,
- PRXS_SUBBAND_40U = 0x000C,
- PRXS_SUBBAND_80 = 0x000F,
- PRXS_SUBBAND_20LLL = 0x0001,
- PRXS_SUBBAND_20LLU = 0x0002,
- PRXS_SUBBAND_20LUL = 0x0004,
- PRXS_SUBBAND_20LUU = 0x0008,
- PRXS_SUBBAND_20ULL = 0x0010,
- PRXS_SUBBAND_20ULU = 0x0020,
- PRXS_SUBBAND_20UUL = 0x0040,
- PRXS_SUBBAND_20UUU = 0x0080,
- PRXS_SUBBAND_40LL = 0x0003,
- PRXS_SUBBAND_40LU = 0x000c,
- PRXS_SUBBAND_40UL = 0x0030,
- PRXS_SUBBAND_40UU = 0x00c0,
- PRXS_SUBBAND_80L = 0x000f,
- PRXS_SUBBAND_80U = 0x00f0,
- PRXS_SUBBAND_160 = 0x00ff
-};
-
-enum prxs_subband_bphy {
- PRXS_SUBBAND_BPHY_20L = 0x0000,
- PRXS_SUBBAND_BPHY_20U = 0x0001
-};
-
-/* ACPHY Gen2 RxStatus defs */
-
-/* ACPHY Gen2 PhyRxStatus_0: */
-#define PRXS0_ACPHY2_MUPPDU 0x1000 /**< 0: SU PPDU; 1: MU PPDU */
-#define PRXS0_ACPHY2_OBSS 0xE000 /**< OBSS mitigation state */
-
-/* ACPHY Gen2 PhyRxStatus_1: */
-#define PRXS1_ACPHY2_SUBBAND_MASK 0xFF00 /**< FinalBWClassification:
- * 8-bit bitfield of sub-bands occupied by Rx frame
- */
-#define PRXS1_ACPHY2_SUBBAND_SHIFT 8
-
-/* ACPHY Gen2 PhyRxStatus_2: */
-#define PRXS2_ACPHY2_MU_INT 0x003F /**< MU interference processing type */
-
-/* ACPHY Gen2 PhyRxStatus_5: */
-#define PRXS5_ACPHY2_RSSI_FRAC 0xFF00 /**< RSSI fractional bits */
-
-/* ucode RxStatus1: */
-#define RXS_BCNSENT 0x8000
-#define RXS_TOFINFO 0x4000 /**< Rxed measurement frame processed by ucode */
-#define RXS_GRANTBT 0x2000 /* Indicate medium given to BT */
-#define RXS_SECKINDX_MASK_GE64 0x1fe0
-#define RXS_SECKINDX_MASK 0x07e0
-#define RXS_IS_DEFRAG 0x4
-#define RXS_DEFRAG_SHIFT 2
-#define RXS_SECKINDX_SHIFT 5
-#define RXS_DECERR (1 << 4)
-#define RXS_DECATMPT (1 << 3)
-#define RXS_PBPRES (1 << 2) /**< PAD bytes to make IP data 4 bytes aligned */
-#define RXS_RESPFRAMETX (1 << 1)
-#define RXS_FCSERR (1 << 0)
-
-/* ucode RxStatus2: */
-#define RXS_AMSDU_MASK 1
-#define RXS_AGGTYPE_MASK 0x6
-#define RXS_AGGTYPE_SHIFT 1
-#define RXS_AMSDU_FIRST 1
-#define RXS_AMSDU_INTERMEDIATE 0
-#define RXS_AMSDU_LAST 2
-#define RXS_AMSDU_N_ONE 3
-#define RXS_TKMICATMPT (1 << 3)
-#define RXS_TKMICERR (1 << 4)
-#define RXS_PHYRXST_PRISEL_CLR (1 << 5) /**< PR113291: When '1', Indicates that the Rx */
- /* packet was received while the antenna */
- /* (prisel) had been granted to BT. */
-#define RXS_PHYRXST_VALID (1 << 8)
-#define RXS_BCNCLSG (1 << 9) /**< Coleasced beacon packet */
-#define RXS_RXANT_MASK 0x3
-#define RXS_RXANT_SHIFT_LT80 12
-#define RXS_RXANT_SHIFT_GE80 5
-#define RXS_LOOPBACK_MODE 4
-
-/* Bit definitions for MRXS word for short rx status. */
-/* RXSS = RX Status Short */
-#define RXSS_AMSDU_MASK 1 /**< 1: AMSDU */
-#define RXSS_AGGTYPE_MASK 0x6 /**< 0 intermed, 1 first, 2 last, 3 single/non-AMSDU */
-#define RXSS_AGGTYPE_SHIFT 1
-#define RXSS_PBPRES (1 << 3) /**< two-byte PAD prior to plcp */
-#define RXSS_HDRSTS (1 << 4) /**< header conversion status. 1 enabled, 0 disabled */
-#define RXSS_RES_MASK 0xE0 /**< reserved */
-#define RXSS_MSDU_CNT_MASK 0xFF00 /**< index of this AMSDU sub-frame in the AMSDU */
-#define RXSS_MSDU_CNT_SHIFT 8
-
-/* RX signal control definitions */
-/** PHYRXSTAUS validity checker; in-between ampdu, or rxs status isn't valid */
-#define PRXS_IS_VALID(rxh, rev, rev_min) \
- ((D11REV_GE(rev, 80) && \
- (D11RXHDR_ACCESS_VAL(rxh, rev, rev_min, dma_flags) & \
- RXS_PHYRXST_VALID_REV_GE80)) || \
- (D11REV_GE(rev, 64) && !(D11RXHDR_ACCESS_VAL(rxh, \
- rev, rev_min, dma_flags) & RXS_SHORT_MASK)) || \
- (D11RXHDR_ACCESS_VAL(rxh, rev, rev_min, RxStatus2) & RXS_PHYRXST_VALID))
-
-/* RxChan */
-#define RXS_CHAN_40 0x1000
-#define RXS_CHAN_5G 0x0800
-#define RXS_CHAN_ID_MASK 0x07f8
-#define RXS_CHAN_ID_SHIFT 3
-
-#define C_BTCX_AGGOFF_BLE (1 << 0)
-#define C_BTCX_AGGOFF_A2DP (1 << 1)
-#define C_BTCX_AGGOFF_PER (1 << 2)
-#define C_BTCX_AGGOFF_MULTIHID (1 << 3)
-#define C_BTCX_AGG_LMT_SET_HIGH (1 << 4)
-#define C_BTCX_AGGOFF_ESCO_SLAVE (1 << 5)
-
-#define BTCX_HFLG_NO_A2DP_BFR (1 << 0) /**< no check a2dp buffer */
-#define BTCX_HFLG_NO_CCK (1 << 1) /**< no cck rate for null or cts2self */
-#define BTCX_HFLG_NO_OFDM_FBR (1 << 2) /**< no ofdm fbr for null or cts2self */
-#define BTCX_HFLG_NO_INQ_DEF (1 << 3) /**< no defer inquery */
-#define BTCX_HFLG_GRANT_BT (1 << 4) /**< always grant bt */
-#define BTCX_HFLG_ANT2WL (1 << 5) /**< force prisel to wl */
-#define BTCX_HFLG_PS4ACL (1 << 7) /**< use ps null for unsniff acl */
-#define BTCX_HFLG_DYAGG (1 << 8) /**< dynamic tx aggregation */
-#define BTCX_HFLG_SKIPLMP (1 << 10) /**< no LMP check for 4331 (w 20702 A1/A3) */
-#define BTCX_HFLG_ACL_BSD_BLE_SCAN_GRNT (1 << 14) /**< ACL based grant for BLE scan */
- /* indication to ucode */
-#define BTCX_HFLG2_TRAP_RFACTIVE (1 << 0) /* trap when RfActive too long */
-#define BTCX_HFLG2_TRAP_TXCONF (1 << 1) /* trap when coex grants txconf late */
-#define BTCX_HFLG2_TRAP_ANTDLY (1 << 2) /* trap when coex grants antdly late */
-#define BTCX_HFLG2_TRAP_BTTYPE (1 << 3) /* trap when illegal BT tasktype receive */
-/* Bit definitions for M_BTCX_CONFIG */
-#define BTCX_CONFIG_FORCE_TRAP (1 << 13) /* Force a specific BTCoex TRAP when set */
-
-/* BTCX_CONFIG bits */
-#define C_BTCX_CONFIG_SLOTTED_STATE_1 (1 << 3)
-#define C_BTCX_CONFIG_SLOTTED_STATE_2 (1 << 4)
-#define C_BTCX_CONFIG_SLOTTED_STATE_3 (1 << 5)
-#define C_BTCX_CONFIG_LOW_RSSI (1 << 7)
-#define C_BTCX_CONFIG_BT_STROBE (1 << 9)
-#define C_BTCX_CONFIG_SCO_PROT (1 << 10)
-#define C_BTCX_CFG_CMN_CTS2SELF (1 << 11)
-#define C_BTCX_CONFIG_HPP_STATE (1 << 15)
-
-#define BTC_PARAMS_FW_START_IDX 1000 /**< starting index of FW only btc params */
-/** BTC_PARAMS_FW definitions */
-typedef enum
-{
- // allow rx-agg to be re-enabled after SCO session completes
- BTC_FW_RX_REAGG_AFTER_SCO = BTC_PARAMS_FW_START_IDX,
- // RSSI threshold at which SCO grant/deny limits are changed dynamically
- BTC_FW_RSSI_THRESH_SCO = BTC_PARAMS_FW_START_IDX + 1,
- // Enable the dynamic LE scan priority
- BTC_FW_ENABLE_DYN_LESCAN_PRI = BTC_PARAMS_FW_START_IDX + 2,
- // If Tput(mbps) is above this, then share antenna with BT's LE_SCAN packet type.
- BTC_FW_LESCAN_LO_TPUT_THRESH = BTC_PARAMS_FW_START_IDX + 3,
- // If Tput(mbps) is below this, then share antenna with BT's LE_SCAN packet type.
- // sampled once a second.
- BTC_FW_LESCAN_HI_TPUT_THRESH = BTC_PARAMS_FW_START_IDX + 4,
- // Numbers of denials before granting LS scans
- BTC_FW_LESCAN_GRANT_INT = BTC_PARAMS_FW_START_IDX + 5,
- // number of times algorighm changes lescn pri
- BTC_FW_LESCAN_ALG_CNT = BTC_PARAMS_FW_START_IDX + 6,
- // RSSI threshold at which aggregation will be disabled during frequent BLE activity
- BTC_FW_RSSI_THRESH_BLE = BTC_PARAMS_FW_START_IDX + 7,
- // AMPDU Aggregation state requested by BTC
- BTC_FW_AGG_STATE_REQ = BTC_PARAMS_FW_START_IDX + 8,
- // Reserving space for parameters used in other projects
- BTC_FW_RSVD_1 = BTC_PARAMS_FW_START_IDX + 9,
- BTC_FW_HOLDSCO_LIMIT = BTC_PARAMS_FW_START_IDX + 10, // Lower Limit
- BTC_FW_HOLDSCO_LIMIT_HI = BTC_PARAMS_FW_START_IDX + 11, // Higher Limit
- BTC_FW_SCO_GRANT_HOLD_RATIO = BTC_PARAMS_FW_START_IDX + 12, // Low Ratio
- BTC_FW_SCO_GRANT_HOLD_RATIO_HI = BTC_PARAMS_FW_START_IDX + 13, // High Ratio
- BTC_FW_HOLDSCO_HI_THRESH = BTC_PARAMS_FW_START_IDX + 14, // BT Period Threshold
- BTC_FW_MOD_RXAGG_PKT_SZ_FOR_SCO = BTC_PARAMS_FW_START_IDX + 15,
- /* Modify Rx Aggregation size when SCO/eSCO detected */
- BTC_FW_AGG_SIZE_LOW = BTC_PARAMS_FW_START_IDX + 16,
- /* Agg size when BT period < 7500 ms */
- BTC_FW_AGG_SIZE_HIGH = BTC_PARAMS_FW_START_IDX + 17,
- /* Agg size when BT period >= 7500 ms */
- BTC_FW_MOD_RXAGG_PKT_SZ_FOR_A2DP = BTC_PARAMS_FW_START_IDX + 18,
- /* Enable COEX constraints for TWT scheduling */
- BTC_FW_TWT_COEX_CONSTRAINTS_EN = BTC_PARAMS_FW_START_IDX + 19,
- /* Enable Rx Aggregation for P2P_GO and SOFTAP when ACL/A2DP detected */
- BTC_FW_MOD_RXAGG_PKT_SZ_FOR_APMODE_ACL_A2DP = BTC_PARAMS_FW_START_IDX + 20,
- /* Disable amsdu dynamicaly during Rx limited aggregation */
- BTC_FW_DISABLE_AMSDU_DURING_LIM_AGG = BTC_PARAMS_FW_START_IDX + 21,
- /* Enable acl based grant for ble scan based on number of 2G slots */
- BTC_FW_ENABLE_ACL_GRNT_FOR_BLE_SCAN = BTC_PARAMS_FW_START_IDX + 22,
- /* Threshold slot count for 2g band to Enable acl based grant for ble scan during NAN */
- BTC_FW_NAN_THRESHOLD_SLOTS_FOR_2G = BTC_PARAMS_FW_START_IDX + 23,
- /* BT task bm override for critical chansw slots */
- BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_L = BTC_PARAMS_FW_START_IDX + 24,
- BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_H = BTC_PARAMS_FW_START_IDX + 25,
- /* Limited Aggr AP check grace period, # of BTC watchdog timeout */
- BTC_FW_AGG_AP_GRACE_PERIOD = BTC_PARAMS_FW_START_IDX + 26,
- /* Limited Aggr AP check buffer limit, sample interval, # of BTC watchdog timeout */
- BTC_FW_AGG_AP_BUFLIM_SMPLINTV = BTC_PARAMS_FW_START_IDX + 27,
- /* Limited Aggr AP check excessive DELBA, sample interval, # of BTC watchdog timeout */
- BTC_FW_AGG_AP_DELBA_SMPLINTV = BTC_PARAMS_FW_START_IDX + 28,
- /* Limited Aggr AP check excessive DELBA, threshold, # of DELBA */
- BTC_FW_AGG_AP_DELBA_THRESHOLD = BTC_PARAMS_FW_START_IDX + 29,
- BTC_FW_MAX_INDICES // Maximum number of btc_fw sw registers
-} btcParamsFirmwareDefinitions;
-
-#define BTC_FW_NUM_INDICES (BTC_FW_MAX_INDICES - BTC_PARAMS_FW_START_IDX)
-
-// 1: Re-enable aggregation after SCO
-#define BTC_FW_RX_REAGG_AFTER_SCO_INIT_VAL 1
-
-// 1: Enable limited aggregation for SCO
-#define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_SCO_INIT_VAL 0
-
-/* Enable Limited aggregation for HI interval BT periodic task only (>=7.5ms) */
-#ifdef WL_BTC_LIMAGG_HI_INT
-/* RX aggregation packet size when SCO */
-#define BTC_FW_AGG_SIZE_LOW_INIT_VAL 0
-#else
-/* RX aggregation packet size when SCO */
-#define BTC_FW_AGG_SIZE_LOW_INIT_VAL 1
-#endif
-
-/* aggregation size when BT period < BT_AMPDU_RESIZE_THRESH */
-#define BTC_FW_AGG_SIZE_HIGH_INIT_VAL 2
-/* aggregation size when BT period > BT_AMPDU_RESIZE_THRESH */
-// 0: disable weak-rssi SCO coex feature. If > 0, adjust SCO COEX algorithm for weak RSSI scenario.
-#define BTC_FW_RSSI_THRESH_SCO_INIT_VAL 0
-
-// 1: Enable limited aggregation for A2DP
-#define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_A2DP_INIT_VAL 0
-
-// Enable LE Scan Priority Algorithm 0: Disable, 1: Enable
-#define BTC_FW_ENABLE_DYN_LESCAN_PRI_INIT_VAL 0
-// If WL Tput below 7 mbps, don't grant background LE Scans
-#define BTC_FW_LESCAN_LO_TPUT_THRESH_INIT_VAL 7
-// If WL Tput above 30 mbps, don't grant background LE Scans
-#define BTC_FW_LESCAN_HI_TPUT_THRESH_INIT_VAL 30
-// If LE Priority algorithm is triggered, grant one out of 2 LE_SCAN requests
-#define BTC_FW_LESCAN_GRANT_INT_INIT_VAL 2
-// If RSSI is weaker than -70 dBm and BLE activity is frequent, then disable
-// RX aggregation, and clamp TX aggregation.
-#ifdef WL_BTCX_UDM
-#define BTC_FW_RSSI_THRESH_BLE_INIT_VAL 100
-#else
-#define BTC_FW_RSSI_THRESH_BLE_INIT_VAL 70
-#endif
-#define BTC_FW_HOLDSCO_LIMIT_INIT_VAL 100
-#define BTC_FW_HOLDSCO_LIMIT_HI_INIT_VAL 10
-#define BTC_FW_SCO_GRANT_HOLD_RATIO_INIT_VAL 1500
-#define BTC_FW_SCO_GRANT_HOLD_RATIO_HI_INIT_VAL 1000
-#define BTC_FW_HOLDSCO_HI_THRESH_INIT_VAL 7400
-#define BTC_FW_TWT_COEX_CONSTRAINTS_EN_INIT_VAL 1
-/* Aggregation in AP mode (P2P_GO and SOFTAP) when ACL and A2DP */
-#define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_APMODE_ACL_A2DP_INIT_VAL 16
-/* Disable amsdu dynamicaly during Rx limited aggregation */
-#define BTC_FW_DISABLE_AMSDU_DURING_LIM_AGG_INIT_VAL 1
-/* Enable acl based grant for ble scan based on number of 2G slots during NAN */
-#define BTC_FW_ENABLE_ACL_GRNT_FOR_BLE_SCAN_INIT_VAL 0
-/* Threshold slot count for 2g band to Enable acl based grant for ble
- * scan during NAN. Setting current value to 8, considering time line is 512ms
- * Threshold changes dynamically based on different time line
- */
-#define BTC_FW_NAN_THRESHOLD_SLOTS_FOR_2G_INIT_VAL 8
-/* BT task bm override for critical chansw slots -initval */
-#define BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_L_INIT_VAL 0x0000
-#define BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_H_INIT_VAL 0x0020
-#define BTC_FW_AGG_AP_GRACE_PERIOD_VAL 1
-#define BTC_FW_AGG_AP_BUFLIM_SMPLINTV_VAL 1
-#define BTC_FW_AGG_AP_DELBA_SMPLINTV_VAL 5
-#define BTC_FW_AGG_AP_DELBA_THRESHOLD_VAL 3
-
-/* NR Coex Params Set/Get via wl btc_params, starting index */
-#define NR5GCX_PARAMS_FW_START_IDX 1200
-
-typedef enum NR5GCX_Params {
- // Min # of PPDU to be tracked for hysteresis
- NR5GCX_FW_MIN_NUM_PPDU = NR5GCX_PARAMS_FW_START_IDX,
- // Threshold for data stall detection, percentage
- NR5GCX_FW_DATA_STALL_TH = NR5GCX_PARAMS_FW_START_IDX + 1,
- // max number of rate recovery attempts
- NR5GCX_FW_MAX_NUM_ATTEMPTS = NR5GCX_PARAMS_FW_START_IDX + 2,
- // Rate recovery rate check duration
- NR5GCX_FW_RR_RATE_CHK_DUR = NR5GCX_PARAMS_FW_START_IDX + 3,
- // Rate recovery attempt duration
- NR5GCX_FW_RR_ATTEMPT_DUR = NR5GCX_PARAMS_FW_START_IDX + 4,
- // NR grant duration after a unsuccessful rate recovery
- NR5GCX_FW_RR_UNSC_DUR = NR5GCX_PARAMS_FW_START_IDX + 5,
- // Threshold for rate recovery, percentage
- NR5GCX_FW_RECOVERY_TH = NR5GCX_PARAMS_FW_START_IDX + 6,
- // Threshold for low RSSI
- NR5GCX_FW_LOWRSSI_TH = NR5GCX_PARAMS_FW_START_IDX + 7,
- // Maximum number of nr5gcx fw params
- NR5GCX_FW_MAX_INDICES
-} NR5GCXParamsFirmwareDefinitions;
-
-#define NR5GCX_FW_NUM_INDICES (NR5GCX_FW_MAX_INDICES - NR5GCX_PARAMS_FW_START_IDX)
-
-#define NR5GCX_FW_MIN_NUM_PPDU_INIT 10u
-#define NR5GCX_FW_DATA_STALL_TH_INIT 75u
-#define NR5GCX_FW_MAX_NUM_ATTEMPTS_INIT 5u
-#define NR5GCX_FW_RR_RATE_CHK_DUR_INIT_MS 60u /* ms */
-#define NR5GCX_FW_RR_ATTEMPT_DUR_INIT_MS 60u /* ms */
-#define NR5GCX_FW_RR_UNSC_DUR_INIT_MS 10000u /* ms */
-#define NR5GCX_FW_RECOVERY_TH_INIT 50u
-#define NR5GCX_FW_LOWRSSI_TH_INIT 85u /* dBm */
-
-/* RC1 Coex Params Set/Get via wl btc_params, starting index */
-#define RC1CX_PARAMS_FW_START_IDX 1200
-
-typedef enum RC1CX_Params {
- // Min # of PPDU to be tracked for hysteresis
- RC1CX_FW_MIN_NUM_PPDU = RC1CX_PARAMS_FW_START_IDX,
- // Threshold for data stall detection, percentage
- RC1CX_FW_DATA_STALL_TH = RC1CX_PARAMS_FW_START_IDX + 1,
- // max number of rate recovery attempts
- RC1CX_FW_MAX_NUM_ATTEMPTS = RC1CX_PARAMS_FW_START_IDX + 2,
- // Rate recovery rate check duration
- RC1CX_FW_RR_RATE_CHK_DUR = RC1CX_PARAMS_FW_START_IDX + 3,
- // Rate recovery attempt duration
- RC1CX_FW_RR_ATTEMPT_DUR = RC1CX_PARAMS_FW_START_IDX + 4,
- // NR grant duration after a unsuccessful rate recovery
- RC1CX_FW_RR_UNSC_DUR = RC1CX_PARAMS_FW_START_IDX + 5,
- // Threshold for rate recovery, percentage
- RC1CX_FW_RECOVERY_TH = RC1CX_PARAMS_FW_START_IDX + 6,
- // Threshold for low RSSI
- RC1CX_FW_LOWRSSI_TH = RC1CX_PARAMS_FW_START_IDX + 7,
- // Maximum number of rc1cx fw params
- RC1CX_FW_MAX_INDICES
-} RC1CXParamsFirmwareDefinitions;
-
-#define RC1CX_FW_NUM_INDICES (RC1CX_FW_MAX_INDICES - RC1CX_PARAMS_FW_START_IDX)
-
-#define RC1CX_FW_MIN_NUM_PPDU_INIT 10u
-#define RC1CX_FW_DATA_STALL_TH_INIT 75u
-#define RC1CX_FW_MAX_NUM_ATTEMPTS_INIT 5u
-#define RC1CX_FW_RR_RATE_CHK_DUR_INIT_MS 60u /* ms */
-#define RC1CX_FW_RR_ATTEMPT_DUR_INIT_MS 60u /* ms */
-#define RC1CX_FW_RR_UNSC_DUR_INIT_MS 10000u /* ms */
-#define RC1CX_FW_RECOVERY_TH_INIT 50u
-#define RC1CX_FW_LOWRSSI_TH_INIT 85u /* dBm */
-
-#ifdef GPIO_TXINHIBIT
-/* GPIO based TX_INHIBIT:SWWLAN-109270 */
-typedef enum shm_macintstatus_ext_e {
- C_MISE_GPIO_TXINHIBIT_VAL_NBIT = 0,
- C_MISE_GPIO_TXINHIBIT_INT_NBIT = 1
-} shm_macintstatus_ext_t;
-#define C_MISE_GPIO_TXINHIBIT_VAL_MASK (1 << C_MISE_GPIO_TXINHIBIT_VAL_NBIT)
-#define C_MISE_GPIO_TXINHIBIT_INT_MASK (1 << C_MISE_GPIO_TXINHIBIT_INT_NBIT)
-#endif
-#define M_PSM_SOFT_REGS 0x0
-
-/** Scratch Reg defs */
-typedef enum
-{
- S_RSV0 = 0,
- S_RSV1,
- S_RSV2,
-
- /* scratch registers for Dot11-constants */
- S_DOT11_CWMIN, /**< CW-minimum 0x03 */
- S_DOT11_CWMAX, /**< CW-maximum 0x04 */
- S_DOT11_CWCUR, /**< CW-current 0x05 */
- S_DOT11_SRC_LMT, /**< short retry count limit 0x06 */
- S_DOT11_LRC_LMT, /**< long retry count limit 0x07 */
- S_DOT11_DTIMCOUNT, /**< DTIM-count 0x08 */
-
- /* Tx-side scratch registers */
- S_SEQ_NUM, /**< hardware sequence number reg 0x09 */
- S_SEQ_NUM_FRAG, /**< seq-num for frags (Set at the start os MSDU 0x0A */
- S_FRMRETX_CNT, /**< frame retx count 0x0B */
- S_SSRC, /**< Station short retry count 0x0C */
- S_SLRC, /**< Station long retry count 0x0D */
- S_EXP_RSP, /**< Expected response frame 0x0E */
- S_OLD_BREM, /**< Remaining backoff ctr 0x0F */
- S_OLD_CWWIN, /**< saved-off CW-cur 0x10 */
- S_TXECTL, /**< TXE-Ctl word constructed in scr-pad 0x11 */
- S_CTXTST, /**< frm type-subtype as read from Tx-descr 0x12 */
-
- /* Rx-side scratch registers */
- S_RXTST, /**< Type and subtype in Rxframe 0x13 */
-
- /* Global state register */
- S_STREG, /**< state storage actual bit maps below 0x14 */
-
- S_TXPWR_SUM, /**< Tx power control: accumulator 0x15 */
- S_TXPWR_ITER, /**< Tx power control: iteration 0x16 */
- S_RX_FRMTYPE, /**< Rate and PHY type for frames 0x17 */
- S_THIS_AGG, /**< Size of this AGG (A-MSDU) 0x18 */
-
- S_KEYINDX, /* 0x19 */
- S_RXFRMLEN, /**< Receive MPDU length in bytes 0x1A */
-
- /* Receive TSF time stored in SCR */
- S_RXTSFTMRVAL_WD3, /**< TSF value at the start of rx 0x1B */
- S_RXTSFTMRVAL_WD2, /**< TSF value at the start of rx 0x1C */
- S_RXTSFTMRVAL_WD1, /**< TSF value at the start of rx 0x1D */
- S_RXTSFTMRVAL_WD0, /**< TSF value at the start of rx 0x1E */
- S_RXSSN, /**< Received start seq number for A-MPDU BA 0x1F */
- S_RXQOSFLD, /**< Rx-QoS field (if present) 0x20 */
-
- /* Scratch pad regs used in microcode as temp storage */
- S_TMP0, /**< stmp0 0x21 */
- S_TMP1, /**< stmp1 0x22 */
- S_TMP2, /**< stmp2 0x23 */
- S_TMP3, /**< stmp3 0x24 */
- S_TMP4, /**< stmp4 0x25 */
- S_TMP5, /**< stmp5 0x26 */
- S_PRQPENALTY_CTR, /**< Probe response queue penalty counter 0x27 */
- S_ANTCNT, /**< unsuccessful attempts on current ant. 0x28 */
- S_SYMBOL, /**< flag for possible symbol ctl frames 0x29 */
- S_RXTP, /**< rx frame type 0x2A */
- S_STREG2, /**< extra state storage 0x2B */
- S_STREG3, /**< even more extra state storage 0x2C */
- S_STREG4, /**< ... 0x2D */
- S_STREG5, /**< remember to initialize it to zero 0x2E */
-
- S_UNUSED_0X2F, /**< No longer used 0x2F */
- S_UPTR, /* Use this to initialize utrace 0x30 */
- S_ADJPWR_IDX, /**< PR 37101 WAR, adj_pwr_idx 0x31 */
- S_CUR_PTR, /**< Temp pointer for A-MPDU re-Tx SHM table 0x32 */
- S_REVID4, /**< 0x33 */
- S_INDX, /**< 0x34 */
- S_ADDR0, /**< 0x35 */
- S_ADDR1, /**< 0x36 */
- S_ADDR2, /**< 0x37 */
- S_ADDR3, /**< 0x38 */
- S_ADDR4, /**< 0x39 */
- S_ADDR5, /**< 0x3A */
- S_TMP6, /**< 0x3B */
- S_KEYINDX_BU, /**< Backup for Key index 0x3C */
- S_MFGTEST_TMP0, /**< Temp register used for RX test calculations 0x3D */
- S_RXESN, /**< Received end sequence number for A-MPDU BA 0x3E */
- S_STREG6, /**< 0x3F */
-} ePsmScratchPadRegDefinitions;
-
-#define C_STREG_SLOWCAL_PD_NBIT 0x00000004 /* BIT 2 slow clock cal is pending */
-#define C_STREG_SLOWCAL_DN_NBIT 0x00000008 /* BIT 3 slow clock cal is done */
-
-#define S_BEACON_INDX S_OLD_BREM
-#define S_PRS_INDX S_OLD_CWWIN
-#define S_BTCX_BT_DUR S_REVID4
-#define S_PHYTYPE S_SSRC
-#define S_PHYVER S_SLRC
-
-/* IHR GPT_2 is corerev >= 3 */
-#define TSF_GPT_2_STAT 0x133
-#define TSF_GPT_2_CTR_L 0x134
-#define TSF_GPT_2_CTR_H 0x135
-#define TSF_GPT_2_VAL_L 0x136
-#define TSF_GPT_2_VAL_H 0x137
-
-/* IHR TSF_GPT STAT values */
-#define TSF_GPT_PERIODIC (1 << 12)
-#define TSF_GPT_ADJTSF (1 << 13)
-#define TSF_GPT_USETSF (1 << 14)
-#define TSF_GPT_ENABLE (1 << 15)
-
-/** ucode mac statistic counters in shared memory */
-#define MACSTAT_OFFSET_SZ 64
-#define MACSTAT_REV80_OFFSET_SZ 118
-
-/* ucode macstat txfunflw offset */
-#define UCODEMSTAT_TXFUNFL_BLK ((0x70 * 2) + (0x76 * 2))
-
-/* MACSTAT offset to SHM address */
-#define MACSTAT_ADDR(x, offset) (M_PSM2HOST_STATS(x) + (offset))
-
-/** ucode mac statistic counters in shared memory, base addr defined in M_UCODE_MACSTAT1 */
-typedef struct macstat1 {
- uint16 txndpa; /* + 0 (0x0) */
- uint16 txndp; /* + 1*2 (0x2) */
- uint16 txsf; /* + 2*2 (0x4) */
- uint16 txcwrts; /* + 3*2 (0x6) */
- uint16 txcwcts; /* + 4*2 (0x8) */
- uint16 txbfm; /* + 5*2 (0xa) */
- uint16 rxndpaucast; /* + 6*2 (0xc) */
- uint16 bferptrdy; /* + 7*2 (0xe) */
- uint16 rxsfucast; /* + 8*2 (0x10) */
- uint16 rxcwrtsucast; /* + 9*2 (0x12) */
- uint16 rxcwctsucast; /* +10*2 (0x14) */
- uint16 rx20s; /* +11*2 (0x16) */
- uint16 bcntrim; /* +12*2 (0x18) */
- uint16 btc_rfact_l; /* +13*2 (0x1a) */
- uint16 btc_rfact_h; /* +14*2 (0x1c) */
- uint16 btc_txconf_l; /* +15*2 (0x1e) : cnt */
- uint16 btc_txconf_h; /* +16*2 (0x20) : cnt */
- uint16 btc_txconf_durl; /* +17*2 (0x22) : dur */
- uint16 btc_txconf_durh; /* +18*2 (0x24) : dur */
- uint16 rxsecrssi0; /* +19*2 (0x26) : high bin */
- uint16 rxsecrssi1; /* +20*2 (0x28) : med bin */
- uint16 rxsecrssi2; /* +21*2 (0x2a) : low bin */
- uint16 rxpri_durl; /* +22*2 (0x2c) : dur */
- uint16 rxpri_durh; /* +23*2 (0x2e) : dur */
- uint16 rxsec20_durl; /* +24*2 (0x30) : dur */
- uint16 rxsec20_durh; /* +25*2 (0x32) : dur */
- uint16 rxsec40_durl; /* +26*2 (0x34) : dur */
- uint16 rxsec40_durh; /* +27*2 (0x36) : dur */
-} macstat1_t;
-
-#define MX_UCODEX_MACSTAT (0x40 * 2)
-/* ucodex mac statistic counters in shared memory */
-#define MACXSTAT_OFFSET_SZ 6
-
-/* psm2 statistic counters in shared memory, base addr defined in MX_PSM2HOST_STATS */
-typedef enum {
- MCXSTOFF_MACXSUSP = 0,
- MCXSTOFF_M2VMSG = 1,
- MCXSTOFF_V2MMSG = 2,
- MCXSTOFF_MBOXOUT = 3,
- MCXSTOFF_MUSND = 4,
- MCXSTOFF_SFB2V = 5
-} macxstat_offset_t;
-
-/* dot11 core-specific control flags */
-#define SICF_MCLKE 0x0001 /* Mac core clock Enable */
-#define SICF_FCLKON 0x0002 /* Force clocks On */
-#define SICF_PCLKE 0x0004 /**< PHY clock enable */
-#define SICF_PRST 0x0008 /**< PHY reset */
-#define SICF_MPCLKE 0x0010 /**< MAC PHY clockcontrol enable */
-#define SICF_FREF 0x0020 /**< PLL FreqRefSelect (corerev >= 5) */
-/* NOTE: the following bw bits only apply when the core is attached
- * to a NPHY (and corerev >= 11 which it will always be for NPHYs).
- */
-#ifdef SICF_160M_BWMASK_DEF
-#define SICF_BWMASK(macrev) (D11REV_GE(macrev, 86) ? 0x00e0 : 0x00c0) /**< phy clkmsk */
-#define SICF_BW160(macrev) (D11REV_GE(macrev, 86) ? 0x0080 : 0x00c0) /**< 160MHz BW */
-#define SICF_BW80(macrev) (D11REV_GE(macrev, 86) ? 0x0060 : 0x00c0) /**< 80MHz BW */
-#define SICF_BW40(macrev) (D11REV_GE(macrev, 86) ? 0x0040 : 0x0080) /**< 40MHz BW */
-#define SICF_BW20(macrev) (D11REV_GE(macrev, 86) ? 0x0020 : 0x0040) /**< 20MHz BW */
-#define SICF_BW10(macrev) (D11REV_GE(macrev, 86) ? 0x0000 : 0x0000) /**< 10MHz BW */
-#else
-#define SICF_BWMASK 0x00c0 /**< phy clock mask (b6 & b7) */
-#define SICF_BW160 0x00c0 /**< 160MHz BW */
-#define SICF_BW80 0x00c0 /**< 80MHz BW */
-#define SICF_BW40 0x0080 /**< 40MHz BW (160MHz phyclk) */
-#define SICF_BW20 0x0040 /**< 20MHz BW (80MHz phyclk) */
-#define SICF_BW10 0x0000 /**< 10MHz BW (40MHz phyclk) */
-#endif
-#define SICF_DAC 0x0300 /**< Highspeed DAC mode control field */
-#define SICF_GMODE 0x2000 /**< gmode enable */
-
-/* Macmode / Phymode / Opmode are used interchangebly sometimes
- * even though they all mean the same. Going ahead with the HW
- * signal name - using phymode here on (even though we know its
- * a misnomer). Applicable to d11 corerev >= 50 ---- ACPHY only
- */
-#define SICF_PHYMODE_SHIFT 16
-#define SICF_PHYMODE 0xf0000 /**< mask */
-
-#define SICF_160CLKSEL 0x100000u /* main phy clock speed selection */
-
-/* dot11 core-specific status flags */
-#define SISF_2G_PHY 0x0001 /**< 2.4G capable phy (corerev >= 5) */
-#define SISF_5G_PHY 0x0002 /**< 5G capable phy (corerev >= 5) */
-#define SISF_FCLKA 0x0004 /**< FastClkAvailable (corerev >= 5) */
-#define SISF_DB_PHY 0x0008 /**< Dualband phy (corerev >= 11) */
-
-/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
-
-/* Bits in phytest(0x0a): */
-#define TST_DDFS 0x2000
-#define TST_TXFILT1 0x0800
-#define TST_UNSCRAM 0x0400
-#define TST_CARR_SUPP 0x0200
-#define TST_DC_COMP_LOOP 0x0100
-#define TST_LOOPBACK 0x0080
-#define TST_TXFILT0 0x0040
-#define TST_TXTEST_ENABLE 0x0020
-#define TST_TXTEST_RATE 0x0018
-#define TST_TXTEST_PHASE 0x0007
-
-/* phytest txTestRate values */
-#define TST_TXTEST_RATE_1MBPS 0
-#define TST_TXTEST_RATE_2MBPS 1
-#define TST_TXTEST_RATE_5_5MBPS 2
-#define TST_TXTEST_RATE_11MBPS 3
-#define TST_TXTEST_RATE_SHIFT 3
-
-typedef struct shm_mbss_prq_entry_s shm_mbss_prq_entry_t;
-BWL_PRE_PACKED_STRUCT struct shm_mbss_prq_entry_s {
- struct ether_addr ta;
- uint8 prq_info[2];
- uint8 time_stamp;
- uint8 flags; /**< bit 0 HT STA Indication, bit 7:1 Reserved */
-} BWL_POST_PACKED_STRUCT;
-
-typedef enum shm_mbss_prq_ft_e {
- SHM_MBSS_PRQ_FT_CCK,
- SHM_MBSS_PRQ_FT_OFDM,
- SHM_MBSS_PRQ_FT_MIMO,
- SHM_MBSS_PRQ_FT_RESERVED
-} shm_mbss_prq_ft_t;
-
-#define SHM_MBSS_PRQ_FT_COUNT SHM_MBSS_PRQ_FT_RESERVED
-
-#define SHM_MBSS_PRQ_ENT_FRAMETYPE(entry) ((entry)->prq_info[0] & 0x3)
-#define SHM_MBSS_PRQ_ENT_UPBAND(entry) ((((entry)->prq_info[0] >> 2) & 0x1) != 0)
-
-/** What was the index matched? */
-#define SHM_MBSS_PRQ_ENT_UC_BSS_IDX(entry) (((entry)->prq_info[0] >> 2) & 0x3)
-#define SHM_MBSS_PRQ_ENT_PLCP0(entry) ((entry)->prq_info[1])
-
-/** Was this directed to a specific SSID or BSSID? If bit clear, quantity known */
-#define SHM_MBSS_PRQ_ENT_DIR_SSID(entry) \
- ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 1)
-#define SHM_MBSS_PRQ_ENT_DIR_BSSID(entry) \
- ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 2)
-
-#define SHM_MBSS_PRQ_ENT_TIMESTAMP(entry) ((entry)->time_stamp)
-/** Was the probe request from a ht STA or a legacy STA */
-#define SHM_MBSS_PRQ_ENT_HTSTA(entry) ((entry)->flags & 0x1)
-
-typedef struct d11ac_tso_s d11ac_tso_t;
-
-BWL_PRE_PACKED_STRUCT struct d11ac_tso_s {
- uint8 flag[3];
- uint8 sfh_hdr_offset;
- uint16 tso_mss; /**< tso segment size */
- uint16 msdu_siz; /**< msdu size */
- uint32 tso_payload_siz; /**< total byte cnt in tcp payload */
- uint16 ip_hdr_offset; /**< relative to the start of txd header */
- uint16 tcp_hdr_offset; /**< relative to start of txd header */
-} BWL_POST_PACKED_STRUCT;
-
-/* toe_ctl TCP offload engine register definitions */
-#define TOE_CTL_DISAB (1u << 0)
-#define TOE_CTL_MASK (1u << 0)
-#define TOE_CTL_ENAB (0xFFFEu)
-#define TOE_CLK_GATING_DISAB (1u << 1)
-
-#define TSO_HDR_TOE_FLAG_OFFSET (0u)
-
-#define TOE_F0_HDRSIZ_NORMAL (1u << 0)
-#define TOE_F0_PASSTHROUGH (1u << 1)
-#define TOE_F0_TCPSEG_EN (1u << 3)
-#define TOE_F0_IPV4 (1u << 4)
-#define TOE_F0_IPV6 (1u << 5)
-#define TOE_F0_TCP (1u << 6)
-#define TOE_F0_UDP (1u << 7)
-
-#define TOE_F1_IPV4_CSUM_EN (1u << 0)
-#define TOE_F1_TCPUDP_CSUM_EN (1u << 1)
-#define TOE_F1_PSEUDO_CSUM_EN (1u << 2)
-#define TOE_F1_FRAG_ALLOW (1u << 5)
-#define TOE_F1_FRAMETYPE_1 (1u << 6)
-#define TOE_F1_FRAMETYPE_2 (1u << 7)
-#define TOE_F1_FT_MASK (TOE_F1_FRAMETYPE_1 | TOE_F1_FRAMETYPE_2)
-#define TOE_F1_FT_SHIFT (6u)
-
-#define TOE_F2_TXD_HEAD_SHORT (1u << 0)
-#define TOE_F2_EPOCH_SHIFT (1u)
-#define TOE_F2_EPOCH (1u << TOE_F2_EPOCH_SHIFT)
-#define TOE_F2_EPOCH_EXT (1u << 2)
-#define TOE_F2_EPOCH_EXT_MASK (TOE_F2_EPOCH | TOE_F2_EPOCH_EXT)
-#define TOE_F2_AMSDU_AGGR_EN (1u << 4)
-#define TOE_F2_AMSDU_CSUM_EN (1u << 5)
-#define TOE_F2_AMSDU_FS_MID (1u << 6)
-#define TOE_F2_AMSDU_FS_LAST (1u << 7)
-
-#define TOE_TXDMA_FLAGS_AMSDU_FIRST (0x14u)
-#define TOE_TXDMA_FLAGS_AMSDU_MID (0x24u)
-#define TOE_TXDMA_FLAGS_AMSDU_LAST (0x34u)
-
-/* This marks the end of a packed structure section. */
-#include <packed_section_end.h>
-
-#define SHM_BYT_CNT 0x2 /**< IHR location */
-#define MAX_BYT_CNT 0x600 /**< Maximum frame len */
-
-/* WOWL Template Regions */
-#define WOWL_NS_CHKSUM (0x57 * 2)
-#define WOWL_PSP_TPL_BASE (0x334 * 2)
-#define WOWL_GTK_MSG2 (0x434 * 2)
-#define WOWL_NS_OFFLOAD (0x634 * 2)
-#define T_KEEPALIVE_0 (0x6b4 * 2)
-#define T_KEEPALIVE_1 ((0x6b4 + 0x40) * 2)
-#define WOWL_ARP_OFFLOAD (0x734 * 2)
-#define WOWL_TX_FIFO_TXRAM_BASE (0x774 * 2) /**< conservative, leave 1KB for GTKM2 */
-
-/* template regions for 11ac */
-#define D11AC_WOWL_PSP_TPL_BASE (0x4c0 * 2)
-#define D11AC_WOWL_GTK_MSG2 (0x5c0 * 2) /**< for core rev >= 42 */
-#define WOWL_NS_OFFLOAD_GE42 (0x7c0 * 2)
-#define T_KEEPALIVE_0_GE42 (0x840 * 2)
-#define T_KEEPALIVE_1_GE42 ((0x840 + 0x40) * 2)
-#define WOWL_ARP_OFFLOAD_GE42 (0x8c0 * 2)
-#define D11AC_WOWL_TX_FIFO_TXRAM_BASE (0x900 * 2) /**< GTKM2 for core rev >= 42 */
-
-/* Event definitions */
-#define WOWL_MAGIC (1 << 0) /**< Wakeup on Magic packet */
-#define WOWL_NET (1 << 1) /**< Wakeup on Netpattern */
-#define WOWL_DIS (1 << 2) /**< Wakeup on loss-of-link due to Disassoc/Deauth */
-#define WOWL_RETR (1 << 3) /**< Wakeup on retrograde TSF */
-#define WOWL_BCN (1 << 4) /**< Wakeup on loss of beacon */
-#define WOWL_TST (1 << 5) /**< Wakeup after test */
-#define WOWL_M1 (1 << 6) /**< Wakeup after PTK refresh */
-#define WOWL_EAPID (1 << 7) /**< Wakeup after receipt of EAP-Identity Req */
-#define WOWL_PME_GPIO (1 << 8) /**< Wakeind via PME(0) or GPIO(1) */
-#define WOWL_NEEDTKIP1 (1 << 9) /**< need tkip phase 1 key to be updated by the driver */
-#define WOWL_GTK_FAILURE (1 << 10) /**< enable wakeup if GTK fails */
-#define WOWL_EXTMAGPAT (1 << 11) /**< support extended magic packets */
-#define WOWL_ARPOFFLOAD (1 << 12) /**< support ARP/NS offloading */
-#define WOWL_WPA2 (1 << 13) /**< read protocol version for EAPOL frames */
-#define WOWL_KEYROT (1 << 14) /**< If the bit is set, use key rotaton */
-#define WOWL_BCAST (1 << 15) /**< If the bit is set, frm received was bcast frame */
-
-#define MAXBCNLOSS (1 << 13) - 1 /**< max 12-bit value for bcn loss */
-
-/* UCODE shm view:
- * typedef struct {
- * uint16 offset; // byte offset
- * uint16 patternsize; // the length of value[.] in bytes
- * uchar bitmask[MAXPATTERNSIZE/8]; // 16 bytes, the effect length is (patternsize+7)/8
- * uchar value[MAXPATTERNSIZE]; // 128 bytes, the effect length is patternsize.
- * } netpattern_t;
- */
-#define NETPATTERNSIZE (148) /* 128 value + 16 mask + 4 offset + 4 patternsize */
-#define MAXPATTERNSIZE 128
-#define MAXMASKSIZE MAXPATTERNSIZE/8
-
-/** Security Algorithm defines */
-#define WOWL_TSCPN_SIZE 6
-#define WOWL_TSCPN_COUNT 4 /**< 4 ACs */
-#define WOWL_TSCPN_BLK_SIZE (WOWL_TSCPN_SIZE * WOWL_TSCPN_COUNT)
-
-#define WOWL_SECSUITE_GRP_ALGO_MASK 0x0007
-#define WOWL_SECSUITE_GRP_ALGO_SHIFT 0
-#define WOWL_SECSUITE_ALGO_MASK 0x0700
-#define WOWL_SECSUITE_ALGO_SHIFT 8
-
-#define EXPANDED_KEY_RNDS 10
-#define EXPANDED_KEY_LEN 176 /* the expanded key from KEK (4*11*4, 16-byte state, 11 rounds) */
-
-/* Organization of Template RAM is as follows
- * typedef struct {
- * uint8 AES_XTIME9DBE[1024];
- * uint8 AES_INVSBOX[256];
- * uint8 AES_KEYW[176];
- * } AES_TABLES_t;
- */
-/* See dot11_firmware/diag/wmac_tcl/wmac_762_wowl_gtk_aes: proc write_aes_tables,
- * for an example of writing those tables into the tx fifo buffer.
- */
-
-typedef struct {
- uint16 MacTxControlLow; /**< mac-tx-ctl-low word */
- uint16 MacTxControlHigh; /**< mac-tx-ctl-high word */
- uint16 PhyTxControlWord; /**< phy control word */
- uint16 PhyTxControlWord_1; /**< extra phy control word for mimophy */
- union {
- uint16 XtraFrameTypes; /**< frame type for RTS/FRAG fallback (used only for AES) */
- uint16 bssenc_pos; /**< BssEnc includes key ID , for corerev >= 42 */
- } u1;
- uint8 plcp[6]; /**< plcp of template */
-
- uint16 mac_frmtype; /**< MAC frame type for GTK MSG2, can be
- * dot11_data frame (0x20) or dot11_QoS_Data frame (0x22).
- */
- uint16 frm_bytesize; /**< number of bytes in the template, it includes:
- * PLCP, MAC header, IV/EIV, the data payload
- * (eth-hdr and EAPOL-Key), TKIP MIC
- */
- uint16 payload_wordoffset; /**< the word offset of the data payload */
-
- /* ALIGN */
- uint16 seqnum; /**< Sequence number for this frame */
- uint8 seciv[18]; /**< 10-byte TTAK used for TKIP, 8-byte IV/EIV.
- * See <SecurityInitVector> in the general tx descriptor.
- */
-} wowl_templ_ctxt_t;
-
-#define WOWL_TEMPL_CTXT_LEN 42 /**< For making sure that no PADs are needed */
-#define WOWL_TEMPL_CTXT_FRMTYPE_DATA 0x2
-#define WOWL_TEMPL_CTXT_FRMTYPE_QOS 0x22
-
-/** constant tables required for AES key unwrapping for key rotation */
-extern uint16 aes_invsbox[128];
-extern uint16 aes_xtime9dbe[512];
-
-#define MAX_MPDU_SPACE (D11_TXH_LEN + 1538)
-
-/* Bits in TXE_BMCCTL */
-#define BMCCTL_INITREQ_SHIFT 0
-#define BMC_CTL_DONE (1 << BMCCTL_INITREQ_SHIFT)
-#define BMCCTL_RESETSTATS_SHIFT 1
-#define BMCCTL_TXBUFSIZE_SHIFT 2
-#define BMCCTL_LOOPBACK_SHIFT 5
-#define BMCCTL_TXBUFSZ_MASK ((1 << BMCCTL_LOOPBACK_SHIFT) - (1 << BMCCTL_TXBUFSIZE_SHIFT))
-#define BMCCTL_CLKGATEEN_SHIFT 8
-
-/* Bits in TXE_BMCConfig */
-#define BMCCONFIG_BUFCNT_SHIFT 0
-#define BMCCONFIG_DISCLKGATE_SHIFT 13
-#define BMCCONFIG_BUFCNT_MASK ((1 << BMCCONFIG_DISCLKGATE_SHIFT) - (1 << BMCCONFIG_BUFCNT_SHIFT))
-
-/* Bits in TXE_BMCStartAddr */
-#define BMCSTARTADDR_STRTADDR_MASK 0x3ff
-
-/* Bits in TXE_BMCDescrLen */
-#define BMCDescrLen_ShortLen_SHIFT 0
-#define BMCDescrLen_LongLen_SHIFT 8
-
-/* Bits in TXE_BMCAllocCtl */
-#define BMCAllocCtl_AllocCount_SHIFT 0
-/* Rev==50 || Rev>52
-* BMCAllocCtl.AllocCount [0:10]
-* BMCAllocCtl.AllocThreshold [11:14]
-* !Rev50
-* BMCAllocCtl.AllocCount [0:7]
-* BMCAllocCtl.AllocThreshold [8:15]
-*/
-#define BMCAllocCtl_AllocThreshold_SHIFT_Rev50 11
-#define BMCAllocCtl_AllocThreshold_SHIFT 8
-
-/* Bits in TXE_BMCCmd1 */
-#define BMCCMD1_TIDSEL_SHIFT 1
-#define BMCCMD1_RDSRC_SHIFT 6
-#define BMCCmd1_RXMapPassThru_SHIFT 12
-#define BMCCMD1_BQSelNum_SHIFT 1u
-#define BMCCMD1_BQSelType_SHIFT 7u
-#define BMCCMD1_RDSRC_Group0 0u /* register itself */
-#define BMCCMD1_RDSRC_Group1 1u /* staged max/min */
-#define BMCCMD1_RDSRC_Group2 2u /* staged max/previous min */
-#define BMCCMD1_RDSRC_Group3 3u /* active max/min */
-#define BMCCMD1_RDSRC_SHIFT_rev80 10u
-#define BMCCMD1_CoreSel_SHIFT 13u
-#define BMCCMD1_CoreSel_SHIFT_rev80 15u
-
-/* Bits in TXE_BMCCmd */
-#define BMCCmd_TIDSel_SHIFT 0
-#define BMCCmd_Enable_SHIFT 4
-#define BMCCmd_ReleasePreAlloc_SHIFT 5
-#define BMCCmd_ReleasePreAllocAll_SHIFT 6
-#define BMCCmd_UpdateBA_SHIFT 7
-#define BMCCmd_Consume_SHIFT 8
-#define BMCCmd_Aggregate_SHIFT 9
-#define BMCCmd_UpdateRetryCount_SHIFT 10
-#define BMCCmd_DisableTID_SHIFT 11
-
-#define BMCCmd_BQSelType_TX 0
-#define BMCCmd_BQSelType_RX 1
-#define BMCCmd_BQSelType_Templ 2
-
-/* Bits in TXE_BMCCMD for rev >= 80 */
-#define BMCCmd_BQSelType_MASK_Rev80 0x00c0
-#define BMCCmd_BQSelType_SHIFT_Rev80 6
-#define BMCCmd_Enable_SHIFT_rev80 8
-#define BMCCmd_ReleasePreAllocAll_SHIFT_rev80 10
-
-/* Bits in TXE_BMCCmd1 */
-#define BMCCmd1_Minmaxappall_SHIFT 0
-#define BMCCmd1_Minmaxlden_SHIFT 5
-#define BMCCmd1_Minmaxffszlden_SHIFT 8
-#define BMCCmd_Core1_Sel_MASK 0x2000
-
-/* Bits in TXE_BMCStatCtl */
-#define BMCStatCtl_TIDSel_SHIFT 0u
-#define BMCStatCtl_STATSel_SHIFT 4u
-#define BMCStatCtl_BQSelNum_SHIFT 0u
-#define BMCStatCtl_BQSelType_SHIFT 6u
-#define BMCStatCtl_STATSel_SHIFT_rev80 8u
-
-/* Bits in BMVpConfig */
-#define BMCVPConfig_SingleVpModePortA_SHIFT 4
-
-/* Bits in TXE_PsmMSDUAccess */
-#define PsmMSDUAccess_TIDSel_SHIFT 0
-#define PsmMSDUAccess_MSDUIdx_SHIFT 4
-#define PsmMSDUAccess_ReadBusy_SHIFT 14
-#define PsmMSDUAccess_WriteBusy_SHIFT 15
-
-/* Bits in TXE_PsmMSDUAccess for rev >= 80 */
-#define PsmMSDUAccess_BQSelType_SHIFT 5
-#define PsmMSDUAccess_MSDUIdx_SHIFT_rev80 7
-#define PsmMSDUAccess_BQSelType_Templ 2
-#define PsmMSDUAccess_BQSelType_TX 0
-
-#ifdef WLRSDB
-#define MAX_RSDB_MAC_NUM 2
-#else
-#define MAX_RSDB_MAC_NUM 1
-#endif
-#define MAX_MIMO_MAC_NUM 1
-
-#ifdef WL_SCAN_CORE
-#define MAX_MAC_CORE_NUM (MAX_RSDB_MAC_NUM + 1)
-#else
-#define MAX_MAC_CORE_NUM (MAX_RSDB_MAC_NUM)
-#endif /* WL_SCAN_CORE */
-
-#define MAC_CORE_UNIT_0 0x0u /**< First mac core unit */
-#define MAC_CORE_UNIT_1 0x1u /**< Second mac core unit */
-
-/* HW unit of scan core.
- * This is used to overwrite the tunables specific to scan core
- */
-#define SCAN_CORE_UNIT 0x2u
-
-/* Supported phymodes / macmodes / opmodes */
-#define SINGLE_MAC_MODE 0x0 /**< only single mac is enabled */
-#define DUAL_MAC_MODE 0x1 /**< enables dual mac */
-/* (JIRA: CRDOT11ACPHY-652) Following two #defines support
- * exclusive reg access to core 0/1 in MIMO mode
- */
-#define SUPPORT_EXCLUSIVE_REG_ACCESS_CORE0 0x2
-#define SUPPORT_EXCLUSIVE_REG_ACCESS_CORE1 0x4 /**< not functional in 4349A0 */
-#define SUPPORT_CHANNEL_BONDING 0x8 /**< enables channel bonding,
- * supported in single mac mode only
- */
-#define SCAN_CORE_ACTIVE 0x10 /* scan core enabled for background DFS */
-
-#define PHYMODE_MIMO (SINGLE_MAC_MODE)
-#define PHYMODE_80P80 (SINGLE_MAC_MODE | SUPPORT_CHANNEL_BONDING)
-#define PHYMODE_RSDB_SISO_0 (DUAL_MAC_MODE | SUPPORT_EXCLUSIVE_REG_ACCESS_CORE0)
-#define PHYMODE_RSDB_SISO_1 (DUAL_MAC_MODE | SUPPORT_EXCLUSIVE_REG_ACCESS_CORE1)
-#define PHYMODE_RSDB (PHYMODE_RSDB_SISO_0 | PHYMODE_RSDB_SISO_1)
-#define PHYMODE_BGDFS 31
-#define PHYMODE_3x3_1x1 31
-
-#define RX_INTR_FIFO_0 0x1 /**< FIFO-0 interrupt */
-#define RX_INTR_FIFO_1 0x2 /**< FIFO-1 interrupt */
-#define RX_INTR_FIFO_2 0x4 /**< FIFO-2 interrupt */
-
-#define MAX_RX_FIFO 3
-
-#define RX_CTL_FIFOSEL_SHIFT 8
-#define RX_CTL_FIFOSEL_MASK (0x3 << RX_CTL_FIFOSEL_SHIFT)
-
-#define RCO_EN (0x1u) /**< Receive checksum offload */
-
-/* MAC_PTM_CTRL1 bit definitions */
-#define PTM_RX_TMSTMP_CAPTURE_EN 0x0001u
-#define PTM_TX_TMSTMP_CAPTURE_EN 0x0001u
-#define PTM_TMSTMP_OVERRIDE_EN 0x1000u
-
-/* For corerev >= 64
- * Additional DMA descriptor flags for AQM Descriptor. These are used in
- * conjunction with the descriptor control flags defined in sbhnddma.h
- */
-/* AQM DMA Descriptor control flags 1 */
-#define D64_AQM_CTRL1_SOFPTR 0x0000FFFF /* index of the descr which
- * is SOF decriptor in DMA table
- */
-#define D64_AQM_CTRL1_EPOCH 0x00010000 /* Epoch bit for the frame */
-#define D64_AQM_CTRL1_NUMD_MASK 0x00F00000 /* NumberofDescriptors(NUMD) */
-#define D64_AQM_CTRL1_NUMD_SHIFT 20
-#define D64_AQM_CTRL1_AC_MASK 0x0F000000 /* AC of the current frame */
-#define D64_AQM_CTRL1_AC_SHIFT 24
-
-/* AQM DMA Descriptor control flags 2 */
-#define D64_AQM_CTRL2_MPDULEN_MASK 0x00003FFF /* Length of the entire MPDU */
-#define D64_AQM_CTRL2_TXDTYPE 0x00080000 /* When set to 1 the long form of the
- * TXD is used for the frame.
- */
-/* For corerev >= 83
- * DMA descriptor flags for AQM Descriptor. These are used in
- * conjunction with the descriptor control flags defined in sbhnddma.h
- */
-/* AQM DMA Descriptor control flags 1 */
-#define D11_REV83_AQM_DESC_CTRL1_SOFPTR 0x0000FFFFu /* index of the descr which
- * is SOF decriptor in DMA table
- */
-#define D11_REV83_AQM_DESC_CTRL1_EPOCH_SHIFT 16u
-#define D11_REV83_AQM_DESC_CTRL1_EPOCH (1u << D11_REV83_AQM_DESC_CTRL1_EPOCH_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT_SHIFT 17u
-#define D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT (1u << \
- D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL1_EPOCH_MASK (D11_REV83_AQM_DESC_CTRL1_EPOCH | \
- D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT)
-#define D11_REV83_AQM_DESC_CTRL1_RESV1 0x00040000u /* RESERVED */
-#define D11_REV83_AQM_DESC_CTRL1_FRAGALLOW_SHIFT 19u /* Fragmentation allowance flag
- * shift.
- */
-#define D11_REV83_AQM_DESC_CTRL1_FRAGALLOW (1u << D11_REV83_AQM_DESC_CTRL1_FRAGALLOW_SHIFT)
- /* Fragmentation allowance flag
- * of the frame
- */
-#define D11_REV83_AQM_DESC_CTRL1_NUMD_SHIFT 20u /* NumberofDescriptors(NUMD) */
-#define D11_REV83_AQM_DESC_CTRL1_NUMD_MASK (0xFu << D11_REV83_AQM_DESC_CTRL1_NUMD_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL1_AC_SHIFT 24u /* AC of the current frame */
-#define D11_REV83_AQM_DESC_CTRL1_AC_MASK (0xFu << D11_REV83_AQM_DESC_CTRL1_AC_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL1_ET 0x10000000u /* End of table */
-#define D11_REV83_AQM_DESC_CTRL1_IC 0x20000000u /* Interrupt on Completion */
-#define D11_REV83_AQM_DESC_CTRL1_RESV2 0x40000000u /* Used to be EF: End of frame,
- * and would have been set to 1.
- */
-#define D11_REV83_AQM_DESC_CTRL1_RESV3 0x80000000u /* Used to be SF: Start of Frame,
- * and would have been set to 1
- */
-
-/* AQM DMA Descriptor control flags 2 */
-#define D11_REV83_AQM_DESC_CTRL2_MPDULEN_MASK 0x00003FFFu /* Length of the entire MPDU */
-#define D11_REV83_AQM_DESC_CTRL2_FTYPE_SHIFT 14u /* Frame Type, Indicate whether
- * frame is Data, Management or
- * Control Frame. 2 bits:
- * 2'b00=Data, 2'b01=Management,
- * 2'b10=Control, 2'b11=Invalid
- * value
- */
-#define D11_REV83_AQM_DESC_CTRL2_FTYPE_MASK (0x3u << D11_REV83_AQM_DESC_CTRL2_FTYPE_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_SHIFT 16u /* pTxD length index in 4-deep table */
-#define D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_MASK (0x3u << \
- D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL2_PT 0x00040000u /* Parity bit. Choose a
- * value such that the entire
- * descriptor haseven parity
- */
-#define D11_REV83_AQM_DESC_CTRL2_USERIT 0x00080000u /* If set, the Rate Table Index and
- * RIT entry are fetched into SHM by
- * hardware. Otherwise, software
- * uses pTxD to convey this
- * information to ucode
- */
-#define D11_REV83_AQM_DESC_CTRL2_USELIT 0x00100000u /* If set, the Link Info Table Index
- * and LIT entry are fetched into
- * SHM by hardware. Otherwise,
- * software uses pTxD to convey this
- * information to ucode
- */
-#define D11_REV83_AQM_DESC_CTRL2_LIT_SHIFT 21u /* LTI(Link info Table Index) */
-#define D11_REV83_AQM_DESC_CTRL2_LIT_MASK (0x3Fu << D11_REV83_AQM_DESC_CTRL2_LIT_SHIFT)
-#define D11_REV83_AQM_DESC_CTRL2_RIT_SHIFT 27u /* bit[4:0] of RTI(Rate info Table Index) */
-#define D11_REV83_AQM_DESC_CTRL2_RIT_MASK (0x1Fu << D11_REV83_AQM_DESC_CTRL2_RIT_SHIFT)
-
-/* AQM DMA Descriptor control flags 3 */
-#define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5 0x00000001u /* bit[5] of RTI (cont'd from ctrl2) */
-#define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5_MASK 1u /* bit[5] of RTI (cont'd from ctrl2) */
-#define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5_SHIFT 0u
-#define D11_REV83_AQM_DESC_CTRL3_AGGR_ID 0x0000000Eu /* Aggregation ID */
-#define D11_REV83_AQM_DESC_CTRL3_CO 0x00000010u /* Coherency */
-#define D11_REV84_AQM_DESC_CTRL3_TXDPTR_SHIFT 5u /* TxD ptr */
-#define D11_REV84_AQM_DESC_CTRL3_TXDPTR_MASK 0xFFFFFFu /* bit[23:0] of TxD addr */
-#define D11_REV86_AQM_DESC_CTRL3_TID_SHIFT 29u /* TID for BSR */
-#define D11_REV86_AQM_DESC_CTRL3_TID_MASK (0x7u << D11_REV86_AQM_DESC_CTRL3_TID_SHIFT)
-
-/* values for psm_patchcopy_ctrl (0x1AC) post corerev 60 */
-#define PSM_PATCHCC_PMODE_MASK (0x3)
-#define PSM_PATCHCC_PMODE_RAM (0) /* default */
-#define PSM_PATCHCC_PMODE_ROM_RO (1)
-#define PSM_PATCHCC_PMODE_ROM_PATCH (2)
-
-#define PSM_PATCHCC_PENG_TRIGGER_SHIFT (2)
-#define PSM_PATCHCC_PENG_TRIGGER_MASK (1 << PSM_PATCHCC_PENG_TRIGGER_SHIFT)
-#define PSM_PATCHCC_PENG_TRIGGER (1 << PSM_PATCHCC_PENG_TRIGGER_SHIFT)
-
-#define PSM_PATCHCC_PCTRL_RST_SHIFT (3)
-#define PSM_PATCHCC_PCTRL_RST_MASK (0x3 << PSM_PATCHCC_PCTRL_RST_SHIFT)
-#define PSM_PATCHCC_PCTRL_RST_RESET (0x0 << PSM_PATCHCC_PCTRL_RST_SHIFT)
-#define PSM_PATCHCC_PCTRL_RST_HW (0x1 << PSM_PATCHCC_PCTRL_RST_SHIFT)
-
-#define PSM_PATCHCC_COPYEN_SHIFT (5)
-#define PSM_PATCHCC_COPYEN_MASK (1 << PSM_PATCHCC_COPYEN_SHIFT)
-#define PSM_PATCHCC_COPYEN (1 << PSM_PATCHCC_COPYEN_SHIFT)
-
-#define PSM_PATCHCC_UCIMGSEL_SHIFT (16)
-#define PSM_PATCHCC_UCIMGSEL_MASK (0x30000)
-#define PSM_PATCHCC_UCIMGSEL_DS0 (0x00000) /* default image */
-#define PSM_PATCHCC_UCIMGSEL_DS1 (0x10000) /* image 1 */
-
-/* patch copy delay for psm: 2millisec */
-#define PSM_PATCHCOPY_DELAY (2000)
-
-/* START-below WAS in d11_if_shm.h which we can move to auto shm.
- * Some of them are offsets, but some of them are not given by ucode [possibly legacy]
- * so, not taken care by autoshm.
- */
-
-/* Addr is byte address used by SW; offset is word offset used by uCode */
-
-/** Per AC TX limit settings */
-#define M_AC_TXLMT_ADDR(x, _ac) (M_AC_TXLMT_BLK(x) + (2 * (_ac)))
-
-/** delay from end of PLCP reception to RxTSFTime */
-#define M_APHY_PLCPRX_DLY 3
-#define M_BPHY_PLCPRX_DLY 4
-
-/* btcx debug shmem size */
-#define C_BTCX_DBGBLK_SZ 6 /**< Number of 16bit words */
-#define C_BTCX_DBGBLK2_SZ 11 /* size of statistics at 2nd SHM segment */
-
-#define C_BTCX_STATS_DBGBLK_SZ 18 /* total size of statistics at A2DP stats */
-#define C_BTCX_A2DP_PRI_SZ 6 /* size of a2dp priority counters stats */
-#define C_BTCX_A2DP_BUFCNT_SZ 8 /* size of a2dp buffer counters stats */
-#define C_BTCX_ANT_GRANT_SZ 4 /* size of ant granted duration to BT */
-#define C_BTCX_STATS_ECNTR_BLK_SZ C_BTCX_STATS_DBGBLK_SZ /* blk size for btcx ecounters */
-
-#define D11_DMA_CHANNELS 6
-
-/* WME shared memory */
-#define M_EDCF_STATUS_OFF(x) (0x007 * 2)
-
-/* Beacon-related parameters */
-#define M_BCN_LI(x) M_PS_MORE_DTIM_TBTT(x) /**< beacon listen interval */
-
-/* prerev 40 defines */
-#define D11_PRE40_M_SECKINDXALGO_BLK(x) (0x2ea * 2)
-
-/* corerev 40 defines */
-/* BLK SIZE needs to change for GE64 */
-#define D11_POST80_MAX_KEY_SIZE 32
-#define D11_PRE80_MAX_KEY_SIZE 16
-
-#define D11_MAX_KEY_SIZE(_corerev) ((D11REV_GE(_corerev, 80)) ? \
- D11_POST80_MAX_KEY_SIZE : D11_PRE80_MAX_KEY_SIZE)
-
-#define M_SECKINDXALGO_BLK_SZ(_corerev) (AMT_SIZE(_corerev) + 4 /* default keys */)
-
-#define C_CTX_PCTLWD_POS (0x4 * 2)
-
-#define D11_MAX_TX_FRMS 32 /**< max frames allowed in tx fifo */
-
-/* Current channel number plus upper bits */
-#define D11_CURCHANNEL_5G 0x0100;
-#define D11_CURCHANNEL_40 0x0200;
-#define D11_CURCHANNEL_MAX 0x00FF;
-
-#define INVALIDFID 0xffff
-
-#define D11_RT_DIRMAP_SIZE 16
-
-/** Rate table entry offsets */
-#define M_RT_PRS_PLCP_POS(x) 10
-#define M_RT_PRS_DUR_POS(x) 16
-#define M_RT_OFDM_PCTL1_POS(x) 18
-#define M_RT_TXPWROFF_POS(x) 20
-#define M_REV40_RT_TXPWROFF_POS(x) 14
-
-#define MIMO_MAXSYM_DEF 0x8000 /* 32k */
-#define MIMO_MAXSYM_MAX 0xffff /* 64k */
-
-#define WATCHDOG_8TU_DEF_LT42 5
-#define WATCHDOG_8TU_MAX_LT42 10
-#define WATCHDOG_8TU_DEF 3
-#define WATCHDOG_8TU_MAX 4
-
-#define M_PKTENG_RXAVGPWR_ANT(x, w) (M_MFGTEST_RXAVGPWR_ANT0(x) + (w) * 2)
-
-/* M_MFGTEST_NUM (pkt eng) bit definitions */
-#define MFGTEST_TXMODE 0x0001 /* TX frames indefinitely */
-#define MFGTEST_RXMODE 0x0002 /* RX frames */
-#define MFGTEST_RXMODE_ACK 0x0402 /* RX frames with sending ACKs back */
-#define MFGTEST_RXMODE_FWD2FW 0x8000 /* RX frames - forward packet to the fw */
-#define MFGTEST_TXMODE_FRMCNT 0x0101 /* TX frames by frmcnt */
-#define MFGTEST_RU_TXMODE 0x0011 /* RU frames TX indefinetly */
-#define MFGTEST_RU_TXMODE_FRMCNT 0x0111 /* RU TX frames by frmcnt */
-
-/* UOTA interface bit definitions */
-enum {
- C_UOTA_CNTSRT_NBIT = 0, /* 0 OTA rx frame count start bit (14 LSB's) */
- C_UOTA_RXFST_NBIT = 14, /* 14 indicating first frame */
- C_UOTA_RSSION_NBIT = 15, /* 15 OTA rx ON bit position */
-};
-
-#define M_EDCF_QLEN(x) (M_EDCF_QINFO1_OFFSET(x))
-#define M_PWRIND_MAP(x, core) (M_PWRIND_BLKS(x) + ((core)<<1))
-
-#define M_BTCX_MAX_INDEX 320u
-#define M_BTCX_BACKUP_SIZE 130
-#define BTCX_AMPDU_MAX_DUR 2500
-
-#define ADDR_STAMON_NBIT (1 << 10) /* STA monitor bit in AMT_INFO_BLK entity */
-
-#ifdef WLP2P_UCODE
-
-/** The number of scheduling blocks */
-#ifdef BCMFUZZ /* need more for fuzzing */
-#define M_P2P_BSS_MAX 8
-#else
-#define M_P2P_BSS_MAX 4
-#endif /* BCMFUZZ */
-
-/** WiFi P2P interrupt block positions */
-#define M_P2P_I_BLK_SZ 4
-#define M_P2P_I_BLK_OFFSET(x) (M_P2P_INTR_BLK(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_I_BLK(x, b) (M_P2P_I_BLK_OFFSET(x) + (M_P2P_I_BLK_SZ * (b) * 2))
-#define M_P2P_I(x, b, i) (M_P2P_I_BLK(x, b) + ((i) * 2))
-
-#define M_P2P_I_PRE_TBTT 0 /**< pretbtt, wake up just before beacon reception */
-#define M_P2P_I_CTW_END 1 /**< CTWindow ends */
-#define M_P2P_I_ABS 2 /**< absence period start, trigger for switching channels */
-#define M_P2P_I_PRS 3 /**< presence period starts */
-
-/** P2P hps flags */
-#define M_P2P_HPS_CTW(b) (1 << (b))
-#define M_P2P_HPS_NOA(b) (1 << ((b) + M_P2P_BSS_MAX))
-
-/** WiFi P2P address attribute block */
-#define M_ADDR_BMP_BLK_SZ 12
-#define M_ADDR_RANDMAC_BMP_BLK_SZ 40u
-
-#define M_ADDR_BMP_BLK(x, b) (M_ADDR_BMP_BLK_OFFSET(x) + ((b) * 2))
-
-#define ADDR_BMP_RA (1 << 0) /**< Receiver Address (RA) */
-#define ADDR_BMP_TA (1 << 1) /**< Transmitter Address (TA) */
-#define ADDR_BMP_BSSID (1 << 2) /**< BSSID */
-#define ADDR_BMP_AP (1 << 3) /**< Infra-BSS Access Point (AP) */
-#define ADDR_BMP_STA (1 << 4) /**< Infra-BSS Station (STA) */
-#define ADDR_BMP_P2P_DISC (1 << 5) /**< P2P Device */
-#define ADDR_BMP_P2P_GO (1 << 6) /**< P2P Group Owner */
-#define ADDR_BMP_P2P_GC (1 << 7) /**< P2P Client */
-#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /**< BSS control block index */
-#define ADDR_BMP_BSS_IDX_SHIFT 8
-
-/** WiFi P2P address starts from this entry in RCMTA */
-#define P2P_ADDR_STRT_INDX (RCMTA_SIZE - M_ADDR_BMP_BLK_SZ)
-
-/* WiFi P2P per BSS control block positions.
- * all time related fields are in units of (1<<P2P_UCODE_TIME_SHIFT)us unless noted otherwise.
- */
-
-#define P2P_UCODE_TIME_SHIFT 7
-#define M_P2P_BSS_BLK_SZ 12
-#define M_P2P_BSS_BLK_OFFSET(x) (M_P2P_PERBSS_BLK(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_BSS_BLK(x, b) (M_P2P_BSS_BLK_OFFSET(x) + (M_P2P_BSS_BLK_SZ * (b) * 2))
-#define M_P2P_BSS(x, b, p) (M_P2P_BSS_BLK(x, b) + (p) * 2)
-#define M_P2P_BSS_BCN_INT(x, b) (M_P2P_BSS_BLK(x, b) + (0 * 2)) /**< beacon interval */
-#define M_P2P_BSS_DTIM_PRD(x, b) (M_P2P_BSS_BLK(x, b) + (1 * 2)) /**< DTIM period */
-#define M_P2P_BSS_ST(x, b) (M_P2P_BSS_BLK(x, b) + (2 * 2)) /**< current state */
-#define M_P2P_BSS_N_PRE_TBTT(x, b) (M_P2P_BSS_BLK(x, b) + (3 * 2)) /**< next pretbtt time */
-#define M_P2P_BSS_CTW(x, b) (M_P2P_BSS_BLK(x, b) + (4 * 2)) /**< CTWindow duration */
-#define M_P2P_BSS_N_CTW_END(x, b) (M_P2P_BSS_BLK(x, b) + (5 * 2)) /**< next CTWindow end */
-#define M_P2P_BSS_NOA_CNT(x, b) (M_P2P_BSS_BLK(x, b) + (6 * 2)) /**< NoA count */
-#define M_P2P_BSS_N_NOA(x, b) (M_P2P_BSS_BLK(x, b) + (7 * 2)) /**< next absence time */
-#define M_P2P_BSS_NOA_DUR(x, b) (M_P2P_BSS_BLK(x, b) + (8 * 2)) /**< absence period */
-#define M_P2P_BSS_NOA_TD(x, b) (M_P2P_BSS_BLK(x, b) + (9 * 2))
- /**< presence period (int - dur) */
-#define M_P2P_BSS_NOA_OFS(x, b) (M_P2P_BSS_BLK(x, b) + (10 * 2))
- /* last 7 bits of interval in us */
-#define M_P2P_BSS_DTIM_CNT(x, b) (M_P2P_BSS_BLK(x, b) + (11 * 2))
- /**< DTIM count */
-
-/* M_P2P_BSS_ST word positions. */
-#define M_P2P_BSS_ST_CTW (1 << 0) /**< BSS is in CTWindow */
-#define M_P2P_BSS_ST_SUPR (1 << 1) /**< BSS is suppressing frames */
-#define M_P2P_BSS_ST_ABS (1 << 2) /**< BSS is in absence period */
-#define M_P2P_BSS_ST_WAKE (1 << 3)
-#define M_P2P_BSS_ST_AP (1 << 4) /**< BSS is Infra-BSS AP */
-#define M_P2P_BSS_ST_STA (1 << 5) /**< BSS is Infra-BSS STA */
-#define M_P2P_BSS_ST_GO (1 << 6) /**< BSS is P2P Group Owner */
-#define M_P2P_BSS_ST_GC (1 << 7) /**< BSS is P2P Client */
-#define M_P2P_BSS_ST_IBSS (1 << 8) /**< BSS is an IBSS */
-#define M_P2P_BSS_ST_AWDL (1 << 9) /* BSS is AWDL */
-#define M_P2P_BSS_ST_NAN (1 << 10) /**< BSS is NAN */
-#define M_P2P_BSS_ST_MULTIDTIM (1 << 11) /* BSS is Muti-DTIM enabled */
-
-/** WiFi P2P TSF block positions */
-#define M_P2P_TSF_BLK_SZ 4
-#define M_P2P_TSF_BLK_OFFSET(x) (M_P2P_TSF_OFFSET_BLK(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_TSF_BLK(x, b) (M_P2P_TSF_BLK_OFFSET(x) + (M_P2P_TSF_BLK_SZ * (b) * 2))
-#define M_P2P_TSF(x, b, w) (M_P2P_TSF_BLK(x, b) + (w) * 2)
-
-#define M_P2P_TSF_DRIFT_OFFSET(x) (M_P2P_TSF_DRIFT_WD0(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_TSF_DRIFT(x, w) (M_P2P_TSF_DRIFT_OFFSET(x) + (w) * 2)
-
-#define M_P2P_GO_CHANNEL_OFFSET(x) (M_P2P_GO_CHANNEL(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_GO_IND_BMP_OFFSET(x) (M_P2P_GO_IND_BMP(x) - M_P2P_INTF_BLK(x))
-
-/**
- * M_P2P_GO_IND_BMP now has multiple fields:
- * 7:0 - GO_IND_BMP
- * 10:8 - BSS Index
- * 15:11 - Reserved
-*/
-#define M_P2P_GO_IND_BMP_MASK (0xFF)
-#define M_P2P_BSS_INDEX_MASK (0x700)
-#define M_P2P_BSS_INDEX_SHIFT_BITS (8)
-
-/* per BSS PreTBTT */
-/* BOM 768.0 and above */
-#define M_P2P_PRE_TBTT_OFFSET(x) (M_P2P_PRETBTT_BLK(x) - M_P2P_INTF_BLK(x))
-#define M_P2P_PRE_TBTT(x, b) (M_P2P_PRE_TBTT_OFFSET(x) + ((b) * 2)) /**< in us */
-
-/* Reserve bottom of RCMTA for P2P Addresses */
-#define WSEC_MAX_RCMTA_KEYS (54 - M_ADDR_BMP_BLK_SZ)
-#else
-#define WSEC_MAX_RCMTA_KEYS 54
-#endif /* WLP2P_UCODE */
-
-#define TXCOREMASK 0x0F
-#define SPATIAL_SHIFT 8
-#define MAX_COREMASK_BLK 5
-#define COREMASK_BLK_TRIG_FRAMES (MAX_COREMASK_BLK + 1)
-
-#define BPHY_ONE_CORE_TX (1 << 15) /**< enable TX ant diversity for 11b frames */
-
-#define M_WLCX_CONFIG_EN(x) 0x1 /**< 1: enable wifi coex */
-#define M_WLCX_CONFIG_MASTER(x) 0x2 /**< 1: Coex Master(5357) */
-
-/* ucode debug status codes */
-#define DBGST_INACTIVE 0 /**< not valid really */
-#define DBGST_INIT 1 /**< after zeroing SHM, before suspending at init */
-#define DBGST_ACTIVE 2 /**< "normal" state */
-#define DBGST_SUSPENDED 3 /**< suspended */
-#define DBGST_ASLEEP 4 /**< asleep (PS mode) */
-#define DBGST_SLP2WAKE 7 /* On wake up path. */
-
-/**
- * Defines for Self Mac address (used currently for CTS2SELF frames
- * generated by BTCX ucode for protection purposes) in SHM. GE40 only.
- */
-#define M_MYMAC_ADDR_L(x) (M_MYMAC_ADDR(x))
-#define M_MYMAC_ADDR_M(x) (M_MYMAC_ADDR(x) + (1*2))
-#define M_MYMAC_ADDR_H(x) (M_MYMAC_ADDR(x) + (2*2))
-
-/* Re-uses M_SSID */
-#define SHM_MBSS_BCNLEN0(x) M_SSID(x)
-
-#define SHM_MBSS_CLOSED_NET(x) (0x80) /**< indicates closed network */
-
-/** SSID Search Engine entries */
-#define SHM_MBSS_SSIDSE_BASE_ADDR(x) (0)
-#define SHM_MBSS_SSIDSE_BLKSZ(x) (36)
-#define SHM_MBSS_SSIDLEN_BLKSZ (4)
-#define SHM_MBSS_SSID_BLKSZ (32)
-
-/* END New for ucode template based mbss */
-
-/** Definitions for PRQ fifo data */
-
-#define SHM_MBSS_PRQ_ENTRY_BYTES 10 /**< Size of each PRQ entry */
-#define SHM_MBSS_PRQ_ENTRY_COUNT 12 /**< Number of PRQ entries */
-#define SHM_MBSS_PRQ_TOT_BYTES (SHM_MBSS_PRQ_ENTRY_BYTES * SHM_MBSS_PRQ_ENTRY_COUNT)
-
-#define M_WOWL_NOBCN (0x06c * 2) /**< loss of bcn value */
-
-#define M_KEK(x) M_EAPOLMICKEY_BLK(x) + (0x10 * 2) /* < KEK for WEP/TKIP */
-
-#define M_ARPRESP_BYTESZ_OFFSET 0 /**< 2 bytes; ARP resp pkt size */
-#define M_NA_BYTESZ_0_OFFSET 2 /**< 2 bytes ; NA pkt size */
-#define M_NA_BYTESZ_1_OFFSET 4 /**< 2 bytes ; NA pkt size */
-#define M_KEEPALIVE_BYTESZ_0_OFFSET 6 /**< 2 bytes; size of first keepalive */
-#define M_KEEPALIVE_BYTESZ_1_OFFSET 8 /**< 2 bytes; size of second keepalive */
-#define M_NPAT_ARPIDX_OFFSET 10 /**< 2 bytes; net pattern index of ARP */
-#define M_NPAT_NS0IDX_OFFSET 12 /**< 2 bytes; net pattern index of NS 0 */
-#define M_NPAT_NS1IDX_OFFSET 14 /**< 2 bytes; net pattern index of NS 1 */
-#define M_EXTWAKEPATTERN_0_OFFSET 16 /**< 6 bytes; ext magic pattern */
-#define M_EXTWAKEPATTERN_U0_OFFSET 22 /**< 8 bytes; unaligned ext magic pattern */
-#define M_KEEPALIVE_INTVL_0_OFFSET 30 /**< 2 bytes; in no of beacon intervals */
-#define M_KEEPALIVE_INTVL_1_OFFSET 32 /**< 2 bytes; in no of beacon intervals */
-
-#define M_COREMASK_BLK_WOWL_L30 (0x298 * 2)
-
-/* corerev > 29 && corerev < 40 */
-#define M_COREMASK_BLK_WOWL (0x7e8 *2)
-
-/* corerev >= 42 */
-#define D11AC_M_COREMASK_BLK_WOWL (0x1b0*2)
-
-#define M_EXTLNA_PWRSAVE(x) M_RADIO_PWR(x) /**< External LNA power control support */
-
-/* D11AC shm location changes */
-#define D11AC_T_NULL_TPL_BASE (0x16 * 2)
-#define D11AC_T_NULL_TPL_SIZE_BYTES (24)
-#define D11_T_BCN0_TPL_BASE T_BCN0_TPL_BASE
-#define D11AC_T_BCN0_TPL_BASE (0x100 * 2)
-#define D11_T_BCN1_TPL_BASE T_BCN1_TPL_BASE
-#define D11AC_T_BCN1_TPL_BASE (0x240 * 2)
-#define D11AC_T_GACT_TWT_INFO_TPL_BASE (0xB0 * 2)
-#define D11AC_T_GACT_TWT_INFO_TPL_SIZE_BYTES (36)
-
-/* The response (ACK/BA) phyctrl words */
-#define D11AC_RSP_TXPCTL0 (0x4c * 2)
-#define D11AC_RSP_TXPCTL1 (0x4d * 2)
-
-#define D11AC_T_PRS_TPL_BASE (0x380 * 2)
-
-#define D11_M_RT_PRS_PLCP_POS(x) M_RT_PRS_PLCP_POS(x)
-#define D11_M_RT_PRS_DUR_POS(x) M_RT_PRS_DUR_POS(x)
-#define D11AC_M_RT_PRS_PLCP_POS 8
-#define D11AC_M_RT_PRS_DUR_POS 12
-
-/* Field definitions for M_REV40_RT_TXPWROFF_POS */
-#define M_REV40_RT_HTTXPWR_OFFSET_MASK 0x01f8 /**< bit 8:3 */
-#define M_REV40_RT_HTTXPWR_OFFSET_SHIFT 3
-
-/* for axphy */
-#define M_REV80_RT_TXPWR_OFFSET_MASK 0xff00 /* bit 15:8 */
-#define M_REV80_RT_TXPWR_OFFSET_SHIFT 9 /* 8 (byte align) + 1 (convert from S5.1 to S5.2) */
-
-/* shmem locations for Beamforming */
-/* shmem defined with prefix M_ are in shmem */
-#define shm_addr(base, offset) (((base)+(offset))*2)
-
-#define C_BFI_REFRESH_THR_OFFSET (1u)
-#define C_BFI_NDPA_TXLMT_OFFSET (2u)
-#define C_BFI_NRXC_OFFSET (3u)
-#define C_BFI_MLBF_LUT_OFFSET (4u) // for corerev < 64 only
-
-#define C_BFI_BLK_SIZE(corerev) ((D11REV_GE(corerev, 86) ? 18u: 16u))
-
-/* BFI block definitions (Beamforming) */
-#define C_BFI_BFRIDX_POS (0)
-#define C_BFI_NDPA_TST_POS (1)
-#define C_BFI_NDPA_TXCNT_POS (2)
-#define C_BFI_NDPA_SEQ_POS (3)
-#define C_BFI_NDPA_FCTST_POS (4)
-#define C_BFI_BFRCTL_POS (5)
-#define C_BFI_BFR_CONFIG0_POS (6)
-#define C_BFI_BFE_CONFIG0_POS (7)
-#define C_BFI_BFE_MIMOCTL_POS (8)
-#define C_BFI_BSSID0_POS (9)
-#define C_BFI_BSSID1_POS (10)
-#define C_BFI_BSSID2_POS (11)
-#define C_BFI_STAINFO_POS (12)
-#define C_BFI_STAINFO1_POS (13)
-#define C_BFI_BFE_MYAID_POS (13) /* stainfo1 is mutually exclusive */
-#define C_BFI_BFMSTAT_POS (14)
-#define C_BFI_BFE_MIMOCTL_EXT_POS (15)
-/* below SHMs for rev >= 86 */
-#define C_BFI_BFE_11AXMIMOCTL_POS (16) /* phyreg bfeMimoCtlReg for 11AX */
-#define C_BFI_BFE_NDPNR_POS (17)
-/* used by BFR */
-#define C_BFI_STA_ADDR_POS C_BFI_BSSID0_POS
-
-/* to be removed -start */
-#define M_BFI_BLK_SIZE (16u)
-#define BFI_BLK_SIZE 18
-/* to be removed -end */
-
-/* Phy cache index Bit<8> indicates the validity. Cleared during TxBf link Init
- * to trigger a new sounding sequence.
- */
-#define C_BFRIDX_VLD_NBIT 8 /* valid */
-#define C_BFRIDX_EN_NBIT 7 /* BFI block is enabled (has valid info),
- * applicable only for MU BFI block in shmemx
- */
-#define C_BFRIDX_BW_NBIT 12
-
-#define C_STAINFO_FBT_NBIT 12 /* 0: SU; 1: MU */
-#define C_STAINFO_NCIDX_NBIT 13 /* Bits13-15: NC IDX; Reserved if Feedback Type is SU */
-
-/* NDP control blk */
-#define C_BFI_BFRCTL_POS_NDP_TYPE_SHIFT (0) /* 0: HT NDP; 1: VHT NDP; HE no need */
-#define C_BFI_BFRCTL_POS_NSTS_SHIFT (1) /* 0: 2ss; 1: 3ss; 2: 4ss */
-#define C_BFI_BFRCTL_POS_MLBF_SHIFT (4) /* 1 enable MLBF(used for corerev < 64) */
-#define C_BFI_BFRCTL_POS_BFM_SHIFT (8) /* Bits15-8: BFM mask for BFM frame tx */
-
-/** dynamic rflo ucode WAR defines */
-#define UCODE_WAR_EN 1
-#define UCODE_WAR_DIS 0
-
-/** LTE coex definitions */
-#define LTECX_FLAGS_LPBK_OFF 0
-
-/** LTECX shares BTCX shmem block */
-#define M_LTECX_BLK_PTR(x) M_BTCX_BLK_PTR(x)
-
-/** NR5GCX shares BTCX shmem block */
-#define M_NR5GCX_BLK_PTR(x) M_BTCX_BLK_PTR(x)
-
-/** RC1CX shares BTCX shmem block */
-#define M_RC1CX_BLK_PTR(x) M_BTCX_BLK_PTR(x)
-
-/** RC2CX shares BTCX shmem block */
-#define M_RC2CX_BLK_PTR(x) M_BTCX_BLK_PTR(x)
-
-/* CORE0 MODE */
-#define CORE0_MODE_RSDB 0x0
-#define CORE0_MODE_MIMO 0x1
-#define CORE0_MODE_80P80 0x2
-
-#define CORE1_MODE_RSDB 0x100
-
-#define HWACI_HOST_FLAG_ADDR (0x186)
-#define HWACI_SET_SW_MITIGATION_MODE (0x0008)
-
-/* split RX war shm locations */
-#define RXFIFO_0_OFFSET 0x1A0
-#define RXFIFO_1_OFFSET 0x19E
-#define HDRCONV_FIFO0_STSLEN 0x4 /* status length in header conversion mode */
-
-/* GE80:
- * [15:8]: Phy status length
- * [7:0]: Ucode status length
- */
-#define DEFAULT_FIFO0_STSLEN(corerev, corerev_minor) \
- (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? 0x2018 : \
- D11REV_GE(corerev, 80) ? 0x2010: 0x24)
-
-/* M_ULP_WAKEIND bits */
-#define C_WATCHDOG_EXPIRY (1 << 0)
-#define C_FCBS_ERROR (1 << 1)
-#define C_RETX_FAILURE (1 << 2)
-#define C_HOST_WAKEUP (1 << 3)
-#define C_INVALID_FCBS_BLOCK (1 << 4)
-#define C_HUDI_DS1_EXIT (1 << 5)
-#define C_LOB_SLEEP (1 << 6)
-
-/* values for M_ULP_FEATURES */
-#define C_P2P_NOA (0x0001)
-#define C_INFINITE_NOA (0x0002)
-#define C_P2P_CTWIN (0x0004)
-#define C_P2P_GC (0x0008)
-#define C_BCN_TRIM (0x0010)
-#define C_BT_COEX (0x0020)
-#define C_LTE_COEX (0x0040)
-#define C_ADS1 (0x0080)
-#define C_LTECX_PSPOLL_PRIO_EN (0x0100)
-#define C_ULP_SLOWCAL_SKIP (0x0200)
-#define C_HUDI_ENABLE (0x0400)
-
-#define M_WOWL_ULP_SW_DAT_BLK (0xBFF * 2) /* (0xFFF * 2) - 1024 */
-#define M_WOWL_ULP_SW_DAT_BLK_MAX_SZ (0x400) /* 1024 bytes */
-
-#define RX_INTR_FIFO_0 0x1 /* FIFO-0 interrupt */
-#define RX_INTR_FIFO_1 0x2 /* FIFO-1 interrupt */
-#define RX_INTR_FIFO_2 0x4 /* FIFO-2 interrupt */
-
-/* M_TOF_FLAG bits */
-typedef enum {
- TOF_RX_FTM_NBIT = 0,
- TOF_SEQ_DISRXENTX_RFCTL = 1,
- TOF_IS_TARGET = 2,
- TOF_TPC_FREEZE = 3
-} eTOFFlags;
-
-/* TOF feature flags */
-#define M_UCODE_F2_TOF_BIT 7 /* part of features_2 shm */
-#define M_UCODE_F3_AVB_BIT 2 /* part of features_3 shm */
-#define M_UCODE_F3_SEQ_BIT 3 /* part of features_3 shm */
-
-/* New SHM definitions required for tsync based time stamping of FTM frames.
-* More details in below conf
-* http://confluence.broadcom.com/display/WLAN/NewUcodeInterfaceForProxdFeature
-*/
-#define FTM_TIMESTAMP_SHIFT 16
-#define TXS_ACK_INDEX_SHIFT 3
-#define FTM_ACK_TS_BLOCK_SIZE 3
-#define RXH_ACK_SHIFT(corerev) (D11REV_GE((corerev), 80) ? 12u:8u)
-#define FTM_INVALID_SHM_INDEX(corerev) (D11REV_GE((corerev), 80) ? 0x04u:0x0Fu)
-#define FTM_ACK_INDEX_MASK 0x0F
-#define NUM_UCODE_ACK_TS_BLKS 4
-
-#define FTM_TXSTATUS_ACK_RSPEC_BLOCK_MASK 0xFF
-#define FTM_TXSTATUS_ACK_RSPEC_BW_MASK 0x3
-#define FTM_TXSTATUS_ACK_RSPEC_BW_SHIFT 2
-#define FTM_TXSTATUS_ACK_RSPEC_BW_20 0
-#define FTM_TXSTATUS_ACK_RSPEC_BW_40 1
-#define FTM_TXSTATUS_ACK_RSPEC_BW_80 2
-#define FTM_TXSTATUS_ACK_RSPEC_BW_160 3
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_SHIFT 4
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_MASK 0x7
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_CCK 0
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_LEG 1 /* Legacy */
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_HT 2
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_VHT 3
-#define FTM_TXSTATUS_ACK_RSPEC_TYPE_HE 4
-#define FTM_TXSTATUS_ACK_RSPEC_RATE_6M(ackword) (ackword >> 7)
-/* Following are the offsets in M_DRVR_UCODE_IF_PTR block. Start address of
- * M_DRVR_UCODE_IF_PTR block is present in M_DRVR_UCODE_IF_PTR.
- */
-#define M_ULP_FEATURES (0x0 * 2)
-
-/* M_HOST_FLAGS5 offset changed in ULP ucode */
-#define M_ULP_HOST_FLAGS5 (0x3d * 2)
-
-#define M_RADAR_REG_TMP (0x033 * 2)
-
-/* Bit masks for ClkGateUcodeReq2: Ucode MAC Clock Request2 (IHR Address 0x375) register */
-#define D11_FUNC16_MAC_CLOCKREQ_MASK (0x3)
-
-/*
- * Clock gating registers
- */
-#define CLKREQ_BLOCK 0
-#define CLKREQ_MAC_ILP 1
-#define CLKREQ_MAC_ALP 2
-#define CLKREQ_MAC_HT 3
-
-/* ClkGateSts */
-#define CLKGTE_FORCE_MAC_CLK_REQ_SHIFT 0
-#define CLKGTE_MAC_PHY_CLK_REQ_SHIFT 4
-
-/* ClkGateReqCtrl0 */
-#define CLKGTE_PSM_PATCHCOPY_CLK_REQ_SHIFT 0
-#define CLKGTE_RXKEEP_OCP_CLK_REQ_SHIFT 2
-#define CLKGTE_PSM_MAC_CLK_REQ_SHIFT 4
-#define CLKGTE_TSF_CLK_REQ_SHIFT 6
-#define CLKGTE_AQM_CLK_REQ_SHIFT 8
-#define CLKGTE_SERIAL_CLK_REQ_SHIFT 10
-#define CLKGTE_TX_CLK_REQ_SHIFT 12
-#define CLKGTE_POSTTX_CLK_REQ_SHIFT 14
-
-/* ClkGateReqCtrl1 */
-#define CLKGTE_RX_CLK_REQ_SHIFT 0
-#define CLKGTE_TXKEEP_OCP_CLK_REQ_SHIFT 2
-#define CLKGTE_HOST_RW_CLK_REQ_SHIFT 4
-#define CLKGTE_IHR_WR_CLK_REQ_SHIFT 6
-#define CLKGTE_TKIP_KEY_CLK_REQ_SHIFT 8
-#define CLKGTE_TKIP_MISC_CLK_REQ_SHIFT 10
-#define CLKGTE_AES_CLK_REQ_SHIFT 12
-#define CLKGTE_WAPI_CLK_REQ_SHIFT 14
-
-/* ClkGateReqCtrl2 */
-#define CLKGTE_WEP_CLK_REQ_SHIFT 0
-#define CLKGTE_PSM_CLK_REQ_SHIFT 2
-#define CLKGTE_MACPHY_CLK_REQ_BY_PHY_SHIFT 4
-#define CLKGTE_FCBS_CLK_REQ_SHIFT 6
-#define CLKGTE_HIN_AXI_MAC_CLK_REQ_SHIFT 8
-
-/* ClkGateStretch0 */
-#define CLKGTE_MAC_HT_CLOCK_STRETCH_SHIFT 0
-#define CLKGTE_MAC_ALP_CLOCK_STRETCH_SHIFT 8
-#define CLKGTE_MAC_HT_CLOCK_STRETCH_VAL 0x4
-
-/* ClkGateStretch1 */
-#define CLKGTE_MAC_PHY_CLOCK_STRETCH_SHIFT 13
-
-/* ClkGateMisc */
-#define CLKGTE_TPF_CLK_REQTHRESH 0xF
-#define CLKGTE_AQM_CLK_REQEXT 0x70
-
-/* ClkGateDivCtrl */
-#define CLKGTE_MAC_ILP_OFF_COUNT_MASK 0x0007
-#define CLKGTE_MAC_ILP_OFF_COUNT_SHIFT 0
-#define CLKGTE_MAC_ILP_ON_COUNT_MASK 0x0020
-#define CLKGTE_MAC_ILP_ON_COUNT_MASK_GE_REV80 0x0030
-#define CLKGTE_MAC_ALP_OFF_COUNT_MASK 0x03C0
-#define CLKGTE_MAC_ALP_OFF_COUNT_SHIFT 6
-
-/* ClkGatePhyClkCtrl */
-#define CLKGTE_PHY_MAC_PHY_CLK_REQ_EN_SHIFT 0
-#define CLKGTE_O2C_HIN_PHY_CLK_EN_SHIFT 1
-#define CLKGTE_HIN_PHY_CLK_EN_SHIFT 2
-#define CLKGTE_IHRP_PHY_CLK_EN_SHIFT 3
-#define CLKGTE_CCA_MAC_PHY_CLK_REQ_EN_SHIFT 4
-#define CLKGTE_TX_MAC_PHY_CLK_REQ_EN_SHIFT 5
-#define CLKGTE_HRP_MAC_PHY_CLK_REQ_EN_SHIFT 6
-#define CLKGTE_SYNC_MAC_PHY_CLK_REQ_EN_SHIFT 7
-#define CLKGTE_RX_FRAME_MAC_PHY_CLK_REQ_EN_SHIFT 8
-#define CLKGTE_RX_START_MAC_PHY_CLK_REQ_EN_SHIFT 9
-#define CLKGTE_FCBS_MAC_PHY_CLK_REQ_SHIFT 10
-#define CLKGTE_POSTRX_MAC_PHY_CLK_REQ_EN_SHIFT 11
-#define CLKGTE_DOT11_MAC_PHY_RXVALID_SHIFT 12
-#define CLKGTE_NOT_PHY_FIFO_EMPTY_SHIFT 13
-#define CLKGTE_DOT11_MAC_PHY_BFE_REPORT_DATA_READY 14
-#define CLKGTE_DOT11_MAC_PHY_CLK_BIT15 15
-
-/* ClkGateExtReq0 */
-#define CLKGTE_TOE_SYNC_MAC_CLK_REQ_SHIFT 0
-#define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_SHIFT 2
-#define CLKGTE_HIN_SYNC_MAC_CLK_REQ_SHIFT 4
-#define CLKGTE_SLOW_SYNC_CLK_REQ_SHIFT 6
-#define CLKGTE_ERCX_SYNC_CLK_REQ_SHIFT 8
-#define CLKGTE_BTCX_SYNC_CLK_REQ_SHIFT 10
-#define CLKGTE_IFS_CRS_SYNC_CLK_REQ_SHIFT 12
-#define CLKGTE_IFS_GCI_SYNC_CLK_REQ_SHIFT 14
-
-#define CLKGTE_TOE_SYNC_MAC_CLK_REQ_80_SHIFT 2
-#define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_80_SHIFT 4
-#define CLKGTE_HIN_SYNC_MAC_CLK_REQ_80_SHIFT 6
-#define CLKGTE_SLOW_SYNC_CLK_REQ_80_SHIFT 8
-#define CLKGTE_ERCX_SYNC_CLK_REQ_80_SHIFT 10
-#define CLKGTE_BTCX_SYNC_CLK_REQ_80_SHIFT 12
-#define CLKGTE_IFS_CRS_SYNC_CLK_REQ_80_SHIFT 14
-
-#define CLKGTE_TOE_SYNC_MAC_CLK_REQ_83_SHIFT 2
-#define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_83_SHIFT 4
-#define CLKGTE_HIN_SYNC_MAC_CLK_REQ_83_SHIFT 6
-#define CLKGTE_SLOW_SYNC_CLK_REQ_83_SHIFT 8
-#define CLKGTE_ERCX_SYNC_CLK_REQ_83_SHIFT 10
-#define CLKGTE_BTCX2_SYNC_CLK_REQ_83_SHIFT 12
-#define CLKGTE_BTCX_SYNC_CLK_REQ_83_SHIFT 14
-
-/* ClkGateExtReq1 */
-#define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_SHIFT 0
-#define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_SHIFT 2
-#define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_SHIFT 4
-#define CLKGTE_PSM_IPC_SYNC_CLK_REQ_SHIFT 6
-
-#define CLKGTE_IFS_GCI_SYNC_CLK_REQ_80_SHIFT 0
-#define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_80_SHIFT 2
-#define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_80_SHIFT 4
-#define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_80_SHIFT 6
-#define CLKGTE_PSM_IPC_SYNC_CLK_REQ_80_SHIFT 8
-
-#define CLKGTE_IFS_CRS_SYNC_CLK_REQ_83_SHIFT 0
-#define CLKGTE_IFS_GCI_SYNC_CLK_REQ_83_SHIFT 2
-#define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_83_SHIFT 4
-#define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_83_SHIFT 6
-#define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_83_SHIFT 8
-#define CLKGTE_PSM_IPC_SYNC_CLK_REQ_83_SHIFT 10
-
-/* PFE CtlStat1 register */
-#define PFE_CTLSTAT1_ROUTE_PFE_TO_BMSTAT (1u << 15u)
-#define PFE_CTLSTAT1_PFE_ENABLE (1u << 0u)
-
-/* PPR Ctrl1 register */
-#define PPR_CTMODE_SHIFT 8u
-#define PPR_CTMODE_MASK (3u << PPR_CTMODE_SHIFT)
-
-#define PPR_CTMODE_A (0u << PPR_CTMODE_SHIFT)
-#define PPR_CTMODE_B (1u << PPR_CTMODE_SHIFT)
-#define PPR_CTMODE_C (2u << PPR_CTMODE_SHIFT)
-
-/* Ptxd Len */
-#define PTXD_LEN0_SHIFT (0u)
-#define PTXD_LEN1_SHIFT (8u)
-#define PTXD_LEN2_SHIFT (0u)
-#define PTXD_LEN3_SHIFT (8u)
-/* =========== LHL regs =========== */
-/* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */
-#define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001
-
-#define D11_AUTO_MEM_STBY_RET_SHIFT (4u)
-#define D11_AUTO_MEM_STBY_RET_83_SHIFT (5u)
-#define D11_AUTO_MEM_STBY_NON_RET_SHIFT (6u)
-#define D11_AUTO_MEM_STBY_BM_SHIFT (9u)
-
-#define D11_AUTO_MEM_STBY_RET_SHIFT_REV(d11rev) \
- (((d11rev) >= 83) ? D11_AUTO_MEM_STBY_RET_83_SHIFT : D11_AUTO_MEM_STBY_RET_SHIFT)
-
-/* WiFi P2P TX stop timestamp block (only applicable with AC ucode) */
-#define P2P_TXSTOP_SHMPERBSS 2u /* 2 shmems per BSS */
-#define M_P2P_TXSTOP_TS(x, b, w) (M_P2P_TXSTOP_T_BLK(x) +\
- (P2P_TXSTOP_SHMPERBSS * (b) + (w)) * 2)
-
-#define D11TXHDR_RATEINFO_ACCESS_VAL(txh, corerev, member) \
- ((((txh)->corerev).RateInfo[3]).member)
-
-/* QoS + BSR information */
-#define D11_QOS_BSR_TIDQS_SHIFT 0u
-#define D11_QOS_BSR_TIDQS_SZ 8u
-#define D11_QOS_BSR_TIDQS_MASK (((1 << D11_QOS_BSR_TIDQS_SZ) - 1) << D11_QOS_BSR_TIDQS_SHIFT)
-
-#define D11_QOS_BSR_UV_SHIFT 8u
-#define D11_QOS_BSR_UV_SZ 6u
-#define D11_QOS_BSR_UV_MASK (((1 << D11_QOS_BSR_UV_SZ) - 1) << D11_QOS_BSR_UV_SHIFT)
-
-#define D11_QOS_BSR_SF_SHIFT 14u
-#define D11_QOS_BSR_SF_SZ 2u
-#define D11_QOS_BSR_SF_MASK (((1 << D11_QOS_BSR_SF_SZ) - 1) << D11_QOS_BSR_SF_SHIFT)
-
-/* Queue size in QoS control */
-#define D11_QOS_BSR_SF_0 0u
-#define D11_QOS_BSR_SF_1 1u
-#define D11_QOS_BSR_SF_2 2u
-#define D11_QOS_BSR_SF_3 3u
-
-#define D11_QS_OFFSET_SF_0 0u
-#define D11_QS_OFFSET_SF_1 1024u
-#define D11_QS_OFFSET_SF_2 17408u
-#define D11_QS_OFFSET_SF_3 148480u
-
-#define D11_QOS_BSR_SF_0_SHIFT 4u /* Scale: 16 bytes */
-#define D11_QOS_BSR_SF_1_SHIFT 8u /* Scale: 256 bytes */
-#define D11_QOS_BSR_SF_2_SHIFT 11u /* Scale: 2048 bytes */
-#define D11_QOS_BSR_SF_3_SHIFT 15u /* Scale: 32768 bytes */
-
-#define D11_MIN_QS_UV 0u
-#define D11_MAX_QS_UV 63u
-#define D11_MAX_QS_UV_SF3 ((D11_MAX_QS_UV) - 1)
-
-/* 1008: 16 * UV when the Scaling Factor subfield is 0 */
-#define D11_MAX_QS_SF_0 (D11_QS_OFFSET_SF_0 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_0_SHIFT))
-/* 17152: 1024 + 256 * UV when the Scaling Factor subfield is 1 */
-#define D11_MAX_QS_SF_1 (D11_QS_OFFSET_SF_1 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_1_SHIFT))
-/* 146432: 17408 + 2048 * UV when the Scaling Factor subfield is 2 */
-#define D11_MAX_QS_SF_2 (D11_QS_OFFSET_SF_2 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_2_SHIFT))
-/* 2147328: 148480 + 32768 * UV when the Scaling Factor subfield is 3 */
-#define D11_MAX_QS_SF_3 (D11_QS_OFFSET_SF_3 + ((D11_MAX_QS_UV_SF3-1) << D11_QOS_BSR_SF_3_SHIFT))
-
-/* 2 bits for HE signature and 4 bits for control ID */
-#define D11_BSR_HE_SIG_SHIFT 6u
-/* HE Variant with BSR control ID */
-#define D11_BSR_HE_SIG (0xf)
-#define D11_BSR_ACI_BMAP_SHIFT (0 + D11_BSR_HE_SIG_SHIFT)
-#define D11_BSR_DELTA_TID_SHIFT (4 + D11_BSR_HE_SIG_SHIFT)
-#define D11_BSR_SF_SHIFT (8 + D11_BSR_HE_SIG_SHIFT)
-#define D11_BSR_QUEUE_SIZE_HIGH_SHIFT (10 + D11_BSR_HE_SIG_SHIFT)
-#define D11_BSR_QUEUE_SIZE_ALL_SHIFT (18 + D11_BSR_HE_SIG_SHIFT)
-
-#define D11_BSR_DELTA_TID_ALLTID_SIGNATURE 3u
-
-#define D11_BSR_QUEUE_SIZE_WIDTH 8u
-#define D11_BSR_QUEUE_SIZE_WIDTH_VAL ((1 << D11_BSR_QUEUE_SIZE_WIDTH) - 1)
-#define D11_BSR_QUEUE_SIZE_UNKNOWN (255u)
-#define D11_BSR_QUEUE_SIZE_MAX (254u)
-#define D11_BSR_QUEUE_SIZE_HIGH_MASK (D11_BSR_QUEUE_SIZE_WIDTH_VAL <<\
- D11_BSR_QUEUE_SIZE_HIGH_SHIFT)
-#define D11_BSR_QUEUE_SIZE_ALL_MASK (D11_BSR_QUEUE_SIZE_WIDTH_VAL <<\
- D11_BSR_QUEUE_SIZE_ALL_SHIFT)
-
-#define D11_BSR_WD1_SHIFT 16u
-
-enum {
- D11_BSR_SF_ID_16 = 0, /* 0 */
- D11_BSR_SF_ID_256 = 1, /* 1 */
- D11_BSR_SF_ID_2048 = 2, /* 2 */
- D11_BSR_SF_ID_32768 = 3 /* 3 */
-};
-
-enum {
- D11_PING_BLOCK_VALID = 0, /* 0 */
- D11_PONG_BLOCK_VALID = 1, /* 1 */
- D11_UC_READING_PING_BLOCK = 2, /* 2 */
- D11_UC_READING_PONG_BLOCK = 3 /* 3 */
-};
-
-enum {
- D11_BSR_TID0_POS = 0, /* 0 */
- D11_BSR_TID1_POS = 1, /* 1 */
- D11_BSR_TID2_POS = 2, /* 2 */
- D11_BSR_TID3_POS = 3, /* 3 */
- D11_BSR_TID4_POS = 4, /* 4 */
- D11_BSR_TID5_POS = 5, /* 5 */
- D11_BSR_TID6_POS = 6, /* 6 */
- D11_BSR_TID7_POS = 7, /* 7 */
- D11_BSR_WD0_POS = 8, /* 8 */
- D11_BSR_WD1_POS = 9, /* 9 */
-};
-
-#define D11_IS_PING_PONG_IN_RESET(i) (((i) & ((1 << D11_PING_BLOCK_VALID) |\
- (1 << D11_UC_READING_PING_BLOCK) | (1 << D11_PONG_BLOCK_VALID) |\
- (1 << D11_UC_READING_PONG_BLOCK))) == 0)
-#define D11_PING_BLOCK_VALID_MASK ((1 << D11_PONG_BLOCK_VALID) |\
- (1 << D11_UC_READING_PING_BLOCK))
-#define D11_PONG_BLOCK_VALID_MASK ((1 << D11_PING_BLOCK_VALID) |\
- (1 << D11_UC_READING_PONG_BLOCK))
-#define D11_PING_PONG_UPDATE_MASK ((1 << D11_PING_BLOCK_VALID) |\
- (1 << D11_PONG_BLOCK_VALID))
-#define D11_IS_PING_BLOCK_WRITABLE(i) (((i) & D11_PING_BLOCK_VALID_MASK) == \
- (1 << D11_PONG_BLOCK_VALID))
-#define D11_IS_PONG_BLOCK_WRITABLE(i) (((i) & D11_PONG_BLOCK_VALID_MASK) == \
- (1 << D11_PING_BLOCK_VALID))
-#define D11_SET_PING_BLOCK_VALID(i) (((i) & ~(1 << D11_PONG_BLOCK_VALID)) |\
- (1 << D11_PING_BLOCK_VALID))
-#define D11_SET_PONG_BLOCK_VALID(i) (((i) & ~(1 << D11_PING_BLOCK_VALID)) |\
- (1 << D11_PONG_BLOCK_VALID))
-#define D11_SET_PING_PONG_INVALID(i) (((i) & ~(1 << D11_PING_BLOCK_VALID)) |\
- ((i) & ~(1 << D11_PONG_BLOCK_VALID)))
-
-/* valid rx plcp check */
-#define PLCP_VALID(plcp) (((plcp)[0] | (plcp)[1] | (plcp)[2]) != 0)
-enum {
- D11_TXTRIG_EN = 0, /* 0 */
- D11_TXTRIG_PROG = 1, /* 1 */
- D11_TXTRIG_DONE = 2, /* 2 */
- D11_TXTRIG_TYPE = 4, /* 4 */
-};
-
-#define D11_SET_TXTRIG_EN (1 << D11_TXTRIG_EN)
-#define D11_TXTRIG_TYPE_MASK ((1 << D11_TXTRIG_TYPE) | (1 << (D11_TXTRIG_TYPE+1)))
-#define D11_SET_TXTRIG_TYPE(i) (((i) << D11_TXTRIG_TYPE) & D11_TXTRIG_TYPE_MASK)
-
-enum {
- D11_MUEDCA_AIFSN = 0, /* 0 */
- D11_MUEDCA_CWMIN = 1, /* 1 */
- D11_MUEDCA_CWMAX = 2, /* 2 */
- D11_MUEDCA_TIMER = 3, /* 3 */
- D11_MUEDCA_SU_AIFSN = 4, /* 4 */
- D11_MUEDCA_SU_CWMIN = 5, /* 5 */
- D11_MUEDCA_SU_CWMAX = 6, /* 6 */
- D11_MUEDCA_EXPIRY_TSF = 7, /* 7 */
- D11_MUEDCA_QINFO = 8, /* 8 */
- D11_MUEDCA_STAT = 9, /* 9 */
- D11_MUEDCA_BLK_SIZE = 10 /* 10 */
-};
-#define D11_MUEDCA_BLK(x, idx, offset) (M_MUEDCA_BLK((x)) +\
- (idx * (D11_MUEDCA_BLK_SIZE << 1)) + (offset << 1))
-
-#define D11_BSSCOLOR_VALID_SHIFT 15u
-#define D11_BSSCOLOR_VALID_MASK (1 << D11_BSSCOLOR_VALID_SHIFT)
-
-#ifdef BCMPCIE_HP2P
-/* HP2P (High Priority P2P) shared memory EDCA parameters */
-typedef struct shm_hp2p_edca_params {
- uint16 txop;
- uint16 cwmin;
- uint16 cwmax;
- uint16 cwcur;
- uint16 aifs;
- uint16 bslots;
- uint16 reggap;
- uint16 status;
-} shm_hp2p_edca_params_t;
-
-#define HP2P_STATUS_NEWPARAMS (1u << 8u)
-#endif /* BCMPCIE_HP2P */
-
-#define MAX_D11_GPIOS 16
-
-/* Workaround register */
-#define WAR_TXDMA_NONMODIFIABLE_EN 0x00000010 /* For TxDMA initiated AXI reads */
-#define WAR_AQMDMA_NONMODIFIABLE_EN 0x00000020 /* For AQMDMA initiated AXI reads */
-
-/* noise cal timeout when NAN is enabled.
-* 54 * 256 = ~14ms .
-* smallest NAN CRB possible is 16ms..choose 14ms
-* as timeout to ensure noise cal happens within this 16ms
-*/
-#define M_NOISE_CALTIMEOUT_FOR_NAN 54u
-
-#define TXPU_CMD_SET 1u /**< txpu set command */
-
-#endif /* _D11_H */
+++ /dev/null
-/*
- * Header file for splitrx mode definitions
- * Explains different splitrx modes, macros for classify, conversion.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _d11_cfg_h_
-#define _d11_cfg_h_
-
-#ifdef USE_BCMCONF_H
-#include <bcmconf.h>
-#else
-#if defined(BCMDONGLEHOST) && !defined(WINNT)
-#define D11REV_IS(var, val) ((var) == (val))
-#define D11REV_GE(var, val) ((var) >= (val))
-#define D11REV_GT(var, val) ((var) > (val))
-#define D11REV_LT(var, val) ((var) < (val))
-#define D11REV_LE(var, val) ((var) <= (val))
-
-#define D11MINORREV_IS(var, val) ((var) == (val))
-#define D11MINORREV_GE(var, val) ((var) >= (val))
-#define D11MINORREV_GT(var, val) ((var) > (val))
-#define D11MINORREV_LT(var, val) ((var) < (val))
-#define D11MINORREV_LE(var, val) ((var) <= (val))
-
-#define D11REV_MAJ_MIN_GE(corerev, corerev_minor, maj, min) \
- ((D11REV_IS((corerev), (maj)) && D11MINORREV_GE((corerev_minor), (min))) || \
- D11REV_GT(corerev, (maj)))
-
-#endif /* BCMDONGLEHOST */
-#endif /* USE_BCMCONF_H */
-
-#define RXMODE0 0 /* no split */
-#define RXMODE1 1 /* descriptor split */
-#define RXMODE2 2 /* descriptor split + classification */
-#define RXMODE3 3 /* fifo split + classification */
-#define RXMODE4 4 /* fifo split + classification + hdr conversion */
-
-#ifdef BCMSPLITRX
- extern bool _bcmsplitrx;
-#if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
- #define BCMSPLITRX_ENAB() (_bcmsplitrx)
-#elif defined(BCMSPLITRX_DISABLED)
- #define BCMSPLITRX_ENAB() (0)
-#else
- #define BCMSPLITRX_ENAB() (1)
-#endif
-
- extern uint8 _bcmsplitrx_mode;
-#if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
- #define BCMSPLITRX_MODE() (_bcmsplitrx_mode)
-#elif defined(BCMSPLITRX_DISABLED)
- #define BCMSPLITRX_MODE() (0)
-#else
- #define BCMSPLITRX_MODE() (_bcmsplitrx_mode)
-#endif
-#else
- #define BCMSPLITRX_ENAB() (0)
- #define BCMSPLITRX_MODE() (0)
-#endif /* BCMSPLITRX */
-
-#define SPLIT_RXMODE1() ((BCMSPLITRX_MODE() == RXMODE1))
-#define SPLIT_RXMODE2() ((BCMSPLITRX_MODE() == RXMODE2))
-#define SPLIT_RXMODE3() ((BCMSPLITRX_MODE() == RXMODE3))
-#define SPLIT_RXMODE4() ((BCMSPLITRX_MODE() == RXMODE4))
-
-#define PKT_CLASSIFY() (SPLIT_RXMODE2() || SPLIT_RXMODE3() || SPLIT_RXMODE4())
-#define RXFIFO_SPLIT() (SPLIT_RXMODE3() || SPLIT_RXMODE4())
-#define HDR_CONV() (SPLIT_RXMODE4())
-#define HDRCONV_PAD 2
-
-#define FRAG_CMN_MSG_HDROOM (16u) /* Common msg headroom required by PCIe to push txstatus */
-
-#if defined(FMF_LIT) && !defined(FMF_LIT_DISABLED)
-/* (188-4*24-16) required HEADROOM - 4 Rate info Block - CacheInfo */
-#define FRAG_HEADROOM_D11REV_GE83 76u
-#else
-#if (defined(WLC_TXDC) && !defined(WLC_TXDC_DISABLED)) || \
- (defined(FMF_RIT) && !defined(FMF_RIT_DISABLED))
-#define FRAG_HEADROOM_D11REV_GE83 92u /* (188-4*24) required HEADROOM - 4 Rate info Block */
-#else
-/* required HEADROOM = PTXD (24) + LIT (16) + RIT (96)
- + max dot11hdr (44)::
- "FC+DUR+SEQ+A1+A2+A3"(24) + QOS(2) + max("HTC(4) + AES IV(8)", WAPI IV(18))
- + MSDU data size (22):: SFH (14) + LLC (8)
- - ETHER_HDR_LEN
- */
-#define FRAG_HEADROOM_D11REV_GE83 188u
-#endif /* (WLC_TXDC && !WLC_TXDC_DISABLED) || (FMF_RIT && !FMF_RIT_DISABLED) */
-#endif /* defined(FMF_LIT) && !defined(FMF_LIT_DISABLED) */
-#define FRAG_HEADROOM_D11REV_LT80 226u /* TXOFF + amsdu header */
-#define FRAG_HEADROOM_D11REV_GE80 \
- (FRAG_HEADROOM_D11REV_GE83 + 4u) /* + TSO_HEADER_PASSTHROUGH_LENGTH(4) */
-
-#ifdef USE_NEW_COREREV_API
-#define FRAG_HEAD_ROOM(corerev) (D11REV_GE(corerev, 83) ? \
- FRAG_HEADROOM_D11REV_GE83 : D11REV_GE(corerev, 80) ? \
- FRAG_HEADROOM_D11REV_GE80 : FRAG_HEADROOM_D11REV_LT80)
-#else
-#define FRAG_HEAD_ROOM(sih, coreid) ((si_get_corerev(sih, coreid) >= 83) ? \
- FRAG_HEADROOM_D11REV_GE83 : ((si_get_corerev(sih, coreid) >= 80) ? \
- FRAG_HEADROOM_D11REV_GE80 : FRAG_HEADROOM_D11REV_LT80))
-#endif
-
-#endif /* _d11_cfg_h_ */
+++ /dev/null
-/* D11reglist prototype for Broadcom 802.11abgn
- * Networking Adapter Device Drivers.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-#ifndef _d11reglist_proto_h_
-#define _d11reglist_proto_h_
-
-/* this is for dump_mac */
-enum {
- D11REG_TYPE_IHR16 = 0,
- D11REG_TYPE_IHR32 = 1,
- D11REG_TYPE_SCR = 2,
- D11REG_TYPE_SHM = 3,
- D11REG_TYPE_TPL = 4,
- D11REG_TYPE_GE64 = 5,
- D11REG_TYPE_KEYTB = D11REG_TYPE_GE64,
- D11REG_TYPE_IHRX16 = 6,
- D11REG_TYPE_SCRX = 7,
- D11REG_TYPE_SHMX = 8,
- D11REG_TYPE_MAX = 9
-};
-
-#define D11REGTYPENAME { \
- "ihr", "ihr", "scr", "shm", \
- "tpl", "keytb", "ihrx", "scrx", \
- "shmx" \
-}
-
-typedef struct _d11regs_bmp_list {
- uint8 type;
- uint16 addr;
- uint32 bitmap;
- uint8 step;
- uint16 cnt; /* can be used together with bitmap or by itself */
-} d11regs_list_t;
-
-#define D11REG_BLK_SIZE 32
-typedef struct _d11regs_addr_list {
- uint8 type;
- uint16 cnt;
- uint16 addr[D11REG_BLK_SIZE]; /* allow up to 32 per list */
-} d11regs_addr_t;
-
-typedef struct _d11obj_cache_t {
- uint32 sel;
- uint32 val;
- uint16 addr32;
- bool cache_valid;
-} d11obj_cache_t;
-
-typedef struct _svmp_list {
- uint32 addr;
- uint16 cnt;
-} svmp_list_t;
-
-#endif /* _d11reglist_proto_h_ */
+++ /dev/null
-/*
- * Chip-specific hardware definitions for
- * Broadcom 802.11abg Networking Device Driver
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _D11REGS_H
-#define _D11REGS_H
-
-#include <typedefs.h>
-#include <sbhndpio.h>
-#include <sbhnddma.h>
-#include <sbconfig.h>
-
-#if !defined(BCMDONGLEHOST)
-#include <dot11mac_all_regs.h>
-#include <d11regs_comp.h>
-#endif
-
-#if defined(BCMDONGLEHOST) || defined(WL_UNITTEST)
-typedef struct {
- uint32 pad;
-} d11regdefs_t;
-
-typedef volatile uint8 d11regs_t;
-typedef struct _d11regs_info {
- uint32 pad;
-} d11regs_info_t;
-
-#else /* defined(BCMDONGLEHOST) || defined(WL_UNITTEST) */
-
-typedef volatile struct d11regs d11regs_t;
-
-typedef struct _d11regs_info {
- d11regs_t *regs;
-} d11regs_info_t;
-
-#endif /* !defined(BCMDONGLEHOST) || !defined(WL_UNITTEST) */
-
-typedef volatile struct {
- uint32 intstatus;
- uint32 intmask;
-} intctrlregs_t;
-
-/**
- * read: 32-bit register that can be read as 32-bit or as 2 16-bit
- * write: only low 16b-it half can be written
- */
-typedef volatile union {
- uint32 pmqhostdata; /**< read only! */
- struct {
- uint16 pmqctrlstatus; /**< read/write */
- uint16 PAD;
- } w;
-} pmqreg_t;
-
-/** dma corerev >= 11 */
-typedef volatile struct {
- dma64regs_t dmaxmt; /* dma tx */
- pio4regs_t piotx; /* pio tx */
- dma64regs_t dmarcv; /* dma rx */
- pio4regs_t piorx; /* pio rx */
-} fifo64_t;
-
-/** indirect dma corerev >= 64 */
-typedef volatile struct {
- dma64regs_t dma; /**< dma tx */
- uint32 indintstatus;
- uint32 indintmask;
-} ind_dma_t;
-
-/** indirect dma corerev 80, 81, 82 */
-typedef volatile struct {
- uint32 indintstatus;
- uint32 indintmask;
- dma64regs_t dma; /**< dma tx, */
-} ind_dma_axc_t;
-
-/* access to register offsets and fields defined in dot11mac_all_regs.h */
-
-#define D11_REG_OFF(regname) \
- dot11mac_##regname##_ADDR
-#define D11_REG_FIELD_MASK(regname, regfield) \
- dot11mac_##regname##__##regfield##_MASK
-#define D11_REG_FIELD_SHIFT(regname, regfield) \
- dot11mac_##regname##__##regfield##_SHIFT
-
-/* convert register offset to backplane address */
-
-#ifndef D11_REG_ADDR_CHK
-// #define D11_REG_ADDR_CHK
-#endif
-
-#ifdef D11_REG_ADDR_CHK
-#define D11_REG_ADDR_EXEMPT(regname) \
- (D11_REG_OFF(regname) == D11_REG_OFF(PHY_REG_ADDR) || \
- D11_REG_OFF(regname) == D11_REG_OFF(radioregaddr) || \
- D11_REG_OFF(regname) == D11_REG_OFF(radioregdata) || \
- D11_REG_OFF(regname) == D11_REG_OFF(OBJ_DATA) || \
- 0)
-#define D11_REG32_ADDR(regbase, regname) \
- ({ \
- STATIC_ASSERT(D11_REG_ADDR_EXEMPT(regname) || D11_REG_OFF(regname) < 0x3e0); \
- (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \
- })
-#define D11_REG16_ADDR(regbase, regname) \
- ({ \
- STATIC_ASSERT(D11_REG_ADDR_EXEMPT(regname) || D11_REG_OFF(regname) >= 0x3e0); \
- (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \
- })
-#else /* !D11_REG_ADDR_CHK */
-#define D11_REG32_ADDR(regbase, regname) \
- (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname))
-#define D11_REG16_ADDR(regbase, regname) \
- (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname))
-#endif /* !D11_REG_ADDR_CHK */
-
-/* used in table */
-#define D11_REG32_ADDR_ENTRY(regbase, regname) \
- (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname))
-#define D11_REG16_ADDR_ENTRY(regbase, regname) \
- (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname))
-
-#ifndef D11_NEW_ACCESS_MACROS
-/* MOVED TO src/wl/sys/wlc_hw_priv.h */
-#define GET_MACINTSTATUS(osh, hw) R_REG((osh), D11_MACINTSTATUS(hw))
-#define SET_MACINTSTATUS(osh, hw, val) W_REG((osh), D11_MACINTSTATUS(hw), (val))
-#define GET_MACINTMASK(osh, hw) R_REG((osh), D11_MACINTMASK(hw))
-#define SET_MACINTMASK(osh, hw, val) W_REG((osh), D11_MACINTMASK(hw), (val))
-
-#define GET_MACINTSTATUS_X(osh, hw) R_REG((osh), D11_MACINTSTATUS_psmx(hw))
-#define SET_MACINTSTATUS_X(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_psmx(hw), (val))
-#define GET_MACINTMASK_X(osh, hw) R_REG((osh), D11_MACINTMASK_psmx(hw))
-#define SET_MACINTMASK_X(osh, hw, val) W_REG((osh), D11_MACINTMASK_psmx(hw), (val))
-
-#define GET_MACINTSTATUS_EXT(osh, hw) R_REG((osh), D11_MACINTSTATUS_EXT(hw))
-#define SET_MACINTSTATUS_EXT(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_EXT(hw), (val))
-#define GET_MACINTMASK_EXT(osh, hw) R_REG((osh), D11_MACINTMASK_EXT(hw))
-#define SET_MACINTMASK_EXT(osh, hw, val) W_REG((osh), D11_MACINTMASK_EXT(hw), (val))
-
-#define GET_MACINTSTATUS_EXT_X(osh, hw) R_REG((osh), D11_MACINTSTATUS_EXT_psmx(hw))
-#define SET_MACINTSTATUS_EXT_X(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_EXT_psmx(hw), (val))
-#define GET_MACINTMASK_EXT_X(osh, hw) R_REG((osh), D11_MACINTMASK_EXT_psmx(hw))
-#define SET_MACINTMASK_EXT_X(osh, hw, val) W_REG((osh), D11_MACINTMASK_EXT_psmx(hw), (val))
-
-#define D11Reggrp_intctrlregs(hw, ix) ((intctrlregs_t*)(((volatile uint8*)D11_intstat0(hw)) + \
- (sizeof(intctrlregs_t)*ix)))
-#define D11Reggrp_inddma(hw, ix) (D11REV_GE(hw->corerev, 86) ? \
- ((ind_dma_t*)(((volatile uint8*)D11_ind_xmt_control(hw)) + (sizeof(ind_dma_t)*ix))) : \
- ((ind_dma_t*)(((volatile uint8*)D11_inddma(hw)) + (sizeof(ind_dma_t)*ix))))
-#define D11Reggrp_inddma_axc(hw, ix) ((ind_dma_axc_t*)(((volatile uint8*)D11_inddma(hw)) + \
- (sizeof(ind_dma_axc_t)*ix)))
-#define D11Reggrp_indaqm(hw, ix) (D11REV_GE(hw->corerev, 86) ? \
- ((ind_dma_t*)(((volatile uint8*)D11_IndAQMctl(hw)) + (sizeof(ind_dma_t)*ix))) : \
- ((ind_dma_t*)(((volatile uint8*)D11_indaqm(hw)) + (sizeof(ind_dma_t)*ix))))
-#define D11Reggrp_pmqreg(hw, ix) ((pmqreg_t*)(((volatile uint8*)D11_PMQHOSTDATA(hw)) + \
- (sizeof(pmqreg_t)*ix)))
-#define D11Reggrp_f64regs(hw, ix) ((fifo64_t*)(((volatile uint8*)D11_xmt0ctl(hw)) + \
- (sizeof(fifo64_t)*ix)))
-#define D11Reggrp_dmafifo(hw, ix) ((dma32diag_t*)(((volatile uint8*)D11_fifobase(hw)) + \
- (sizeof(dma32diag_t)*ix)))
-#define D11Reggrp_intrcvlazy(hw, ix) ((volatile uint32*)(((volatile uint8*)D11_intrcvlzy0(hw)) + \
- (sizeof(uint32)*ix)))
-#define D11Reggrp_altintmask(hw, ix) ((volatile uint32*)(((volatile uint8*)D11_alt_intmask0(hw)) + \
- (sizeof(uint32)*ix)))
-#define D11REG_ISVALID(ptr, addr) ((volatile uint16 *)(addr) != \
- ((volatile uint16 *) &((ptr)->regs->INVALID_ID)))
-#endif /* D11_NEW_ACCESS_MACROS */
-
-#endif /* _D11REGS_H */
#elif (defined (BCMDBG_ASSERT) && !defined (BCMDBG_ASSERT_DISABLED))
#define EPI_VERSION_STR "101.10.361 (wlan=r892223 ASSRT)"
#else
-#define EPI_VERSION_STR "101.10.361.24 (wlan=r892223-20220913-1)"
+#define EPI_VERSION_STR "101.10.361.28 (wlan=r892223-20221116-5)"
#endif /* BCMINTERNAL */
#endif /* _epivers_h_ */
+++ /dev/null
-/*
- * Generic functions for d11 access
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _hndd11_h_
-#define _hndd11_h_
-
-#include <typedefs.h>
-#include <osl_decl.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <d11.h>
-
-/* This marks the start of a packed structure section. */
-#include <packed_section_start.h>
-
-#ifndef WL_RSSI_ANT_MAX
-#define WL_RSSI_ANT_MAX 4 /**< max possible rx antennas */
-#elif WL_RSSI_ANT_MAX != 4
-#error "WL_RSSI_ANT_MAX does not match"
-#endif
-
-BWL_PRE_PACKED_STRUCT struct wl_d11rxrssi {
- int8 dBm; /* number of full dBms */
- /* sub-dbm resolution */
- int8 decidBm; /* sub dBms : value after the decimal point */
-} BWL_POST_PACKED_STRUCT;
-
-typedef struct wl_d11rxrssi wlc_d11rxrssi_t;
-
-BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
- /* SW header */
- uint32 tsf_l; /**< TSF_L reading */
- int8 rssi; /**< computed instantaneous rssi */
- int8 rssi_qdb; /**< qdB portion of the computed rssi */
- int16 snr; /**< computed snginal-to-noise instantaneous snr */
- int8 rxpwr[ROUNDUP(WL_RSSI_ANT_MAX,2)]; /**< rssi for supported antennas */
- /**
- * Even though rxhdr can be in short or long format, always declare it here
- * to be in long format. So the offsets for the other fields are always the same.
- */
- d11rxhdr_t rxhdr;
-} BWL_POST_PACKED_STRUCT;
-
-/* SW RXHDR + HW RXHDR */
-typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
-
-/* extension of wlc_d11rxhdr..
- * This extra block can be used to store extra internal information that cannot fit into
- * wlc_d11rxhdr.
- * At the moment, it is only used to store and possibly transmit the per-core quater dbm rssi
- * information produced by the phy.
- * NOTE: To avoid header overhead and amsdu handling complexities this usage is limited to
- * only in case that host need to get the extra info. e.g., monitoring mode packet.
- */
-
-BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr_ext {
-#ifdef BCM_MON_QDBM_RSSI
- wlc_d11rxrssi_t rxpwr[WL_RSSI_ANT_MAX];
-#endif
- wlc_d11rxhdr_t wlc_d11rx;
-} BWL_POST_PACKED_STRUCT;
-
-typedef struct wlc_d11rxhdr_ext wlc_d11rxhdr_ext_t;
-
-/* Length of software rx header extension */
-#define WLC_SWRXHDR_EXT_LEN (OFFSETOF(wlc_d11rxhdr_ext_t, wlc_d11rx))
-
-/* Length of SW header (12 bytes) */
-#define WLC_RXHDR_LEN (OFFSETOF(wlc_d11rxhdr_t, rxhdr))
-/* Length of RX headers - SW header + HW/ucode/PHY RX status */
-#define WL_RXHDR_LEN(corerev, corerev_minor) \
- (WLC_RXHDR_LEN + D11_RXHDR_LEN(corerev, corerev_minor))
-#define WL_RXHDR_LEN_TMP(corerev, corerev_minor) \
- (WLC_RXHDR_LEN + D11_RXHDR_LEN_TMP(corerev, corerev_minor))
-
-/* This marks the end of a packed structure section. */
-#include <packed_section_end.h>
-
-/* Structure to hold d11 corerev information */
-typedef struct d11_info d11_info_t;
-struct d11_info {
- uint major_revid;
- uint minor_revid;
-};
-
-/* ulp dbg macro */
-#define HNDD11_DBG(x)
-#define HNDD11_ERR(x) printf x
-
-/* d11 slice index */
-#define DUALMAC_MAIN 0
-#define DUALMAC_AUX 1
-#define DUALMAC_SCAN 2
-
-extern void hndd11_read_shm(si_t *sih, uint coreunit, uint offset, void* buf);
-extern void hndd11_write_shm(si_t *sih, uint coreunit, uint offset, const void* buf);
-
-extern void hndd11_copyfrom_shm(si_t *sih, uint coreunit, uint offset, void* buf, int len);
-extern void hndd11_copyto_shm(si_t *sih, uint coreunit, uint offset, const void* buf, int len);
-
-extern uint32 hndd11_bm_read(osl_t *osh, d11regs_info_t *regsinfo, uint32 offset, uint32 len,
- uint32 *buf);
-extern uint32 hndd11_bm_write(osl_t *osh, d11regs_info_t *regsinfo, uint32 offset, uint32 len,
- const uint32 *buf);
-extern void hndd11_bm_dump(osl_t *osh, d11regs_info_t *regsinfo, uint32 offset, uint32 len);
-
-extern int hndd11_get_reginfo(si_t *sih, d11regs_info_t *regsinfo, uint coreunit);
-
-#endif /* _hndd11_h_ */
#define OSL_ENABLE_PREEMPTION(osh) osl_preempt_enable(osh)
#if (defined(BCMPCIE) && !defined(DHD_USE_COHERENT_MEM_FOR_RING) && defined(__ARM_ARCH_7A__))
-
extern void osl_cache_flush(void *va, uint size);
extern void osl_cache_inv(void *va, uint size);
extern void osl_prefetch(const void *ptr);
#define KMALLOC_FLAG (CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC)
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 170))
+#define RANDOM32 get_random_u32
+#define RANDOM_BYTES get_random_bytes
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
#define RANDOM32 prandom_u32
#define RANDOM_BYTES prandom_bytes
#else
+++ /dev/null
-/*
- * Monitor Mode definitions.
- * This header file housing the define and function prototype use by
- * both the wl firmware and drivers.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-#ifndef _MONITOR_H_
-#define _MONITOR_H_
-
-#include <bcmwifi_channels.h>
-
-#include <packed_section_start.h>
-/* wl_monitor rx status per packet */
-typedef struct BWL_PRE_PACKED_STRUCT wl_rxsts {
- uint pkterror; /* error flags per pkt */
- uint phytype; /* 802.11 A/B/G /N */
- chanspec_t chanspec; /* channel spec */
- uint16 datarate; /* rate in 500kbps */
- uint8 mcs; /* MCS for HT frame */
- uint8 htflags; /* HT modulation flags */
- uint antenna; /* antenna pkts received on */
- uint pktlength; /* pkt length minus bcm phy hdr */
- uint32 mactime; /* time stamp from mac, count per 1us */
- uint sq; /* signal quality */
- int32 signal; /* in dBm */
- int32 noise; /* in dBm */
- uint preamble; /* Unknown, short, long */
- uint encoding; /* Unknown, CCK, PBCC, OFDM, HT, VHT */
- uint nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
- uint8 nss; /* Number of spatial streams for VHT frame */
- uint8 coding;
- uint16 aid; /* Partial AID for VHT frame */
- uint8 gid; /* Group ID for VHT frame */
- uint8 bw; /* Bandwidth for VHT frame */
- uint16 vhtflags; /* VHT modulation flags */
- uint16 bw_nonht; /* non-HT bw advertised in rts/cts */
- uint32 ampdu_counter; /* AMPDU counter for sniffer */
- uint32 sig_a1; /* TODO: this unused field needs to be removed */
- uint32 sig_a2; /* TODO: this unused field needs to be removed */
- uint16 data1;
- uint16 data2;
- uint16 data3;
- uint16 data4;
- uint16 data5;
- uint16 data6;
- uint8 ru_channel1[4];
- uint8 ru_channel2[4];
- uint16 flag1;
- uint16 flag2;
-} BWL_POST_PACKED_STRUCT wl_rxsts_t, wl_mon_rxsts_t;
-#include <packed_section_end.h>
-
-#define WLMONRXSTS_SIZE sizeof(wl_rxsts_t)
-
-/* phy type */
-#define WL_RXS_PHY_N 0x00000004 /* N phy type */
-
-/* encoding */
-#define WL_RXS_ENCODING_UNKNOWN 0x00000000
-#define WL_RXS_ENCODING_DSSS_CCK 0x00000001 /* DSSS/CCK encoding (1, 2, 5.5, 11) */
-#define WL_RXS_ENCODING_OFDM 0x00000002 /* OFDM encoding */
-#define WL_RXS_ENCODING_HT 0x00000003 /* HT encoding */
-#define WL_RXS_ENCODING_VHT 0x00000004 /* VHT encoding */
-#define WL_RXS_ENCODING_HE 0x00000005 /* HE encoding */
-#define WL_RXS_ENCODING_EHT 0x00000006 /* EHT encoding */
-
-/* status per error RX pkt */
-#define WL_RXS_CRC_ERROR 0x00000001 /* CRC Error in packet */
-#define WL_RXS_RUNT_ERROR 0x00000002 /* Runt packet */
-#define WL_RXS_ALIGN_ERROR 0x00000004 /* Misaligned packet */
-#define WL_RXS_OVERSIZE_ERROR 0x00000008 /* packet bigger than RX_LENGTH (usually 1518) */
-#define WL_RXS_WEP_ICV_ERROR 0x00000010 /* Integrity Check Value error */
-#define WL_RXS_WEP_ENCRYPTED 0x00000020 /* Encrypted with WEP */
-#define WL_RXS_PLCP_SHORT 0x00000040 /* Short PLCP error */
-#define WL_RXS_DECRYPT_ERR 0x00000080 /* Decryption error */
-#define WL_RXS_OTHER_ERR 0x80000000 /* Other errors */
-
-/* preamble */
-#define WL_RXS_UNUSED_STUB 0x0 /**< stub to match with wlc_ethereal.h */
-#define WL_RXS_PREAMBLE_SHORT 0x00000001 /**< Short preamble */
-#define WL_RXS_PREAMBLE_LONG 0x00000002 /**< Long preamble */
-#define WL_RXS_PREAMBLE_HT_MM 0x00000003 /**< HT mixed mode preamble */
-#define WL_RXS_PREAMBLE_HT_GF 0x00000004 /**< HT green field preamble */
-
-/* htflags */
-#define WL_RXS_HTF_BW_MASK 0x07
-#define WL_RXS_HTF_40 0x01
-#define WL_RXS_HTF_20L 0x02
-#define WL_RXS_HTF_20U 0x04
-#define WL_RXS_HTF_SGI 0x08
-#define WL_RXS_HTF_STBC_MASK 0x30
-#define WL_RXS_HTF_STBC_SHIFT 4
-#define WL_RXS_HTF_LDPC 0x40
-
-#ifdef WLTXMONITOR
-/* reuse bw-bits in ht for vht */
-#define WL_RXS_VHTF_BW_MASK 0x87
-#define WL_RXS_VHTF_40 0x01
-#define WL_RXS_VHTF_20L WL_RXS_VHTF_20LL
-#define WL_RXS_VHTF_20U WL_RXS_VHTF_20LU
-#define WL_RXS_VHTF_80 0x02
-#define WL_RXS_VHTF_20LL 0x03
-#define WL_RXS_VHTF_20LU 0x04
-#define WL_RXS_VHTF_20UL 0x05
-#define WL_RXS_VHTF_20UU 0x06
-#define WL_RXS_VHTF_40L 0x07
-#define WL_RXS_VHTF_40U 0x80
-#endif /* WLTXMONITOR */
-
-/* vhtflags */
-#define WL_RXS_VHTF_STBC 0x01
-#define WL_RXS_VHTF_TXOP_PS 0x02
-#define WL_RXS_VHTF_SGI 0x04
-#define WL_RXS_VHTF_SGI_NSYM_DA 0x08
-#define WL_RXS_VHTF_LDPC_EXTRA 0x10
-#define WL_RXS_VHTF_BF 0x20
-#define WL_RXS_VHTF_DYN_BW_NONHT 0x40
-#define WL_RXS_VHTF_CODING_LDCP 0x01
-
-#define WL_RXS_VHT_BW_20 0
-#define WL_RXS_VHT_BW_40 1
-#define WL_RXS_VHT_BW_20L 2
-#define WL_RXS_VHT_BW_20U 3
-#define WL_RXS_VHT_BW_80 4
-#define WL_RXS_VHT_BW_40L 5
-#define WL_RXS_VHT_BW_40U 6
-#define WL_RXS_VHT_BW_20LL 7
-#define WL_RXS_VHT_BW_20LU 8
-#define WL_RXS_VHT_BW_20UL 9
-#define WL_RXS_VHT_BW_20UU 10
-#define WL_RXS_VHT_BW_160 11
-#define WL_RXS_VHT_BW_80L 12
-#define WL_RXS_VHT_BW_80U 13
-#define WL_RXS_VHT_BW_40LL 14
-#define WL_RXS_VHT_BW_40LU 15
-#define WL_RXS_VHT_BW_40UL 16
-#define WL_RXS_VHT_BW_40UU 17
-#define WL_RXS_VHT_BW_20LLL 18
-#define WL_RXS_VHT_BW_20LLU 19
-#define WL_RXS_VHT_BW_20LUL 20
-#define WL_RXS_VHT_BW_20LUU 21
-#define WL_RXS_VHT_BW_20ULL 22
-#define WL_RXS_VHT_BW_20ULU 23
-#define WL_RXS_VHT_BW_20UUL 24
-#define WL_RXS_VHT_BW_20UUU 25
-
-#define WL_RXS_NFRM_AMPDU_FIRST 0x00000001 /* first MPDU in A-MPDU */
-#define WL_RXS_NFRM_AMPDU_SUB 0x00000002 /* subsequent MPDU(s) in A-MPDU */
-#define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
-#define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
-
-/* HE flags */
-#define WL_RXS_HEF_SIGA_PPDU_SU 0x0000
-#define WL_RXS_HEF_SIGA_PPDU_EXT_SU 0x0001
-#define WL_RXS_HEF_SIGA_PPDU_MU 0x0002
-#define WL_RXS_HEF_SIGA_PPDU_TRIG 0x0003
-#define WL_RXS_HEF_SIGA_BSS_COLOR 0x0004
-#define WL_RXS_HEF_SIGA_BEAM_CHANGE 0x0008
-#define WL_RXS_HEF_SIGA_DL_UL 0x0010
-#define WL_RXS_HEF_SIGA_MCS 0x0020
-#define WL_RXS_HEF_SIGA_DCM 0x0040
-#define WL_RXS_HEF_SIGA_CODING 0x0080
-#define WL_RXS_HEF_SIGA_LDPC 0x0100
-#define WL_RXS_HEF_SIGA_STBC 0x0200
-#define WL_RXS_HEF_SIGA_SPATIAL_REUSE 0x0400
-#define WL_RXS_HEF_SIGA_STA_ID 0x0800
-#define WL_RXS_HEF_SIGA_SPATIAL_REUSE2 0x0800
-#define WL_RXS_HEF_SIGA_SPATIAL_REUSE3 0x1000
-#define WL_RXS_HEF_SIGA_SPATIAL_REUSE4 0x2000
-#define WL_RXS_HEF_SIGA_BW 0x4000
-#define WL_RXS_HEF_SIGA_RU_ALLOC 0x4000
-#define WL_RXS_HEF_SIGA_DOPPLER 0x8000
-#define WL_RXS_HEF_SIGA_GI 0x0002
-#define WL_RXS_HEF_SIGA_LTF_SIZE 0x0004 /* no explicit known field */
-#define WL_RXS_HEF_SIGA_NUM_LTF 0x0004
-#define WL_RXS_HEF_SIGA_PADDING 0x0008
-#define WL_RXS_HEF_SIGA_TXBF 0x0010
-#define WL_RXS_HEF_SIGA_PE 0x0020
-#define WL_RXS_HEF_SIGA_TXOP 0x0040
-#define WL_RXS_HEF_SIGA_MIDAMBLE 0x0080
-
-/* https://www.radiotap.org/fields/HE-MU.html */
-#define WL_RXS_HEF_SIGB_MCS_KNOWN 0x0010
-#define WL_RXS_HEF_SIGB_DCM_KNOWN 0x0040
-#define WL_RXS_HEF_CH2_26TONE_RU_KNOWN 0x0080
-#define WL_RXS_HEF_CH1_RU_KNOWN 0x0100
-#define WL_RXS_HEF_CH2_RU_KNOWN 0x0200
-#define WL_RXS_HEF_CH1_26TONE_RU_KNOWN 0x1000
-#define WL_RXS_HEF_SIGB_COMP_KNOWN 0x4000
-#define WL_RXS_HEF_NUM_SIGB_SYMB_KNOWN 0x8000
-#define WL_RXS_HEF_BW_SIGA_KNOWN 0x0004
-#define WL_RXS_HEF_PREPUNCR_SIGA_KNOWN 0x0400
-#define WL_RXS_HEF_SIGB_SYMB_KNOWN 0x8000
-#define WL_RXS_HEF_PREPUNCR_KNOWN 0x0400
-
-#include <packed_section_start.h>
-typedef struct BWL_PRE_PACKED_STRUCT wl_txsts {
- uint pkterror; /**< error flags per pkt */
- uint phytype; /**< 802.11 A/B/G /N */
- chanspec_t chanspec; /**< channel spec */
- uint16 datarate; /**< rate in 500kbps */
- uint8 mcs; /**< MCS for HT frame */
- uint8 htflags; /**< HT modulation flags */
- uint antenna; /**< antenna pkt transmitted on */
- uint pktlength; /**< pkt length minus bcm phy hdr */
- uint32 mactime; /**< ? time stamp from mac, count per 1us */
- uint preamble; /**< Unknown, short, long */
- uint encoding; /**< Unknown, CCK, PBCC, OFDM, HT */
- uint nfrmtype; /**< special 802.11n frames(AMPDU, AMSDU) */
- uint txflags; /**< As defined in radiotap field 15 */
- uint retries; /**< Number of retries */
- struct wl_if *wlif; /**< wl interface */
-} BWL_POST_PACKED_STRUCT wl_txsts_t;
-#include <packed_section_end.h>
-
-#define WL_TXS_TXF_FAIL 0x01 /**< TX failed due to excessive retries */
-#define WL_TXS_TXF_CTS 0x02 /**< TX used CTS-to-self protection */
-#define WL_TXS_TXF_RTSCTS 0x04 /**< TX used RTS/CTS */
-
-#endif /* _MONITOR_H_ */
+++ /dev/null
-/*
- * Misc utility routines for accessing chip-specific features
- * of the BOOKER NCI (non coherent interconnect) based Broadcom chips.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- *
- */
-
-#ifndef _NCI_H
-#define _NCI_H
-
-#include <siutils.h>
-
-#ifdef SOCI_NCI_BUS
-void nci_uninit(void *nci);
-uint32 nci_scan(si_t *sih);
-void nci_dump_erom(void *nci);
-void* nci_init(si_t *sih, chipcregs_t *cc, uint bustype);
-volatile void *nci_setcore(si_t *sih, uint coreid, uint coreunit);
-volatile void *nci_setcoreidx(si_t *sih, uint coreidx);
-uint nci_findcoreidx(const si_t *sih, uint coreid, uint coreunit);
-volatile uint32 *nci_corereg_addr(si_t *sih, uint coreidx, uint regoff);
-uint nci_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
-uint nci_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
-uint nci_corerev_minor(const si_t *sih);
-uint nci_corerev(const si_t *sih);
-uint nci_corevendor(const si_t *sih);
-uint nci_get_wrap_reg(const si_t *sih, uint32 offset, uint32 mask, uint32 val);
-void nci_core_reset(const si_t *sih, uint32 bits, uint32 resetbits);
-void nci_core_disable(const si_t *sih, uint32 bits);
-bool nci_iscoreup(const si_t *sih);
-uint32 nci_coreid(const si_t *sih, uint coreidx);
-uint nci_numcoreunits(const si_t *sih, uint coreid);
-uint32 nci_addr_space(const si_t *sih, uint spidx, uint baidx);
-uint32 nci_addr_space_size(const si_t *sih, uint spidx, uint baidx);
-bool nci_iscoreup(const si_t *sih);
-uint nci_intflag(si_t *sih);
-uint nci_flag(si_t *sih);
-uint nci_flag_alt(const si_t *sih);
-void nci_setint(const si_t *sih, int siflag);
-uint32 nci_oobr_baseaddr(const si_t *sih, bool second);
-uint nci_coreunit(const si_t *sih);
-uint nci_corelist(const si_t *sih, uint coreid[]);
-int nci_numaddrspaces(const si_t *sih);
-uint32 nci_addrspace(const si_t *sih, uint spidx, uint baidx);
-uint32 nci_addrspacesize(const si_t *sih, uint spidx, uint baidx);
-void nci_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size);
-uint32 nci_core_cflags(const si_t *sih, uint32 mask, uint32 val);
-void nci_core_cflags_wo(const si_t *sih, uint32 mask, uint32 val);
-uint32 nci_core_sflags(const si_t *sih, uint32 mask, uint32 val);
-uint nci_wrapperreg(const si_t *sih, uint32 offset, uint32 mask, uint32 val);
-void nci_invalidate_second_bar0win(si_t *sih);
-int nci_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read);
-int nci_backplane_access_64(si_t *sih, uint addr, uint size, uint64 *val, bool read);
-uint nci_num_slaveports(const si_t *sih, uint coreid);
-#if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_PHYDUMP)
-void nci_dumpregs(const si_t *sih, struct bcmstrbuf *b);
-#endif /* BCMDBG || BCMDBG_DUMP || BCMDBG_PHYDUMP */
-#ifdef BCMDBG
-void nci_view(si_t *sih, bool verbose);
-void nci_viewall(si_t *sih, bool verbose);
-#endif /* BCMDBG */
-uint32 nci_get_nth_wrapper(const si_t *sih, int32 wrap_pos);
-uint32 nci_get_axi_addr(const si_t *sih, uint32 *size);
-uint32* nci_wrapper_dump_binary_one(const si_info_t *sii, uint32 *p32, uint32 wrap_ba);
-uint32 nci_wrapper_dump_binary(const si_t *sih, uchar *p);
-uint32 nci_wrapper_dump_last_timeout(const si_t *sih, uint32 *error,
- uint32 *core, uint32 *ba, uchar *p);
-bool nci_check_enable_backplane_log(const si_t *sih);
-uint32 nci_get_core_baaddr(const si_t *sih, uint32 *size, int32 baidx);
-uint32 nci_clear_backplane_to(si_t *sih);
-uint32 nci_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void *wrap);
-bool nci_ignore_errlog(const si_info_t *sii, const aidmp_t *ai,
- uint32 lo_addr, uint32 hi_addr, uint32 err_axi_id, uint32 errsts);
-void nci_wrapper_get_last_error(const si_t *sih, uint32 *error_status, uint32 *core, uint32 *lo,
- uint32 *hi, uint32 *id);
-uint32 nci_get_axi_timeout_reg(void);
-uint32 nci_findcoreidx_by_axiid(const si_t *sih, uint32 axiid);
-uint32* nci_wrapper_dump_binary_one(const si_info_t *sii, uint32 *p32, uint32 wrap_ba);
-uint32 nci_wrapper_dump_binary(const si_t *sih, uchar *p);
-uint32 nci_wrapper_dump_last_timeout(const si_t *sih, uint32 *error,
- uint32 *core, uint32 *ba, uchar *p);
-bool nci_check_enable_backplane_log(const si_t *sih);
-uint32 ai_wrapper_dump_buf_size(const si_t *sih);
-uint32 nci_wrapper_dump_buf_size(const si_t *sih);
-#endif /* SOCI_NCI_BUS */
-#endif /* _NCI_H */
+++ /dev/null
-/*
- * SPROM format definitions for the Broadcom 47xx and 43xx chip family.
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#ifndef _SBSPROM_H
-#define _SBSPROM_H
-
-#include "typedefs.h"
-#include "bcmdevs.h"
-
-/* A word is this many bytes */
-#define SRW 2
-
-/* offset into PCI config space for write enable bit */
-#define CFG_SROM_WRITABLE_OFFSET 0x88
-#define SROM_WRITEABLE 0x10
-
-/* enumeration space consists of N contiguous 4Kbyte core register sets */
-#define SBCORES_BASE 0x18000000
-#define SBCORES_EACH 0x1000
-
-/* offset from BAR0 for srom space */
-#define SROM_BASE 4096
-
-/* number of 2-byte words in srom */
-#define SROM_SIZE 64
-
-#define SROM_BYTES (SROM_SIZE * SRW)
-
-#define MAX_FN 4
-
-/* Word 0, Hardware control */
-#define SROM_HWCTL 0
-#define HW_FUNMSK 0x000f
-#define HW_FCLK 0x0200
-#define HW_CBM 0x0400
-#define HW_PIMSK 0xf000
-#define HW_PISHIFT 12
-#define HW_PI4402 0x2
-#define HW_FUN4401 0x0001
-#define HW_FCLK4402 0x0000
-
-/* Word 1, common-power/boot-rom */
-#define SROM_COMMPW 1
-/* boot rom present bit */
-#define BR_PRESSHIFT 8
-/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
-#define BR_SIZESHIFT 9
-
-/* Word 2, SubsystemId */
-#define SROM_SSID 2
-
-/* Word 3, VendorId */
-#define SROM_VID 3
-
-/* Function 0 info, function info length */
-#define SROM_FN0 4
-#define SROM_FNSZ 8
-
-/* Within each function: */
-/* Word 0, deviceID */
-#define SRFN_DID 0
-
-/* Words 1-2, ClassCode */
-#define SRFN_CCL 1
-/* Word 2, D0 Power */
-#define SRFN_CCHD0 2
-
-/* Word 3, PME and D1D2D3 power */
-#define SRFN_PMED123 3
-
-#define PME_IL 0
-#define PME_ENET0 1
-#define PME_ENET1 2
-#define PME_CODEC 3
-
-#define PME_4402_ENET 0
-#define PME_4402_CODEC 1
-#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
-
-/* Word 4, Bar1 enable, pme reports */
-#define SRFN_B1PMER 4
-#define B1E 1
-#define B1SZMSK 0xe
-#define B1SZSH 1
-#define PMERMSK 0x0ff0
-#define PME 0x0010
-#define PMERD0 0x0020
-#define PMERD1 0x0040
-#define PMERD2 0x0080
-#define PMERD3H 0x0100
-#define PMERD3CA 0x0200
-#define PMERD3CV 0x0400
-#define IGNCLKRR 0x0800
-#define B0LMSK 0xf000
-
-/* Words 4-5, Bar0 Sonics value */
-#define SRFN_B0H 5
-/* Words 6-7, CIS Pointer */
-#define SRFN_CISL 6
-#define SRFN_CISH 7
-
-/* Words 36-38: iLine MAC address */
-#define SROM_I_MACHI 36
-#define SROM_I_MACMID 37
-#define SROM_I_MACLO 38
-
-/* Words 36-38: wireless0 MAC address on 43xx */
-#define SROM_W0_MACHI 36
-#define SROM_W0_MACMID 37
-#define SROM_W0_MACLO 38
-
-/* Words 39-41: enet0 MAC address */
-#define SROM_E0_MACHI 39
-#define SROM_E0_MACMID 40
-#define SROM_E0_MACLO 41
-
-/* Words 42-44: enet1 MAC address */
-#define SROM_E1_MACHI 42
-#define SROM_E1_MACMID 43
-#define SROM_E1_MACLO 44
-
-#define SROM_EPHY 45
-
-/* Words 47-51 wl0 PA bx */
-#define SROM_WL0_PAB0 47
-#define SROM_WL0_PAB1 48
-#define SROM_WL0_PAB2 49
-#define SROM_WL0_PAB3 50
-#define SROM_WL0_PAB4 51
-
-/* Word 52: wl0/wl1 MaxPower */
-#define SROM_WL_MAXPWR 52
-
-/* Words 53-55 wl1 PA bx */
-#define SROM_WL1_PAB0 53
-#define SROM_WL1_PAB1 54
-#define SROM_WL1_PAB2 55
-
-/* Woprd 56: itt */
-#define SROM_ITT 56
-
-/* Words 59-62: OEM Space */
-#define SROM_WL_OEM 59
-#define SROM_OEM_SIZE 4
-
-/* Contents for the srom */
-
-#define BU4710_SSID 0x0400
-#define VSIM4710_SSID 0x0401
-#define QT4710_SSID 0x0402
-
-#define BU4610_SSID 0x0403
-#define VSIM4610_SSID 0x0404
-
-#define BU4402_SSID 0x4402
-
-#define CLASS_OTHER 0x8000
-#define CLASS_ETHER 0x0000
-#define CLASS_NET 0x0002
-#define CLASS_COMM 0x0007
-#define CLASS_MODEM 0x0300
-#define CLASS_MIPS 0x3000
-#define CLASS_PROC 0x000b
-#define CLASS_FLASH 0x0100
-#define CLASS_MEM 0x0005
-#define CLASS_SERIALBUS 0x000c
-#define CLASS_OHCI 0x0310
-
-/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
-#define MACHI 0x90
-
-#define MACMID_BU4710I 0x4c17
-#define MACMID_BU4710E0 0x4c18
-#define MACMID_BU4710E1 0x4c19
-
-#define MACMID_94710R1I 0x4c1a
-#define MACMID_94710R1E0 0x4c1b
-#define MACMID_94710R1E1 0x4c1c
-
-#define MACMID_94710R4I 0x4c1d
-#define MACMID_94710R4E0 0x4c1e
-#define MACMID_94710R4E1 0x4c1f
-
-#define MACMID_94710DEVI 0x4c20
-#define MACMID_94710DEVE0 0x4c21
-#define MACMID_94710DEVE1 0x4c22
-
-#define MACMID_BU4402 0x4c23
-
-#define MACMID_BU4610I 0x4c24
-#define MACMID_BU4610E0 0x4c25
-#define MACMID_BU4610E1 0x4c26
-
-#define MACMID_BU4401 0x4c37
-
-/* Enet phy settings one or two singles or a dual */
-/* Bits 4-0 : MII address for enet0 (0x1f for not there */
-/* Bits 9-5 : MII address for enet1 (0x1f for not there */
-/* Bit 14 : Mdio for enet0 */
-/* Bit 15 : Mdio for enet1 */
-
-/* bu4710 with only one phy on enet1 with address 7: */
-#define SROM_EPHY_ONE 0x80ff
-
-/* bu4710 with two individual phys, at 6 and 7, */
-/* each mdio connected to its own mac: */
-#define SROM_EPHY_TWO 0x80e6
-
-/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
-/* bringup board has phyaddr0 and phyaddr1 swapped */
-#define SROM_EPHY_DUAL 0x0001
-
-/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
-#define SROM_EPHY_R1 0x0010
-
-/* r4 board with a single phy on enet0 at address 5 and a switch */
-/* chip on enet1 (speciall case: 0x1e */
-#define SROM_EPHY_R4 0x83e5
-
-/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
-#define SROM_EPHY_INTERNAL 0x0001
-
-#define SROM_VERS 0x0001
-
-#endif /* _SBSPROM_H */
+++ /dev/null
-/*
- * Misc utility routines for accessing chip-specific features
- * of the BOOKER NCI (non coherent interconnect) based Broadcom chips.
- *
- * Broadcom Proprietary and Confidential. Copyright (C) 2020,
- * All Rights Reserved.
- *
- * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom;
- * the contents of this file may not be disclosed to third parties,
- * copied or duplicated in any form, in whole or in part, without
- * the prior written permission of Broadcom.
- *
- *
- * <<Broadcom-WL-IPTag/Proprietary:>>
- */
-
-#include <typedefs.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <pcicfg.h>
-#include <pcie_core.h>
-#include "siutils_priv.h"
-#include <nci.h>
-#include <bcmdevs.h>
-#include <hndoobr.h>
-
-#define NCI_BAD_REG 0xbbadd000u /* Bad Register Address */
-#define NCI_BAD_INDEX -1 /* Bad Index */
-
-#define OOBR_BASE_MASK 0x00001FFFu /* Mask to get Base address of OOBR */
-#define EROM1_BASE_MASK 0x00000FFFu /* Mask to get Base address of EROM1 */
-
-/* Core Info */
-#define COREINFO_COREID_MASK 0x00000FFFu /* Bit-11 to 0 */
-#define COREINFO_REV_MASK 0x000FF000u /* Core Rev Mask */
-#define COREINFO_REV_SHIFT 12u /* Bit-12 */
-#define COREINFO_MFG_MASK 0x00F00000u /* Core Mfg Mask */
-#define COREINFO_MFG_SHIFT 20u /* Bit-20 */
-#define COREINFO_BPID_MASK 0x07000000u /* 26-24 Gives Backplane ID */
-#define COREINFO_BPID_SHIFT 24u /* Bit:26-24 */
-#define COREINFO_ISBP_MASK 0x08000000u /* Is Backplane or Bridge */
-#define COREINFO_ISBP_SHIFT 27u /* Bit:27 */
-
-/* Interface Config */
-#define IC_IFACECNT_MASK 0x0000F000u /* No of Interface Descriptor Mask */
-#define IC_IFACECNT_SHIFT 12u /* Bit-12 */
-#define IC_IFACEOFFSET_MASK 0x00000FFFu /* OFFSET for 1st Interface Descriptor */
-
-/* DMP Reg Offset */
-#define DMP_DMPCTRL_REG_OFFSET 8u
-
-/* Interface Descriptor Masks */
-#define ID_NODEPTR_MASK 0xFFFFFFF8u /* Master/Slave Network Interface Addr */
-#define ID_NODETYPE_MASK 0x00000007u /* 0:Booker 1:IDM 1-0xf:Reserved */
-#define ID_WORDOFFSET_MASK 0xF0000000u /* WordOffset to next Iface Desc in EROM2 */
-#define ID_WORDOFFSET_SHIFT 28u /* WordOffset bits 31-28 */
-#define ID_CORETYPE_MASK 0x08000000u /* CORE belongs to OOBR(0) or EROM(1) */
-#define ID_CORETYPE_SHIFT 27u /* Bit-27 */
-#define ID_MI_MASK 0x04000000u /* 0: Slave Interface, 1:Master Interface */
-#define ID_MI_SHIFT 26u /* Bit-26 */
-#define ID_NADDR_MASK 0x03000000u /* No of Slave Address Regions */
-#define ID_NADDR_SHIFT 24u /* Bit:25-24 */
-#define ID_BPID_MASK 0x00F00000u /* Give Backplane ID */
-#define ID_BPID_SHIFT 20u /* Bit:20-23 */
-#define ID_COREINFOPTR_MASK 0x00001FFFu /* OOBR or EROM Offset */
-#define ID_ENDMARKER 0xFFFFFFFFu /* End of EROM Part 2 */
-
-/* Slave Port Address Descriptor Masks */
-#define SLAVEPORT_BASE_ADDR_MASK 0xFFFFFF00u /* Bits 31:8 is the base address */
-#define SLAVEPORT_BOUND_ADDR_MASK 0x00000040u /* Addr is not 2^n and with bound addr */
-#define SLAVEPORT_BOUND_ADDR_SHIFT 6u /* Bit-6 */
-#define SLAVEPORT_64BIT_ADDR_MASK 0x00000020u /* 64-bit base and bound fields */
-#define SLAVEPORT_64BIT_ADDR_SHIFT 5u /* Bit-5 */
-#define SLAVEPORT_ADDR_SIZE_MASK 0x0000001Fu /* Address Size mask */
-#define SLAVEPORT_ADDR_TYPE_BOUND 0x1u /* Bound Addr */
-#define SLAVEPORT_ADDR_TYPE_64 0x2u /* 64-Bit Addr */
-#define SLAVEPORT_ADDR_MIN_SHIFT 0x8u
-/* Address space Size of the slave port */
-#define SLAVEPORT_ADDR_SIZE(adesc) (1u << ((adesc & SLAVEPORT_ADDR_SIZE_MASK) + \
- SLAVEPORT_ADDR_MIN_SHIFT))
-
-#define GET_NEXT_EROM_ADDR(addr) ((uint32*)((uintptr)(addr) + 4u))
-
-#define NCI_DEFAULT_CORE_UNIT (0u)
-
-/* Error Codes */
-enum {
- NCI_OK = 0,
- NCI_BACKPLANE_ID_MISMATCH = -1,
- NCI_INVALID_EROM2PTR = -2,
- NCI_WORDOFFSET_MISMATCH = -3,
- NCI_NOMEM = -4,
- NCI_MASTER_INVALID_ADDR = -5
-};
-
-#define GET_OOBR_BASE(erom2base) ((erom2base) & ~OOBR_BASE_MASK)
-#define GET_EROM1_BASE(erom2base) ((erom2base) & ~EROM1_BASE_MASK)
-#define CORE_ID(core_info) ((core_info) & COREINFO_COREID_MASK)
-#define GET_INFACECNT(iface_cfg) (((iface_cfg) & IC_IFACECNT_MASK) >> IC_IFACECNT_SHIFT)
-#define GET_NODEPTR(iface_desc_0) ((iface_desc_0) & ID_NODEPTR_MASK)
-#define GET_NODETYPE(iface_desc_0) ((iface_desc_0) & ID_NODETYPE_MASK)
-#define GET_WORDOFFSET(iface_desc_1) (((iface_desc_1) & ID_WORDOFFSET_MASK) \
- >> ID_WORDOFFSET_SHIFT)
-#define IS_MASTER(iface_desc_1) (((iface_desc_1) & ID_MI_MASK) >> ID_MI_SHIFT)
-#define GET_CORETYPE(iface_desc_1) (((iface_desc_1) & ID_CORETYPE_MASK) >> ID_CORETYPE_SHIFT)
-#define GET_NUM_ADDR_REG(iface_desc_1) (((iface_desc_1) & ID_NADDR_MASK) >> ID_NADDR_SHIFT)
-#define GET_COREOFFSET(iface_desc_1) ((iface_desc_1) & ID_COREINFOPTR_MASK)
-#define ADDR_SIZE(sz) ((1u << ((sz) + 8u)) - 1u)
-
-#define CORE_REV(core_info) ((core_info) & COREINFO_REV_MASK) >> COREINFO_REV_SHIFT
-#define CORE_MFG(core_info) ((core_info) & COREINFO_MFG_MASK) >> COREINFO_MFG_SHIFT
-#define COREINFO_BPID(core_info) (((core_info) & COREINFO_BPID_MASK) >> COREINFO_BPID_SHIFT)
-#define IS_BACKPLANE(core_info) (((core_info) & COREINFO_ISBP_MASK) >> COREINFO_ISBP_SHIFT)
-#define ID_BPID(iface_desc_1) (((iface_desc_1) & ID_BPID_MASK) >> ID_BPID_SHIFT)
-#define IS_BACKPLANE_ID_SAME(core_info, iface_desc_1) \
- (COREINFO_BPID((core_info)) == ID_BPID((iface_desc_1)))
-
-#define NCI_WORD_SIZE (4u)
-#define PCI_ACCESS_SIZE (4u)
-
-#define NCI_ADDR2NUM(addr) ((uintptr)(addr))
-#define NCI_ADD_NUM(addr, size) (NCI_ADDR2NUM(addr) + (size))
-#ifdef DONGLEBUILD
-#define NCI_ADD_ADDR(addr, size) ((uint32*)REG_MAP(NCI_ADD_NUM((addr), (size)), 0u))
-#else /* !DONGLEBUILD */
-#define NCI_ADD_ADDR(addr, size) ((uint32*)(NCI_ADD_NUM((addr), (size))))
-#endif /* DONGLEBUILD */
-#define NCI_INC_ADDR(addr, size) ((addr) = NCI_ADD_ADDR((addr), (size)))
-
-#define NODE_TYPE_BOOKER 0x0u
-#define NODE_TYPE_NIC400 0x1u
-
-#define BP_BOOKER 0x0u
-#define BP_NIC400 0x1u
-#define BP_APB1 0x2u
-#define BP_APB2 0x3u
-#define BP_CCI400 0x4u
-
-#define PCIE_WRITE_SIZE 4u
-
-static const char BACKPLANE_ID_NAME[][11] = {
- "BOOKER",
- "NIC400",
- "APB1",
- "APB2",
- "CCI400",
- "\0"
-};
-
-#define APB_INF(ifd) ((ID_BPID((ifd).iface_desc_1) == BP_APB1) || \
- (ID_BPID((ifd).iface_desc_1) == BP_APB2))
-#define BOOKER_INF(ifd) (ID_BPID((ifd).iface_desc_1) == BP_BOOKER)
-#define NIC_INF(ifd) (ID_BPID((ifd).iface_desc_1) == BP_NIC400)
-
-/* BOOKER NCI LOG LEVEL */
-#define NCI_LOG_LEVEL_ERROR 0x1u
-#define NCI_LOG_LEVEL_TRACE 0x2u
-#define NCI_LOG_LEVEL_INFO 0x4u
-#define NCI_LOG_LEVEL_PRINT 0x8u
-
-#ifndef NCI_DEFAULT_LOG_LEVEL
-#define NCI_DEFAULT_LOG_LEVEL (NCI_LOG_LEVEL_ERROR)
-#endif /* NCI_DEFAULT_LOG_LEVEL */
-
-uint32 nci_log_level = NCI_DEFAULT_LOG_LEVEL;
-
-#ifdef DONGLEBUILD
-#define NCI_ERROR(args) do { if (nci_log_level & NCI_LOG_LEVEL_ERROR) { printf args; } } while (0u)
-#define NCI_TRACE(args) do { if (nci_log_level & NCI_LOG_LEVEL_TRACE) { printf args; } } while (0u)
-#define NCI_INFO(args) do { if (nci_log_level & NCI_LOG_LEVEL_INFO) { printf args; } } while (0u)
-#define NCI_PRINT(args) do { if (nci_log_level & NCI_LOG_LEVEL_PRINT) { printf args; } } while (0u)
-#else /* !DONGLEBUILD */
-#define NCI_KERN_PRINT(...) printk(KERN_ERR __VA_ARGS__)
-#define NCI_ERROR(args) do { if (nci_log_level & NCI_LOG_LEVEL_ERROR) \
- { NCI_KERN_PRINT args; } } while (0u)
-#define NCI_TRACE(args) do { if (nci_log_level & NCI_LOG_LEVEL_TRACE) \
- { NCI_KERN_PRINT args; } } while (0u)
-#define NCI_INFO(args) do { if (nci_log_level & NCI_LOG_LEVEL_INFO) \
- { NCI_KERN_PRINT args; } } while (0u)
-#define NCI_PRINT(args) do { if (nci_log_level & NCI_LOG_LEVEL_PRINT) \
- { NCI_KERN_PRINT args; } } while (0u)
-#endif /* DONGLEBUILD */
-
-#define NCI_EROM_WORD_SIZEOF 4u
-#define NCI_REGS_PER_CORE 2u
-
-#define NCI_EROM1_LEN(erom2base) (erom2base - GET_EROM1_BASE(erom2base))
-#define NCI_NONOOBR_CORES(erom2base) NCI_EROM1_LEN(erom2base) \
- /(NCI_REGS_PER_CORE * NCI_EROM_WORD_SIZEOF)
-
-/* AXI ID to CoreID + unit mappings */
-typedef struct nci_axi_to_coreidx {
- uint coreid;
- uint coreunit;
-} nci_axi_to_coreidx_t;
-
-static const nci_axi_to_coreidx_t axi2coreidx_4397[] = {
- {CC_CORE_ID, 0}, /* 00 Chipcommon */
- {PCIE2_CORE_ID, 0}, /* 01 PCIe */
- {D11_CORE_ID, 0}, /* 02 D11 Main */
- {ARMCR4_CORE_ID, 0}, /* 03 ARM */
- {BT_CORE_ID, 0}, /* 04 BT AHB */
- {D11_CORE_ID, 1}, /* 05 D11 Aux */
- {D11_CORE_ID, 0}, /* 06 D11 Main l1 */
- {D11_CORE_ID, 1}, /* 07 D11 Aux l1 */
- {D11_CORE_ID, 0}, /* 08 D11 Main l2 */
- {D11_CORE_ID, 1}, /* 09 D11 Aux l2 */
- {NODEV_CORE_ID, 0}, /* 10 M2M DMA */
- {NODEV_CORE_ID, 0}, /* 11 unused */
- {NODEV_CORE_ID, 0}, /* 12 unused */
- {NODEV_CORE_ID, 0}, /* 13 unused */
- {NODEV_CORE_ID, 0}, /* 14 unused */
- {NODEV_CORE_ID, 0} /* 15 unused */
-};
-
-typedef struct slave_port {
- uint32 adesc; /**< Address Descriptor 0 */
- uint32 addrl; /**< Lower Base */
- uint32 addrh; /**< Upper Base */
- uint32 extaddrl; /**< Lower Bound */
- uint32 extaddrh; /**< Ubber Bound */
-} slave_port_t;
-
-typedef struct interface_desc {
- slave_port_t *sp; /**< Slave Port Addr 0-3 */
-
- uint32 iface_desc_0; /**< Interface-0 Descriptor Word0 */
- /* If Node Type 0-Booker xMNI/xSNI address. If Node Type 1-DMP wrapper Address */
- uint32 node_ptr; /**< Core's Node pointer */
-
- uint32 iface_desc_1; /**< Interface Descriptor Word1 */
- uint8 num_addr_reg; /**< Number of Slave Port Addr (Valid only if master=0) */
- uint8 coretype; /**< Core Belongs to 0:OOBR 1:Without OOBR */
- uint8 master; /**< 1:Master 0:Slave */
-
- uint8 node_type; /**< 0:Booker , 1:IDM Wrapper, 2-0xf: Reserved */
-} interface_desc_t;
-
-typedef struct nci_cores {
- void *regs;
- /* 2:0-Node type (0-booker,1-IDM Wrapper) 31:3-Interconnect registyer space */
- interface_desc_t *desc; /**< Interface & Address Descriptors */
- /*
- * 11:0-CoreID, 19:12-RevID 23:20-MFG 26:24-Backplane ID if
- * bit 27 is 1 (Core is Backplane or Bridge )
- */
- uint32 coreinfo; /**< CoreInfo of each core */
- /*
- * 11:0 - Offosewt of 1st Interface desc in EROM 15:12 - No.
- * of interfaces attachedto this core
- */
- uint32 iface_cfg; /**< Interface config Reg */
- uint32 dmp_regs_off; /**< DMP control & DMP status @ 0x48 from coreinfo */
- uint32 coreid; /**< id of each core */
- uint8 coreunit; /**< Unit differentiate same coreids */
- uint8 iface_cnt; /**< no of Interface connected to each core */
- uint8 PAD[2u];
-} nci_cores_t;
-
-typedef struct nci_info {
- void *osh; /**< osl os handle */
- nci_cores_t *cores; /**< Cores Parsed */
- void *pci_bar_addr; /**< PCI BAR0 Window */
- uint32 cc_erom2base; /**< Base of EROM2 from ChipCommon */
- uint32 *erom1base; /**< Base of EROM1 */
- uint32 *erom2base; /**< Base of EROM2 */
- uint32 *oobr_base; /**< Base of OOBR */
- uint16 bustype; /**< SI_BUS, PCI_BUS */
- uint8 max_cores; /**< # Max cores indicated by Register */
- uint8 num_cores; /**< # discovered cores */
- uint8 refcnt; /**< Allocation reference count */
- uint8 scan_done; /**< Set to TRUE when erom scan is done. */
- uint8 PAD[2];
-} nci_info_t;
-
-#define NI_IDM_RESET_ENTRY 0x1
-#define NI_IDM_RESET_EXIT 0x0
-
-/* AXI Slave Network Interface registers */
-typedef volatile struct asni_regs {
- uint32 node_type; /* 0x000 */
- uint32 node_info; /* 0x004 */
- uint32 secr_acc; /* 0x008 */
- uint32 pmusela; /* 0x00c */
- uint32 pmuselb; /* 0x010 */
- uint32 PAD[11];
- uint32 node_feat; /* 0x040 */
- uint32 bursplt; /* 0x044 */
- uint32 addr_remap; /* 0x048 */
- uint32 PAD[13];
- uint32 sildbg; /* 0x080 */
- uint32 qosctl; /* 0x084 */
- uint32 wdatthrs; /* 0x088 */
- uint32 arqosovr; /* 0x08c */
- uint32 awqosovr; /* 0x090 */
- uint32 atqosot; /* 0x094 */
- uint32 arqosot; /* 0x098 */
- uint32 awqosot; /* 0x09c */
- uint32 axqosot; /* 0x0a0 */
- uint32 qosrdpk; /* 0x0a4 */
- uint32 qosrdbur; /* 0x0a8 */
- uint32 qosrdavg; /* 0x0ac */
- uint32 qoswrpk; /* 0x0b0 */
- uint32 qoswrbur; /* 0x0b4 */
- uint32 qoswravg; /* 0x0b8 */
- uint32 qoscompk; /* 0x0bc */
- uint32 qoscombur; /* 0x0c0 */
- uint32 qoscomavg; /* 0x0c4 */
- uint32 qosrbbqv; /* 0x0c8 */
- uint32 qoswrbqv; /* 0x0cc */
- uint32 qoscombqv; /* 0x0d0 */
- uint32 PAD[11];
- uint32 idm_device_id; /* 0x100 */
- uint32 PAD[15];
- uint32 idm_reset_ctrl; /* 0x140 */
-} asni_regs_t;
-
-/* AXI Master Network Interface registers */
-typedef volatile struct amni_regs {
- uint32 node_type; /* 0x000 */
- uint32 node_info; /* 0x004 */
- uint32 secr_acc; /* 0x008 */
- uint32 pmusela; /* 0x00c */
- uint32 pmuselb; /* 0x010 */
- uint32 PAD[11];
- uint32 node_feat; /* 0x040 */
- uint32 PAD[15];
- uint32 sildbg; /* 0x080 */
- uint32 qosacc; /* 0x084 */
- uint32 PAD[26];
- uint32 interrupt_status; /* 0x0f0 */
- uint32 interrupt_mask; /* 0x0f4 */
- uint32 interrupt_status_ns; /* 0x0f8 */
- uint32 interrupt_mask_ns; /* 0x0FC */
- uint32 idm_device_id; /* 0x100 */
- uint32 PAD[15];
- uint32 idm_reset_ctrl; /* 0x140 */
-} amni_regs_t;
-
-#define NCI_SPINWAIT_TIMEOUT (300u)
-
-/* DMP/io control and DMP/io status */
-typedef struct dmp_regs {
- uint32 dmpctrl;
- uint32 dmpstatus;
-} dmp_regs_t;
-
-#ifdef _RTE_
-static nci_info_t *knci_info = NULL;
-#endif /* _RTE_ */
-
-static void nci_save_iface1_reg(interface_desc_t *desc, uint32 iface_desc_1);
-static uint32* nci_save_slaveport_addr(nci_info_t *nci,
- interface_desc_t *desc, uint32 *erom2ptr);
-static int nci_get_coreunit(nci_cores_t *cores, uint32 numcores, uint cid,
- uint32 iface_desc_1);
-static nci_cores_t* nci_initial_parse(nci_info_t *nci, uint32 *erom2ptr, uint32 *core_idx);
-static void _nci_setcoreidx_pcie_bus(si_t *sih, volatile void **regs, uint32 curmap,
- uint32 curwrap);
-static volatile void *_nci_setcoreidx(si_t *sih, uint coreidx);
-static uint32 _nci_get_curwrap(nci_info_t *nci, uint coreidx, uint wrapper_idx);
-static uint32 nci_get_curwrap(nci_info_t *nci, uint coreidx);
-static uint32 _nci_get_curmap(nci_info_t *nci, uint coreidx, uint slave_port_idx, uint base_idx);
-static uint32 nci_get_curmap(nci_info_t *nci, uint coreidx);
-static void _nci_core_reset(const si_t *sih, uint32 bits, uint32 resetbits);
-#if defined (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC)
-static void nci_reset_APB(const si_info_t *sii, aidmp_t *ai, int *ret,
- uint32 errlog_status, uint32 errlog_id);
-static void nci_reset_axi_to(const si_info_t *sii, aidmp_t *ai);
-#endif /* (AXI_TIMEOUTS) || (AXI_TIMEOUTS_NIC) */
-static uint32 nci_find_numcores(si_t *sih);
-#ifdef BOOKER_NIC400_INF
-static int32 nci_find_first_wrapper_idx(nci_info_t *nci, uint32 coreidx);
-#endif /* BOOKER_NIC400_INF */
-
-/*
- * Description : This function will search for a CORE with matching 'core_id' and mismatching
- * 'wordoffset', if found then increments 'coreunit' by 1.
- */
-/* TODO: Need to understand this. */
-static int
-BCMATTACHFN(nci_get_coreunit)(nci_cores_t *cores, uint32 numcores,
- uint core_id, uint32 iface_desc_1)
-{
- uint32 core_idx;
- uint32 coreunit = NCI_DEFAULT_CORE_UNIT;
-
- for (core_idx = 0u; core_idx < numcores; core_idx++) {
- if ((cores[core_idx].coreid == core_id) &&
- (GET_COREOFFSET(cores[core_idx].desc->iface_desc_1) !=
- GET_COREOFFSET(iface_desc_1))) {
- coreunit = cores[core_idx].coreunit + 1;
- }
- }
-
- return coreunit;
-}
-
-/*
- * OOBR Region
- +-------------------------------+
- + +
- + OOBR with EROM Data +
- + +
- +-------------------------------+
- + +
- + EROM1 +
- + +
- +-------------------------------+ --> ChipCommon.EROMBASE
- + +
- + EROM2 +
- + +
- +-------------------------------+
-*/
-
-/**
- * Function : nci_init
- * Description : Malloc's memory related to 'nci_info_t' and its internal elements.
- *
- * @paramter[in]
- * @regs : This is a ChipCommon Regster
- * @bustype : Bus Connect Type
- *
- * Return : On Succes 'nci_info_t' data structure is returned as void,
- * where all EROM parsed Cores are saved,
- * using this all EROM Cores are Freed.
- * On Failure 'NULL' is returned by printing ERROR messages
- */
-void*
-BCMATTACHFN(nci_init)(si_t *sih, chipcregs_t *cc, uint bustype)
-{
- si_info_t *sii = SI_INFO(sih);
- nci_cores_t *cores;
- nci_info_t *nci = NULL;
- uint8 err_at = 0u;
-
-#ifdef _RTE_
- if (knci_info) {
- knci_info->refcnt++;
- nci = knci_info;
-
- goto end;
- }
-#endif /* _RTE_ */
-
- /* It is used only when NCI_ERROR is used */
- BCM_REFERENCE(err_at);
-
- if ((nci = MALLOCZ(sii->osh, sizeof(*nci))) == NULL) {
- err_at = 1u;
- goto end;
- }
- sii->nci_info = nci;
-
- nci->osh = sii->osh;
- nci->refcnt++;
-
- nci->cc_erom2base = R_REG(nci->osh, &cc->eromptr);
- nci->bustype = bustype;
- switch (nci->bustype) {
- case SI_BUS:
- nci->erom2base = (uint32*)REG_MAP(nci->cc_erom2base, 0u);
- nci->oobr_base = (uint32*)REG_MAP(GET_OOBR_BASE(nci->cc_erom2base), 0u);
- nci->erom1base = (uint32*)REG_MAP(GET_EROM1_BASE(nci->cc_erom2base), 0u);
-
- break;
-
- case PCI_BUS:
- /* Set wrappers address */
- sii->curwrap = (void *)((uintptr)cc + SI_CORE_SIZE);
- /* Set access window to Erom Base(For NCI, EROM starts with OOBR) */
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_EROM1_BASE(nci->cc_erom2base));
- nci->erom1base = (uint32*)((uintptr)cc);
- nci->erom2base = (uint32*)((uintptr)cc + NCI_EROM1_LEN(nci->cc_erom2base));
-
- break;
-
- default:
- err_at = 2u;
- ASSERT(0u);
- goto end;
- }
-
- nci->max_cores = nci_find_numcores(sih);
- if (!nci->max_cores) {
- err_at = 3u;
- goto end;
- }
-
- if ((cores = MALLOCZ(nci->osh, sizeof(*cores) * nci->max_cores)) == NULL) {
- err_at = 4u;
- goto end;
- }
- nci->cores = cores;
-
-#ifdef _RTE_
- knci_info = nci;
-#endif /* _RTE_ */
-
-end:
- if (err_at) {
- NCI_ERROR(("nci_init: Failed err_at=%#x\n", err_at));
- nci_uninit(nci);
- nci = NULL;
- }
-
- return nci;
-}
-
-/**
- * Function : nci_uninit
- * Description : Free's memory related to 'nci_info_t' and its internal malloc'd elements.
- *
- * @paramter[in]
- * @nci : This is 'nci_info_t' data structure, where all EROM parsed Cores are saved, using this
- * all EROM Cores are Freed.
- *
- * Return : void
- */
-void
-BCMATTACHFN(nci_uninit)(void *ctx)
-{
- nci_info_t *nci = (nci_info_t *)ctx;
- uint8 core_idx, desc_idx;
- interface_desc_t *desc;
- nci_cores_t *cores;
- slave_port_t *sp;
-
- if (nci == NULL) {
- return;
- }
-
- nci->refcnt--;
-
-#ifdef _RTE_
- if (nci->refcnt != 0) {
- return;
- }
-#endif /* _RTE_ */
-
- cores = nci->cores;
- if (cores == NULL) {
- goto end;
- }
-
- for (core_idx = 0u; core_idx < nci->num_cores; core_idx++) {
- desc = cores[core_idx].desc;
- if (desc == NULL) {
- break;
- }
-
- for (desc_idx = 0u; desc_idx < cores[core_idx].iface_cnt; desc_idx++) {
- sp = desc[desc_idx].sp;
- if (sp) {
- MFREE(nci->osh, sp, (sizeof(*sp) * desc[desc_idx].num_addr_reg));
- }
- }
- MFREE(nci->osh, desc, (sizeof(*desc) * cores[core_idx].iface_cnt));
- }
- MFREE(nci->osh, cores, sizeof(*cores) * nci->max_cores);
-
-end:
-
-#ifdef _RTE_
- knci_info = NULL;
-#endif /* _RTE_ */
-
- MFREE(nci->osh, nci, sizeof(*nci));
-}
-
-/**
- * Function : nci_save_iface1_reg
- * Description : Interface1 Descriptor is obtained from the Reg and saved in
- * Internal data structures 'nci->cores'.
- *
- * @paramter[in]
- * @desc : Descriptor of Core which needs to be updated with obatained Interface1 Descritpor.
- * @iface_desc_1 : Obatained Interface1 Descritpor.
- *
- * Return : void
- */
-static void
-BCMATTACHFN(nci_save_iface1_reg)(interface_desc_t *desc, uint32 iface_desc_1)
-{
- BCM_REFERENCE(BACKPLANE_ID_NAME);
-
- desc->coretype = GET_CORETYPE(iface_desc_1);
- desc->master = IS_MASTER(iface_desc_1);
-
- desc->iface_desc_1 = iface_desc_1;
- desc->num_addr_reg = GET_NUM_ADDR_REG(iface_desc_1);
- if (desc->master) {
- if (desc->num_addr_reg) {
- NCI_ERROR(("nci_save_iface1_reg: Master NODEPTR Addresses is not zero "
- "i.e. %d\n", GET_NUM_ADDR_REG(iface_desc_1)));
- ASSERT(0u);
- }
- } else {
- /* SLAVE 'NumAddressRegion' one less than actual slave ports, so increment by 1 */
- desc->num_addr_reg++;
- }
-
- NCI_INFO(("\tnci_save_iface1_reg: %s InterfaceDesc:%#x WordOffset=%#x "
- "NoAddrReg=%#x %s_Offset=%#x BackplaneID=%s\n",
- desc->master?"Master":"Slave", desc->iface_desc_1,
- GET_WORDOFFSET(desc->iface_desc_1),
- desc->num_addr_reg, desc->coretype?"EROM1":"OOBR",
- GET_COREOFFSET(desc->iface_desc_1),
- BACKPLANE_ID_NAME[ID_BPID(desc->iface_desc_1)]));
-}
-
-/**
- * Function : nci_save_slaveport_addr
- * Description : All Slave Port Addr of Interface Descriptor are saved.
- *
- * @paramter[in]
- * @nci : This is 'nci_info_t' data structure, where all EROM parsed Cores are saved
- * @desc : Current Interface Descriptor.
- * @erom2ptr : Pointer to Address Descriptor0.
- *
- * Return : On Success, this function returns Erom2 Ptr to Next Interface Descriptor,
- * On Failure, NULL is returned.
- */
-static uint32*
-BCMATTACHFN(nci_save_slaveport_addr)(nci_info_t *nci,
- interface_desc_t *desc, uint32 *erom2ptr)
-{
- slave_port_t *sp;
- uint32 adesc;
- uint32 sz;
- uint32 addr_idx;
-
- /* Allocate 'NumAddressRegion' of Slave Port */
- if ((desc->sp = (slave_port_t *)MALLOCZ(
- nci->osh, (sizeof(*sp) * desc->num_addr_reg))) == NULL) {
- NCI_ERROR(("\tnci_save_slaveport_addr: Memory Allocation failed for Slave Port\n"));
- return NULL;
- }
-
- sp = desc->sp;
- /* Slave Port Addrs Desc */
- for (addr_idx = 0u; addr_idx < desc->num_addr_reg; addr_idx++) {
- adesc = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- sp[addr_idx].adesc = adesc;
-
- sp[addr_idx].addrl = adesc & SLAVEPORT_BASE_ADDR_MASK;
- if (adesc & SLAVEPORT_64BIT_ADDR_MASK) {
- sp[addr_idx].addrh = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- sp[addr_idx].extaddrl = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- sp[addr_idx].extaddrh = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- NCI_INFO(("\tnci_save_slaveport_addr: SlavePortAddr[%#x]:0x%08x al=0x%08x "
- "ah=0x%08x extal=0x%08x extah=0x%08x\n", addr_idx, adesc,
- sp[addr_idx].addrl, sp[addr_idx].addrh, sp[addr_idx].extaddrl,
- sp[addr_idx].extaddrh));
- }
- else if (adesc & SLAVEPORT_BOUND_ADDR_MASK) {
- sp[addr_idx].addrh = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- NCI_INFO(("\tnci_save_slaveport_addr: SlavePortAddr[%#x]:0x%08x al=0x%08x "
- "ah=0x%08x\n", addr_idx, adesc, sp[addr_idx].addrl,
- sp[addr_idx].addrh));
- } else {
- sz = adesc & SLAVEPORT_ADDR_SIZE_MASK;
- sp[addr_idx].addrh = sp[addr_idx].addrl + ADDR_SIZE(sz);
- NCI_INFO(("\tnci_save_slaveport_addr: SlavePortAddr[%#x]:0x%08x al=0x%08x "
- "ah=0x%08x sz=0x%08x\n", addr_idx, adesc, sp[addr_idx].addrl,
- sp[addr_idx].addrh, sz));
- }
- }
-
- return erom2ptr;
-}
-
-/**
- * Function : nci_initial_parse
- * Description : This function does
- * 1. Obtains OOBR/EROM1 pointer based on CoreType
- * 2. Analysis right CoreUnit for this 'core'
- * 3. Saves CoreInfo & Interface Config in Coresponding 'core'
- *
- * @paramter[in]
- * @nci : This is 'nci_info_t' data structure, where all EROM parsed Cores are saved.
- * @erom2ptr : Pointer to Interface Descriptor0.
- * @core_idx : New core index needs to be populated in this pointer.
- *
- * Return : On Success, this function returns 'core' where CoreInfo & Interface Config are saved.
- */
-static nci_cores_t*
-BCMATTACHFN(nci_initial_parse)(nci_info_t *nci, uint32 *erom2ptr, uint32 *core_idx)
-{
- uint32 iface_desc_1;
- nci_cores_t *core;
- uint32 dmp_regs_off = 0u;
- uint32 iface_cfg = 0u;
- uint32 core_info;
- uint32 *ptr;
- uint coreid;
-
- iface_desc_1 = R_REG(nci->osh, erom2ptr);
-
- /* Get EROM1/OOBR Pointer based on CoreType */
- if (!GET_CORETYPE(iface_desc_1)) {
- if (nci->bustype == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- nci->oobr_base = (uint32*)((uintptr)nci->erom1base);
- }
-
- ptr = NCI_ADD_ADDR(nci->oobr_base, GET_COREOFFSET(iface_desc_1));
- } else {
- ptr = NCI_ADD_ADDR(nci->erom1base, GET_COREOFFSET(iface_desc_1));
- }
- dmp_regs_off = GET_COREOFFSET(iface_desc_1) + DMP_DMPCTRL_REG_OFFSET;
-
- core_info = R_REG(nci->osh, ptr);
- NCI_INC_ADDR(ptr, NCI_WORD_SIZE);
- iface_cfg = R_REG(nci->osh, ptr);
-
- *core_idx = nci->num_cores;
- core = &nci->cores[*core_idx];
-
- if (CORE_ID(core_info) < 0xFFu) {
- coreid = CORE_ID(core_info) | 0x800u;
- } else {
- coreid = CORE_ID(core_info);
- }
-
- /* Get coreunit from previous cores i.e. num_cores */
- core->coreunit = nci_get_coreunit(nci->cores, nci->num_cores,
- coreid, iface_desc_1);
-
- core->coreid = coreid;
-
- /* Increment the num_cores once proper coreunit is known */
- nci->num_cores++;
-
- NCI_INFO(("\n\nnci_initial_parse: core_idx:%d %s=%p \n",
- *core_idx, GET_CORETYPE(iface_desc_1)?"EROM1":"OOBR", ptr));
-
- /* Core Info Register */
- core->coreinfo = core_info;
-
- /* Save DMP register base address. */
- core->dmp_regs_off = dmp_regs_off;
-
- NCI_INFO(("\tnci_initial_parse: COREINFO:%#x CId:%#x CUnit=%#x CRev=%#x CMfg=%#x\n",
- core->coreinfo, core->coreid, core->coreunit, CORE_REV(core->coreinfo),
- CORE_MFG(core->coreinfo)));
-
- /* Interface Config Register */
- core->iface_cfg = iface_cfg;
- core->iface_cnt = GET_INFACECNT(iface_cfg);
-
- NCI_INFO(("\tnci_initial_parse: INTERFACE_CFG:%#x IfaceCnt=%#x IfaceOffset=%#x \n",
- iface_cfg, core->iface_cnt, iface_cfg & IC_IFACEOFFSET_MASK));
-
- /* For PCI_BUS case set back BAR0 Window to EROM1 Base */
- if (nci->bustype == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_EROM1_BASE(nci->cc_erom2base));
- }
-
- return core;
-}
-
-static uint32
-BCMATTACHFN(nci_find_numcores)(si_t *sih)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- volatile hndoobr_reg_t *oobr_reg = NULL;
- uint32 orig_bar0_win1 = 0u;
- uint32 num_oobr_cores = 0u;
- uint32 num_nonoobr_cores = 0u;
-
- /* No of Non-OOBR Cores */
- num_nonoobr_cores = NCI_NONOOBR_CORES(nci->cc_erom2base);
- if (num_nonoobr_cores <= 0u) {
- NCI_ERROR(("nci_find_numcores: Invalid Number of non-OOBR cores %d\n",
- num_nonoobr_cores));
- goto fail;
- }
-
- /* No of OOBR Cores */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- oobr_reg = (volatile hndoobr_reg_t*)REG_MAP(GET_OOBR_BASE(nci->cc_erom2base),
- SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Save Original Bar0 Win1 */
- orig_bar0_win1 = OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN,
- PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- oobr_reg = (volatile hndoobr_reg_t*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("nci_find_numcores: Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- ASSERT(0);
- goto fail;
- }
-
- num_oobr_cores = R_REG(nci->osh, &oobr_reg->capability) & OOBR_CAP_CORECNT_MASK;
- if (num_oobr_cores <= 0u) {
- NCI_ERROR(("nci_find_numcores: Invalid Number of OOBR cores %d\n", num_oobr_cores));
- goto fail;
- }
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE, orig_bar0_win1);
- }
-
- NCI_PRINT(("nci_find_numcores: Total Cores found %d\n",
- (num_oobr_cores + num_nonoobr_cores)));
- /* Total No of Cores */
- return (num_oobr_cores + num_nonoobr_cores);
-
-fail:
- return 0u;
-}
-
-/**
- * Function : nci_scan
- * Description : Function parses EROM in BOOKER NCI Architecture and saves all inforamtion about
- * Cores in 'nci_info_t' data structure.
- *
- * @paramter[in]
- * @nci : This is 'nci_info_t' data structure, where all EROM parsed Cores are saved.
- *
- * Return : On Success No of parsed Cores in EROM is returned,
- * On Failure '0' is returned by printing ERROR messages
- * in Console(If NCI_LOG_LEVEL is enabled).
- */
-uint32
-BCMATTACHFN(nci_scan)(si_t *sih)
-{
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = (nci_info_t *)sii->nci_info;
- axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
- uint32 *cur_iface_desc_1_ptr;
- nci_cores_t *core;
- interface_desc_t *desc;
- uint32 wordoffset = 0u;
- uint32 iface_desc_0;
- uint32 iface_desc_1;
- uint32 *erom2ptr;
- uint8 iface_idx;
- uint32 core_idx;
- int err = 0;
-
- /* If scan was finished already */
- if (nci->scan_done) {
- goto end;
- }
-
- erom2ptr = nci->erom2base;
- sii->axi_num_wrappers = 0;
-
- while (TRUE) {
- iface_desc_0 = R_REG(nci->osh, erom2ptr);
- if (iface_desc_0 == ID_ENDMARKER) {
- NCI_INFO(("\nnci_scan: Reached end of EROM2 with total cores=%d \n",
- nci->num_cores));
- break;
- }
-
- /* Save current Iface1 Addr for comparision */
- cur_iface_desc_1_ptr = GET_NEXT_EROM_ADDR(erom2ptr);
-
- /* Get CoreInfo, InterfaceCfg, CoreIdx */
- core = nci_initial_parse(nci, cur_iface_desc_1_ptr, &core_idx);
-
- core->desc = (interface_desc_t *)MALLOCZ(
- nci->osh, (sizeof(*(core->desc)) * core->iface_cnt));
- if (core->desc == NULL) {
- NCI_ERROR(("nci_scan: Mem Alloc failed for Iface and Addr "
- "Descriptor\n"));
- err = NCI_NOMEM;
- break;
- }
-
- for (iface_idx = 0u; iface_idx < core->iface_cnt; iface_idx++) {
- desc = &core->desc[iface_idx];
-
- iface_desc_0 = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
- iface_desc_1 = R_REG(nci->osh, erom2ptr);
- NCI_INC_ADDR(erom2ptr, NCI_WORD_SIZE);
-
- /* Interface Descriptor Register */
- nci_save_iface1_reg(desc, iface_desc_1);
- if (desc->master && desc->num_addr_reg) {
- err = NCI_MASTER_INVALID_ADDR;
- goto end;
- }
-
- wordoffset = GET_WORDOFFSET(iface_desc_1);
-
- /* NodePointer Register */
- desc->iface_desc_0 = iface_desc_0;
- desc->node_ptr = GET_NODEPTR(iface_desc_0);
- desc->node_type = GET_NODETYPE(iface_desc_0);
-
- if (axi_wrapper && (sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS)) {
- axi_wrapper[sii->axi_num_wrappers].mfg = CORE_MFG(core->coreinfo);
- axi_wrapper[sii->axi_num_wrappers].cid = CORE_ID(core->coreinfo);
- axi_wrapper[sii->axi_num_wrappers].rev = CORE_REV(core->coreinfo);
- axi_wrapper[sii->axi_num_wrappers].wrapper_type = desc->master;
- axi_wrapper[sii->axi_num_wrappers].wrapper_addr = desc->node_ptr;
- sii->axi_num_wrappers++;
- }
-
- NCI_INFO(("nci_scan: %s NodePointer:%#x Type=%s NODEPTR=%#x \n",
- desc->master?"Master":"Slave", desc->iface_desc_0,
- desc->node_type?"NIC-400":"BOOKER", desc->node_ptr));
-
- /* Slave Port Addresses */
- if (!desc->master) {
- erom2ptr = nci_save_slaveport_addr(nci, desc, erom2ptr);
- if (erom2ptr == NULL) {
- NCI_ERROR(("nci_scan: Invalid EROM2PTR\n"));
- err = NCI_INVALID_EROM2PTR;
- goto end;
- }
- }
-
- /* Current loop ends with next iface_desc_0 */
- }
-
- if (wordoffset == 0u) {
- NCI_INFO(("\nnci_scan: EROM PARSING found END 'wordoffset=%#x' "
- "with total cores=%d \n", wordoffset, nci->num_cores));
- break;
- }
- }
- nci->scan_done = TRUE;
-
-end:
- if (err) {
- NCI_ERROR(("nci_scan: Failed with Code %d\n", err));
- nci->num_cores = 0;
- ASSERT(0u);
- }
-
- return nci->num_cores;
-}
-
-/**
- * Function : nci_dump_erom
- * Description : Function dumps EROM from inforamtion cores in 'nci_info_t' data structure.
- *
- * @paramter[in]
- * @nci : This is 'nci_info_t' data structure, where all EROM parsed Cores are saved.
- *
- * Return : void
- */
-void
-BCMATTACHFN(nci_dump_erom)(void *ctx)
-{
- nci_info_t *nci = (nci_info_t *)ctx;
- nci_cores_t *core;
- interface_desc_t *desc;
- slave_port_t *sp;
- uint32 core_idx, addr_idx, iface_idx;
- uint32 core_info;
-
- BCM_REFERENCE(core_info);
-
- NCI_INFO(("\nnci_dump_erom: -- EROM Dump --\n"));
- for (core_idx = 0u; core_idx < nci->num_cores; core_idx++) {
- core = &nci->cores[core_idx];
-
- /* Core Info Register */
- core_info = core->coreinfo;
- NCI_INFO(("\nnci_dump_erom: core_idx=%d COREINFO:%#x CId:%#x CUnit:%#x CRev=%#x "
- "CMfg=%#x\n", core_idx, core_info, CORE_ID(core_info), core->coreunit,
- CORE_REV(core_info), CORE_MFG(core_info)));
-
- /* Interface Config Register */
- NCI_INFO(("nci_dump_erom: IfaceCfg=%#x IfaceCnt=%#x \n",
- core->iface_cfg, core->iface_cnt));
-
- for (iface_idx = 0u; iface_idx < core->iface_cnt; iface_idx++) {
- desc = &core->desc[iface_idx];
- /* NodePointer Register */
- NCI_INFO(("nci_dump_erom: %s iface_desc_0 Master=%#x MASTER_WRAP=%#x "
- "Type=%s \n", desc->master?"Master":"Slave", desc->iface_desc_0,
- desc->node_ptr,
- (desc->node_type)?"NIC-400":"BOOKER"));
-
- /* Interface Descriptor Register */
- NCI_INFO(("nci_dump_erom: %s InterfaceDesc:%#x WOffset=%#x NoAddrReg=%#x "
- "%s_Offset=%#x\n", desc->master?"Master":"Slave",
- desc->iface_desc_1, GET_WORDOFFSET(desc->iface_desc_1),
- desc->num_addr_reg,
- desc->coretype?"EROM1":"OOBR", GET_COREOFFSET(desc->iface_desc_1)));
-
- /* Slave Port Addresses */
- sp = desc->sp;
- if (!sp) {
- continue;
- }
- for (addr_idx = 0u; addr_idx < desc->num_addr_reg; addr_idx++) {
- if (sp[addr_idx].extaddrl) {
- NCI_INFO(("nci_dump_erom: SlavePortAddr[%#x]: AddrDesc=%#x"
- " al=%#x ah=%#x extal=%#x extah=%#x\n", addr_idx,
- sp[addr_idx].adesc, sp[addr_idx].addrl,
- sp[addr_idx].addrh, sp[addr_idx].extaddrl,
- sp[addr_idx].extaddrh));
- } else {
- NCI_INFO(("nci_dump_erom: SlavePortAddr[%#x]: AddrDesc=%#x"
- " al=%#x ah=%#x\n", addr_idx, sp[addr_idx].adesc,
- sp[addr_idx].addrl, sp[addr_idx].addrh));
- }
- }
- }
- }
-
- return;
-}
-
-/*
- * Switch to 'coreidx', issue a single arbitrary 32bit register mask & set operation,
- * switch back to the original core, and return the new value.
- */
-uint
-BCMPOSTTRAPFN(nci_corereg)(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
-{
- uint origidx = 0;
- volatile uint32 *r = NULL;
- uint w;
- bcm_int_bitmask_t intr_val;
- bool fast = FALSE;
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores_info = &nci->cores[coreidx];
-
- NCI_TRACE(("nci_corereg coreidx %u regoff %u mask %u val %u\n",
- coreidx, regoff, mask, val));
- ASSERT(GOODIDX(coreidx, nci->num_cores));
- ASSERT(regoff < SI_CORE_SIZE);
- ASSERT((val & ~mask) == 0);
-
- if (coreidx >= SI_MAXCORES) {
- return 0;
- }
-
- if (BUSTYPE(sih->bustype) == SI_BUS) {
- /* If internal bus, we can always get at everything */
- uint32 curmap = nci_get_curmap(nci, coreidx);
- BCM_REFERENCE(curmap);
-
- fast = TRUE;
- /* map if does not exist */
- if (!cores_info->regs) {
- cores_info->regs = REG_MAP(curmap, SI_CORE_SIZE);
- ASSERT(GOODREGS(cores_info->regs));
- }
- r = (volatile uint32 *)((volatile uchar *)cores_info->regs + regoff);
- } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
- /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
-
- if ((cores_info->coreid == CC_CORE_ID) && SI_FAST(sii)) {
- /* Chipc registers are mapped at 12KB */
-
- fast = TRUE;
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_CCREGS_OFFSET + regoff);
- } else if (sii->pub.buscoreidx == coreidx) {
- /* pci registers are at either in the last 2KB of an 8KB window
- * or, in pcie and pci rev 13 at 8KB
- */
- fast = TRUE;
- if (SI_FAST(sii)) {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_PCIREGS_OFFSET + regoff);
- } else {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- ((regoff >= SBCONFIGOFF) ?
- PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) + regoff);
- }
- }
- }
-
- if (!fast) {
- INTR_OFF(sii, &intr_val);
-
- /* save current core index */
- origidx = si_coreidx(&sii->pub);
-
- /* switch core */
- r = (volatile uint32*)((volatile uchar*)nci_setcoreidx(&sii->pub, coreidx) +
- regoff);
- }
- ASSERT(r != NULL);
-
- /* mask and set */
- if (mask || val) {
- w = (R_REG(sii->osh, r) & ~mask) | val;
- W_REG(sii->osh, r, w);
- }
-
- /* readback */
- w = R_REG(sii->osh, r);
-
- if (!fast) {
- /* restore core index */
- if (origidx != coreidx) {
- nci_setcoreidx(&sii->pub, origidx);
- }
- INTR_RESTORE(sii, &intr_val);
- }
-
- return (w);
-}
-
-uint
-nci_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
-{
- uint origidx = 0;
- volatile uint32 *r = NULL;
- uint w = 0;
- bcm_int_bitmask_t intr_val;
- bool fast = FALSE;
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores_info = &nci->cores[coreidx];
-
- NCI_TRACE(("nci_corereg_writeonly() coreidx %u regoff %u mask %u val %u\n",
- coreidx, regoff, mask, val));
-
- ASSERT(GOODIDX(coreidx, nci->num_cores));
- ASSERT(regoff < SI_CORE_SIZE);
- ASSERT((val & ~mask) == 0);
-
- if (coreidx >= SI_MAXCORES) {
- return 0;
- }
-
- if (BUSTYPE(sih->bustype) == SI_BUS) {
- /* If internal bus, we can always get at everything */
- uint32 curmap = nci_get_curmap(nci, coreidx);
- BCM_REFERENCE(curmap);
- fast = TRUE;
- /* map if does not exist */
- if (!cores_info->regs) {
- cores_info->regs = REG_MAP(curmap, SI_CORE_SIZE);
- ASSERT(GOODREGS(cores_info->regs));
- }
- r = (volatile uint32 *)((volatile uchar *)cores_info->regs + regoff);
- } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
- /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
-
- if ((cores_info->coreid == CC_CORE_ID) && SI_FAST(sii)) {
- /* Chipc registers are mapped at 12KB */
-
- fast = TRUE;
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_CCREGS_OFFSET + regoff);
- } else if (sii->pub.buscoreidx == coreidx) {
- /* pci registers are at either in the last 2KB of an 8KB window
- * or, in pcie and pci rev 13 at 8KB
- */
- fast = TRUE;
- if (SI_FAST(sii)) {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_PCIREGS_OFFSET + regoff);
- } else {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- ((regoff >= SBCONFIGOFF) ?
- PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) + regoff);
- }
- }
- }
-
- if (!fast) {
- INTR_OFF(sii, &intr_val);
-
- /* save current core index */
- origidx = si_coreidx(&sii->pub);
-
- /* switch core */
- r = (volatile uint32*) ((volatile uchar*) nci_setcoreidx(&sii->pub, coreidx) +
- regoff);
- }
- ASSERT(r != NULL);
-
- /* mask and set */
- if (mask || val) {
- w = (R_REG(sii->osh, r) & ~mask) | val;
- W_REG(sii->osh, r, w);
- }
-
- if (!fast) {
- /* restore core index */
- if (origidx != coreidx) {
- nci_setcoreidx(&sii->pub, origidx);
- }
-
- INTR_RESTORE(sii, &intr_val);
- }
-
- return (w);
-}
-
-/*
- * If there is no need for fiddling with interrupts or core switches (typically silicon
- * back plane registers, pci registers and chipcommon registers), this function
- * returns the register offset on this core to a mapped address. This address can
- * be used for W_REG/R_REG directly.
- *
- * For accessing registers that would need a core switch, this function will return
- * NULL.
- */
-volatile uint32 *
-nci_corereg_addr(si_t *sih, uint coreidx, uint regoff)
-{
- volatile uint32 *r = NULL;
- bool fast = FALSE;
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores_info = &nci->cores[coreidx];
-
- NCI_TRACE(("nci_corereg_addr() coreidx %u regoff %u\n", coreidx, regoff));
-
- ASSERT(GOODIDX(coreidx, nci->num_cores));
- ASSERT(regoff < SI_CORE_SIZE);
-
- if (coreidx >= SI_MAXCORES) {
- return 0;
- }
-
- if (BUSTYPE(sih->bustype) == SI_BUS) {
- uint32 curmap = nci_get_curmap(nci, coreidx);
- BCM_REFERENCE(curmap);
-
- /* If internal bus, we can always get at everything */
- fast = TRUE;
- /* map if does not exist */
- if (!cores_info->regs) {
- cores_info->regs = REG_MAP(curmap, SI_CORE_SIZE);
- ASSERT(GOODREGS(cores_info->regs));
- }
- r = (volatile uint32 *)((volatile uchar *)cores_info->regs + regoff);
-
- } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
- /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
-
- if ((cores_info->coreid == CC_CORE_ID) && SI_FAST(sii)) {
- /* Chipc registers are mapped at 12KB */
-
- fast = TRUE;
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_CCREGS_OFFSET + regoff);
- } else if (sii->pub.buscoreidx == coreidx) {
- /* pci registers are at either in the last 2KB of an 8KB window
- * or, in pcie and pci rev 13 at 8KB
- */
- fast = TRUE;
- if (SI_FAST(sii)) {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- PCI_16KB0_PCIREGS_OFFSET + regoff);
- } else {
- r = (volatile uint32 *)((volatile char *)sii->curmap +
- ((regoff >= SBCONFIGOFF) ?
- PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) + regoff);
- }
- }
- }
-
- if (!fast) {
- ASSERT(sii->curidx == coreidx);
- r = (volatile uint32*) ((volatile uchar*)sii->curmap + regoff);
- }
-
- return (r);
-}
-
-uint
-BCMPOSTTRAPFN(nci_findcoreidx)(const si_t *sih, uint coreid, uint coreunit)
-{
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- uint core_idx;
-
- NCI_TRACE(("nci_findcoreidx() coreid %u coreunit %u\n", coreid, coreunit));
-
- for (core_idx = 0; core_idx < nci->num_cores; core_idx++) {
- if ((nci->cores[core_idx].coreid == coreid) &&
- (nci->cores[core_idx].coreunit == coreunit)) {
- return core_idx;
- }
- }
- return BADIDX;
-}
-
-static uint32
-_nci_get_slave_addr_size(nci_info_t *nci, uint coreidx, uint32 slave_port_idx, uint base_idx)
-{
- uint32 size;
- uint32 add_desc;
-
- NCI_TRACE(("_nci_get_slave_addr_size() coreidx %u slave_port_idx %u base_idx %u\n",
- coreidx, slave_port_idx, base_idx));
-
- add_desc = nci->cores[coreidx].desc[slave_port_idx].sp[base_idx].adesc;
-
- size = add_desc & SLAVEPORT_ADDR_SIZE_MASK;
- return ADDR_SIZE(size);
-}
-
-static uint32
-BCMPOSTTRAPFN(_nci_get_curmap)(nci_info_t *nci, uint coreidx, uint slave_port_idx, uint base_idx)
-{
- /* TODO: Is handling of 64 bit addressing required */
- NCI_TRACE(("_nci_get_curmap coreidx %u slave_port_idx %u base_idx %u\n",
- coreidx, slave_port_idx, base_idx));
- return nci->cores[coreidx].desc[slave_port_idx].sp[base_idx].addrl;
-}
-
-/* Get the interface descriptor which is connected to APB and return its address */
-static uint32
-BCMPOSTTRAPFN(nci_get_curmap)(nci_info_t *nci, uint coreidx)
-{
- nci_cores_t *core_info = &nci->cores[coreidx];
- uint32 iface_idx;
-
- NCI_TRACE(("nci_get_curmap coreidx %u\n", coreidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curmap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
-
- /* If core is a Backplane or Bridge, then its slave port
- * will give the pointer to access registers.
- */
- if (!IS_MASTER(core_info->desc[iface_idx].iface_desc_1) &&
- (IS_BACKPLANE(core_info->coreinfo) ||
- APB_INF(core_info->desc[iface_idx]))) {
- return _nci_get_curmap(nci, coreidx, iface_idx, 0);
- }
- }
-
- /* no valid slave port address is found */
- return NCI_BAD_REG;
-}
-
-static uint32
-BCMPOSTTRAPFN(_nci_get_curwrap)(nci_info_t *nci, uint coreidx, uint wrapper_idx)
-{
- return nci->cores[coreidx].desc[wrapper_idx].node_ptr;
-}
-
-static uint32
-BCMPOSTTRAPFN(nci_get_curwrap)(nci_info_t *nci, uint coreidx)
-{
- nci_cores_t *core_info = &nci->cores[coreidx];
- uint32 iface_idx;
- NCI_TRACE(("nci_get_curwrap coreidx %u\n", coreidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curwrap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
- if ((ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_BOOKER) ||
- (ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_NIC400)) {
- return _nci_get_curwrap(nci, coreidx, iface_idx);
- }
- }
-
- /* no valid master wrapper found */
- return NCI_BAD_REG;
-}
-
-static void
-_nci_setcoreidx_pcie_bus(si_t *sih, volatile void **regs, uint32 curmap,
- uint32 curwrap)
-{
- si_info_t *sii = SI_INFO(sih);
-
- *regs = sii->curmap;
- switch (sii->slice) {
- case 0: /* main/first slice */
- /* point bar0 window */
- OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, PCIE_WRITE_SIZE, curmap);
- // TODO: why curwrap is zero i.e no master wrapper
- if (curwrap != 0) {
- if (PCIE_GEN2(sii)) {
- OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2,
- PCIE_WRITE_SIZE, curwrap);
- } else {
- OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2,
- PCIE_WRITE_SIZE, curwrap);
- }
- }
- break;
- case 1: /* aux/second slice */
- /* PCIE GEN2 only for other slices */
- if (!PCIE_GEN2(sii)) {
- /* other slices not supported */
- NCI_ERROR(("pci gen not supported for slice 1\n"));
- ASSERT(0);
- break;
- }
-
- /* 0x4000 - 0x4fff: enum space 0x5000 - 0x5fff: wrapper space */
-
- *regs = (volatile uint8 *)*regs + PCI_SEC_BAR0_WIN_OFFSET;
- sii->curwrap = (void *)((uintptr)*regs + SI_CORE_SIZE);
-
- /* point bar0 window */
- OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, PCIE_WRITE_SIZE, curmap);
- OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN2, PCIE_WRITE_SIZE, curwrap);
- break;
-
- case 2: /* scan/third slice */
- /* PCIE GEN2 only for other slices */
- if (!PCIE_GEN2(sii)) {
- /* other slices not supported */
- NCI_ERROR(("pci gen not supported for slice 1\n"));
- ASSERT(0);
- break;
- }
- /* 0x9000 - 0x9fff: enum space 0xa000 - 0xafff: wrapper space */
- *regs = (volatile uint8 *)*regs + PCI_SEC_BAR0_WIN_OFFSET;
- sii->curwrap = (void *)((uintptr)*regs + SI_CORE_SIZE);
-
- /* point bar0 window */
- nci_corereg(sih, sih->buscoreidx, PCIE_TER_BAR0_WIN, ~0, curmap);
- nci_corereg(sih, sih->buscoreidx, PCIE_TER_BAR0_WRAPPER, ~0, curwrap);
- break;
- default:
- ASSERT(0);
- break;
- }
-}
-
-static volatile void *
-BCMPOSTTRAPFN(_nci_setcoreidx)(si_t *sih, uint coreidx)
-{
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores_info = &nci->cores[coreidx];
- uint32 curmap, curwrap;
- volatile void *regs = NULL;
-
- NCI_TRACE(("_nci_setcoreidx coreidx %u\n", coreidx));
- if (!GOODIDX(coreidx, nci->num_cores)) {
- return (NULL);
- }
- /*
- * If the user has provided an interrupt mask enabled function,
- * then assert interrupts are disabled before switching the core.
- */
- ASSERT((sii->intrsenabled_fn == NULL) ||
- !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
-
- curmap = nci_get_curmap(nci, coreidx);
- curwrap = nci_get_curwrap(nci, coreidx);
-
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- /* map if does not exist */
- if (!cores_info->regs) {
- cores_info->regs = REG_MAP(curmap, SI_CORE_SIZE);
- ASSERT(GOODREGS(cores_info->regs));
- }
- sii->curmap = regs = cores_info->regs;
- sii->curwrap = REG_MAP(curwrap, SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- _nci_setcoreidx_pcie_bus(sih, ®s, curmap, curwrap);
- break;
-
- default:
- NCI_ERROR(("_nci_stcoreidx Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- break;
- }
- sii->curidx = coreidx;
- return regs;
-}
-
-volatile void *
-BCMPOSTTRAPFN(nci_setcoreidx)(si_t *sih, uint coreidx)
-{
- return _nci_setcoreidx(sih, coreidx);
-}
-
-volatile void *
-BCMPOSTTRAPFN(nci_setcore)(si_t *sih, uint coreid, uint coreunit)
-{
- si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- uint core_idx;
-
- NCI_TRACE(("nci_setcore coreidx %u coreunit %u\n", coreid, coreunit));
- core_idx = nci_findcoreidx(sih, coreid, coreunit);
-
- if (!GOODIDX(core_idx, nci->num_cores)) {
- return (NULL);
- }
- return nci_setcoreidx(sih, core_idx);
-}
-
-/* Get the value of the register at offset "offset" of currently configured core */
-uint
-BCMPOSTTRAPFN(nci_get_wrap_reg)(const si_t *sih, uint32 offset, uint32 mask, uint32 val)
-{
- const si_info_t *sii = SI_INFO(sih);
- uint32 *addr = (uint32 *) ((uchar *)(sii->curwrap) + offset);
- NCI_TRACE(("nci_wrap_reg offset %u mask %u val %u\n", offset, mask, val));
-
- if (mask || val) {
- uint32 w = R_REG(sii->osh, addr);
- w &= ~mask;
- w |= val;
- W_REG(sii->osh, addr, w);
- }
- return (R_REG(sii->osh, addr));
-}
-
-uint
-nci_corevendor(const si_t *sih)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
-
- NCI_TRACE(("nci_corevendor coreidx %u\n", sii->curidx));
- return (nci->cores[sii->curidx].coreinfo & COREINFO_MFG_MASK) >> COREINFO_MFG_SHIFT;
-}
-
-uint
-BCMPOSTTRAPFN(nci_corerev)(const si_t *sih)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- uint coreidx = sii->curidx;
-
- NCI_TRACE(("nci_corerev coreidx %u\n", coreidx));
-
- return (nci->cores[coreidx].coreinfo & COREINFO_REV_MASK) >> COREINFO_REV_SHIFT;
-}
-
-uint
-nci_corerev_minor(const si_t *sih)
-{
- return (nci_core_sflags(sih, 0, 0) >> SISF_MINORREV_D11_SHIFT) &
- SISF_MINORREV_D11_MASK;
-}
-
-uint
-BCMPOSTTRAPFN(nci_coreid)(const si_t *sih, uint coreidx)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
-
- NCI_TRACE(("nci_coreid coreidx %u\n", coreidx));
- return nci->cores[coreidx].coreid;
-}
-
-/** return total coreunit of coreid or zero if not found */
-uint
-BCMPOSTTRAPFN(nci_numcoreunits)(const si_t *sih, uint coreid)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- uint found = 0;
- uint i;
-
- NCI_TRACE(("nci_numcoreunits coreidx %u\n", coreid));
-
- for (i = 0; i < nci->num_cores; i++) {
- if (nci->cores[i].coreid == coreid) {
- found++;
- }
- }
-
- return found;
-}
-
-/* Return the address of the nth address space in the current core
- * Arguments:
- * sih : Pointer to struct si_t
- * spidx : slave port index
- * baidx : base address index
- */
-uint32
-nci_addr_space(const si_t *sih, uint spidx, uint baidx)
-{
- const si_info_t *sii = SI_INFO(sih);
- uint cidx;
-
- NCI_TRACE(("nci_addr_space spidx %u baidx %u\n", spidx, baidx));
- cidx = sii->curidx;
- return _nci_get_curmap(sii->nci_info, cidx, spidx, baidx);
-}
-
-/* Return the size of the nth address space in the current core
-* Arguments:
-* sih : Pointer to struct si_t
-* spidx : slave port index
-* baidx : base address index
-*/
-uint32
-nci_addr_space_size(const si_t *sih, uint spidx, uint baidx)
-{
- const si_info_t *sii = SI_INFO(sih);
- uint cidx;
-
- NCI_TRACE(("nci_addr_space_size spidx %u baidx %u\n", spidx, baidx));
-
- cidx = sii->curidx;
- return _nci_get_slave_addr_size(sii->nci_info, cidx, spidx, baidx);
-}
-
-/*
- * Performs soft reset of attached device.
- * Writes have the following effect:
- * 0b1 Request attached device to enter reset.
- * Write is ignored if it occurs before soft reset exit has occurred.
- *
- * 0b0 Request attached device to exit reset.
- * Write is ignored if it occurs before soft reset entry has occurred.
- *
- * Software can poll this register to determine whether soft reset entry or exit has occurred,
- * using the following values:
- * 0b1 Indicates that the device is in reset.
- * 0b0 Indicates that the device is not in reset.
- *
- *
- * Note
- * The register value updates to reflect a request for reset entry or reset exit,
- * but the update can only occur after required internal conditions are met.
- * Until these conditions are met, a read to the register returns the old value.
- * For example, outstanding transactions currently being handled must complete before
- * the register value updates.
- *
- * To ensure reset propagation within the device,
- * it is the responsibility of software to allow enough cycles after
- * soft reset assertion is reflected in the reset control register
- * before exiting soft reset by triggering a write of 0b0.
- * If this responsibility is not met, the behavior is undefined or unpredictable.
- *
- * When the register value is 0b1,
- * the external soft reset pin that connects to the attached AXI master or slave
- * device is asserted, using the correct polarity of the reset pin.
- * When the register value is 0b0, the external softreset
- * pin that connects to the attached AXI master or slave device is deasserted,
- * using the correct polarity of the reset pin.
- */
-static void
-BCMPOSTTRAPFN(_nci_core_reset)(const si_t *sih, uint32 bits, uint32 resetbits)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- amni_regs_t *amni = (amni_regs_t *)(uintptr)sii->curwrap;
- volatile dmp_regs_t *io;
- volatile uint32* erom_base = 0u;
- uint32 orig_bar0_win1 = 0u;
- volatile uint32 dummy;
- volatile uint32 reg_read;
- uint32 dmp_write_value;
-
- /* Point to OOBR base */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- erom_base = (volatile uint32*)REG_MAP(GET_OOBR_BASE(nci->cc_erom2base),
- SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /*
- * Save Original Bar0 Win1. In nci, the io registers dmpctrl & dmpstatus
- * registers are implemented in the EROM section. REF -
- * https://docs.google.com/document/d/1HE7hAmvdoNFSnMI7MKQV1qVrFBZVsgLdNcILNOA2C8c
- * This requires addition BAR0 windows mapping to erom section in chipcommon.
- */
- orig_bar0_win1 = OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN,
- PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- erom_base = (volatile uint32*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("_nci_core_reset Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- break;
- }
-
- /* Point to DMP Control */
- io = (dmp_regs_t*)(NCI_ADD_ADDR(erom_base, nci->cores[sii->curidx].dmp_regs_off));
-
- NCI_TRACE(("_nci_core_reset reg 0x%p io %p\n", amni, io));
-
- /* Put core into reset */
- W_REG(nci->osh, &amni->idm_reset_ctrl, NI_IDM_RESET_ENTRY);
-
- /* poll for the reset to happen */
- while (TRUE) {
- /* Wait until reset is effective */
- SPINWAIT(((reg_read = R_REG(nci->osh, &amni->idm_reset_ctrl)) !=
- NI_IDM_RESET_ENTRY), NCI_SPINWAIT_TIMEOUT);
-
- if (reg_read == NI_IDM_RESET_ENTRY) {
- break;
- }
- }
-
- dmp_write_value = (bits | resetbits | SICF_FGC | SICF_CLOCK_EN);
-
- W_REG(nci->osh, &io->dmpctrl, dmp_write_value);
-
- /* poll for the dmp_reg write to happen */
- while (TRUE) {
- /* Wait until reset is effective */
- SPINWAIT(((reg_read = R_REG(nci->osh, &io->dmpctrl)) !=
- dmp_write_value), NCI_SPINWAIT_TIMEOUT);
- if (reg_read == dmp_write_value) {
- break;
- }
- }
-
- /* take core out of reset */
- W_REG(nci->osh, &amni->idm_reset_ctrl, 0u);
-
- /* poll for the core to come out of reset */
- while (TRUE) {
- /* Wait until reset is effected */
- SPINWAIT(((reg_read = R_REG(nci->osh, &amni->idm_reset_ctrl)) !=
- NI_IDM_RESET_EXIT), NCI_SPINWAIT_TIMEOUT);
- if (reg_read == NI_IDM_RESET_EXIT) {
- break;
- }
- }
-
- dmp_write_value = (bits | SICF_CLOCK_EN);
- W_REG(nci->osh, &io->dmpctrl, (bits | SICF_CLOCK_EN));
- /* poll for the core to come out of reset */
- while (TRUE) {
- SPINWAIT(((reg_read = R_REG(nci->osh, &io->dmpctrl)) !=
- dmp_write_value), NCI_SPINWAIT_TIMEOUT);
- if (reg_read == dmp_write_value) {
- break;
- }
- }
-
- dummy = R_REG(nci->osh, &io->dmpctrl);
- BCM_REFERENCE(dummy);
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE, orig_bar0_win1);
- }
-}
-
-/* reset and re-enable a core
- */
-void
-BCMPOSTTRAPFN(nci_core_reset)(const si_t *sih, uint32 bits, uint32 resetbits)
-{
- const si_info_t *sii = SI_INFO(sih);
- int32 iface_idx = 0u;
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *core = &nci->cores[sii->curidx];
-
- /* If Wrapper is of NIC400, then call AI functionality */
- for (iface_idx = core->iface_cnt-1; iface_idx >= 0; iface_idx--) {
- if (!(BOOKER_INF(core->desc[iface_idx]) || NIC_INF(core->desc[iface_idx]))) {
- continue;
- }
-#ifdef BOOKER_NIC400_INF
- if (core->desc[iface_idx].node_type == NODE_TYPE_NIC400) {
- ai_core_reset_ext(sih, bits, resetbits);
- } else
-#endif /* BOOKER_NIC400_INF */
- {
- _nci_core_reset(sih, bits, resetbits);
- }
- }
-}
-
-#ifdef BOOKER_NIC400_INF
-static int32
-BCMPOSTTRAPFN(nci_find_first_wrapper_idx)(nci_info_t *nci, uint32 coreidx)
-{
- nci_cores_t *core_info = &nci->cores[coreidx];
- uint32 iface_idx;
-
- NCI_TRACE(("nci_find_first_wrapper_idx %u\n", coreidx));
-
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_INFO(("nci_find_first_wrapper_idx: %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
-
- if ((ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_BOOKER) ||
- (ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_NIC400)) {
- return iface_idx;
- }
- }
-
- /* no valid master wrapper found */
- return NCI_BAD_INDEX;
-}
-#endif /* BOOKER_NIC400_INF */
-
-void
-nci_core_disable(const si_t *sih, uint32 bits)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- uint32 reg_read;
- volatile dmp_regs_t *io = NULL;
- uint32 orig_bar0_win1 = 0u;
- uint32 dmp_write_value;
- amni_regs_t *amni = (amni_regs_t *)(uintptr)sii->curwrap;
- nci_cores_t *core = &nci->cores[sii->curidx];
- int32 iface_idx;
-
- NCI_TRACE(("nci_core_disable\n"));
-
- BCM_REFERENCE(core);
- BCM_REFERENCE(iface_idx);
-
-#ifdef BOOKER_NIC400_INF
- iface_idx = nci_find_first_wrapper_idx(nci, sii->curidx);
-
- if (iface_idx < 0) {
- NCI_ERROR(("nci_core_disable: First Wrapper is not found\n"));
- ASSERT(0u);
- return;
- }
-
- /* If Wrapper is of NIC400, then call AI functionality */
- if (core->desc[iface_idx].master && (core->desc[iface_idx].node_type == NODE_TYPE_NIC400)) {
- return ai_core_disable(sih, bits);
- }
-#endif /* BOOKER_NIC400_INF */
-
- ASSERT(GOODREGS(sii->curwrap));
- reg_read = R_REG(nci->osh, &amni->idm_reset_ctrl);
-
- /* if core is already in reset, just return */
- if (reg_read == NI_IDM_RESET_ENTRY) {
- return;
- }
-
- /* Put core into reset */
- W_REG(nci->osh, &amni->idm_reset_ctrl, NI_IDM_RESET_ENTRY);
- while (TRUE) {
- /* Wait until reset is effected */
- SPINWAIT(((reg_read = R_REG(nci->osh, &amni->idm_reset_ctrl)) !=
- NI_IDM_RESET_ENTRY), NCI_SPINWAIT_TIMEOUT);
- if (reg_read == NI_IDM_RESET_ENTRY) {
- break;
- }
- }
-
- /* Point to OOBR base */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- io = (volatile dmp_regs_t*)
- REG_MAP(GET_OOBR_BASE(nci->cc_erom2base), SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Save Original Bar0 Win1 */
- orig_bar0_win1 =
- OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- io = (volatile dmp_regs_t*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("nci_core_disable Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- break;
-
- }
-
- /* Point to DMP Control */
- io = (dmp_regs_t*)(NCI_ADD_ADDR(io, nci->cores[sii->curidx].dmp_regs_off));
-
- dmp_write_value = (bits | SICF_FGC | SICF_CLOCK_EN);
- W_REG(nci->osh, &io->dmpctrl, dmp_write_value);
-
- /* poll for the dmp_reg write to happen */
- while (TRUE) {
- /* Wait until reset is effected */
- SPINWAIT(((reg_read = R_REG(nci->osh, &io->dmpctrl)) != dmp_write_value),
- NCI_SPINWAIT_TIMEOUT);
- if (reg_read == dmp_write_value) {
- break;
- }
- }
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE, orig_bar0_win1);
- }
-}
-
-bool
-BCMPOSTTRAPFN(nci_iscoreup)(const si_t *sih)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- amni_regs_t *ni = (amni_regs_t *)(uintptr)sii->curwrap;
- uint32 reset_ctrl;
-
-#ifdef BOOKER_NIC400_INF
- nci_cores_t *core = &nci->cores[sii->curidx];
- int32 iface_idx = nci_find_first_wrapper_idx(nci, sii->curidx);
-
- if (iface_idx < 0) {
- NCI_ERROR(("nci_iscoreup: First Wrapper is not found\n"));
- ASSERT(0u);
- return FALSE;
- }
-
- /* If Wrapper is of NIC400, then call AI functionality */
- if (core->desc[iface_idx].master && (core->desc[iface_idx].node_type == NODE_TYPE_NIC400)) {
- return ai_iscoreup(sih);
- }
-#endif /* BOOKER_NIC400_INF */
-
- NCI_TRACE(("nci_iscoreup\n"));
- reset_ctrl = R_REG(nci->osh, &ni->idm_reset_ctrl);
-
- return (reset_ctrl == NI_IDM_RESET_ENTRY) ? FALSE : TRUE;
-}
-
-/* TODO: OOB Router core is not available. Can be removed. */
-uint
-nci_intflag(si_t *sih)
-{
- return 0;
-}
-
-uint
-nci_flag(si_t *sih)
-{
- /* TODO: will be implemented if required for NCI */
- return 0;
-}
-
-uint
-nci_flag_alt(const si_t *sih)
-{
- /* TODO: will be implemented if required for NCI */
- return 0;
-}
-
-void
-BCMATTACHFN(nci_setint)(const si_t *sih, int siflag)
-{
- BCM_REFERENCE(sih);
- BCM_REFERENCE(siflag);
-
- /* TODO: Figure out how to set interrupt mask in nci */
-}
-
-/* TODO: OOB Router core is not available. Can we remove or need an alternate implementation. */
-uint32
-nci_oobr_baseaddr(const si_t *sih, bool second)
-{
- return 0;
-}
-
-uint
-nci_coreunit(const si_t *sih)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores = nci->cores;
- uint idx;
- uint coreid;
- uint coreunit;
- uint i;
-
- coreunit = 0;
-
- idx = sii->curidx;
-
- ASSERT(GOODREGS(sii->curmap));
- coreid = nci_coreid(sih, sii->curidx);
-
- /* count the cores of our type */
- for (i = 0; i < idx; i++) {
- if (cores[i].coreid == coreid) {
- coreunit++;
- }
- }
-
- return (coreunit);
-}
-
-uint
-nci_corelist(const si_t *sih, uint coreid[])
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *cores = nci->cores;
- uint32 i;
-
- for (i = 0; i < sii->numcores; i++) {
- coreid[i] = cores[i].coreid;
- }
-
- return (sii->numcores);
-}
-
-/* Return the number of address spaces in current core */
-int
-BCMATTACHFN(nci_numaddrspaces)(const si_t *sih)
-{
- /* TODO: Either save it or parse the EROM on demand, currently hardcode 2 */
- BCM_REFERENCE(sih);
-
- return 2;
-}
-
-/* The value of wrap_pos should be greater than 0 */
-/* wrapba, wrapba2 and wrapba3 */
-uint32
-nci_get_nth_wrapper(const si_t *sih, int32 wrap_pos)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = &nci->cores[sii->curidx];
- uint32 iface_idx;
- uint32 addr = 0;
-
- ASSERT(wrap_pos >= 0);
- if (wrap_pos < 0) {
- return addr;
- }
-
- NCI_TRACE(("nci_get_curmap coreidx %u\n", sii->curidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curmap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
- /* hack for core idx 8, coreidx without APB Backplane ID */
- if (!IS_MASTER(core_info->desc[iface_idx].iface_desc_1)) {
- continue;
- }
- /* TODO: Should the interface be only BOOKER or NIC is also fine. */
- if (GET_NODETYPE(core_info->desc[iface_idx].iface_desc_0) != NODE_TYPE_BOOKER) {
- continue;
- }
- /* Iterate till we do not get a wrapper at nth (wrap_pos) position */
- if (wrap_pos == 0) {
- break;
- }
- wrap_pos--;
- }
- if (iface_idx < core_info->iface_cnt) {
- addr = GET_NODEPTR(core_info->desc[iface_idx].iface_desc_0);
- }
- return addr;
-}
-
-/* Get slave port address of the 0th slave (csp2ba) */
-uint32
-nci_get_axi_addr(const si_t *sih, uint32 *size)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = (const nci_cores_t *)&nci->cores[sii->curidx];
- uint32 iface_idx;
- uint32 addr = 0;
-
- NCI_TRACE(("nci_get_curmap coreidx %u\n", sii->curidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curmap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
- if (IS_MASTER(core_info->desc[iface_idx].iface_desc_1)) {
- continue;
- }
- if ((ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_BOOKER) ||
- (ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_NIC400)) {
- break;
- }
- }
- if (iface_idx < core_info->iface_cnt) {
- /*
- * TODO: Is there any case where we need to return the slave port address
- * corresponding to index other than 0.
- */
- if (&core_info->desc[iface_idx].sp[0] != NULL) {
- addr = core_info->desc[iface_idx].sp[0].addrl;
- if (size) {
- uint32 adesc = core_info->desc[iface_idx].sp[0].adesc;
- *size = SLAVEPORT_ADDR_SIZE(adesc);
- }
- }
- }
- return addr;
-}
-
-/* spidx shouldbe the index of the slave port which we are expecting.
- * The value will vary from 0 to num_addr_reg.
- */
-/* coresba and coresba2 */
-uint32
-nci_get_core_baaddr(const si_t *sih, uint32 *size, int32 baidx)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = (const nci_cores_t *)&nci->cores[sii->curidx];
- uint32 iface_idx;
- uint32 addr = 0;
-
- NCI_TRACE(("nci_get_curmap coreidx %u\n", sii->curidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curmap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
- /* hack for core idx 8, coreidx without APB Backplane ID */
- if (IS_MASTER(core_info->desc[iface_idx].iface_desc_1)) {
- continue;
- }
- if ((ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_APB1) ||
- (ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_APB2)) {
- break;
- }
- }
- if (iface_idx < core_info->iface_cnt) {
- /*
- * TODO: Is there any case where we need to return the slave port address
- * corresponding to index other than 0.
- */
- if ((core_info->desc[iface_idx].num_addr_reg > baidx) &&
- (&core_info->desc[iface_idx].sp[baidx] != NULL)) {
- addr = core_info->desc[iface_idx].sp[baidx].addrl;
- if (size) {
- uint32 adesc = core_info->desc[iface_idx].sp[0].adesc;
- *size = SLAVEPORT_ADDR_SIZE(adesc);
- }
- }
- }
- return addr;
-}
-
-uint32
-nci_addrspace(const si_t *sih, uint spidx, uint baidx)
-{
- if (spidx == CORE_SLAVE_PORT_0) {
- if (baidx == CORE_BASE_ADDR_0) {
- return nci_get_core_baaddr(sih, NULL, CORE_BASE_ADDR_0);
- } else if (baidx == CORE_BASE_ADDR_1) {
- return nci_get_core_baaddr(sih, NULL, CORE_BASE_ADDR_1);
- }
- } else if (spidx == CORE_SLAVE_PORT_1) {
- if (baidx == CORE_BASE_ADDR_0) {
- return nci_get_axi_addr(sih, NULL);
- }
- }
-
- SI_ERROR(("nci_addrspace: Need to parse the erom again to find %d base addr"
- " in %d slave port\n", baidx, spidx));
-
- return 0;
-}
-
-uint32
-BCMATTACHFN(nci_addrspacesize)(const si_t *sih, uint spidx, uint baidx)
-{
- uint32 size = 0;
-
- if (spidx == CORE_SLAVE_PORT_0) {
- if (baidx == CORE_BASE_ADDR_0) {
- nci_get_core_baaddr(sih, &size, CORE_BASE_ADDR_0);
- goto done;
- } else if (baidx == CORE_BASE_ADDR_1) {
- nci_get_core_baaddr(sih, &size, CORE_BASE_ADDR_1);
- goto done;
- }
- } else if (spidx == CORE_SLAVE_PORT_1) {
- if (baidx == CORE_BASE_ADDR_0) {
- nci_get_axi_addr(sih, &size);
- goto done;
- }
- }
-
- SI_ERROR(("nci_addrspacesize: Need to parse the erom again to find %d"
- " base addr in %d slave port\n", baidx, spidx));
-done:
- return size;
-}
-
-uint32
-BCMPOSTTRAPFN(nci_core_cflags)(const si_t *sih, uint32 mask, uint32 val)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *core = &nci->cores[sii->curidx];
- uint32 orig_bar0_win1 = 0;
- int32 iface_idx;
- uint32 w;
-
- BCM_REFERENCE(iface_idx);
-
- if ((core[sii->curidx].coreid) == PMU_CORE_ID) {
- NCI_ERROR(("nci_core_cflags: Accessing PMU DMP register (ioctrl)\n"));
- return 0;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
- ASSERT((val & ~mask) == 0);
-
-#ifdef BOOKER_NIC400_INF
- iface_idx = nci_find_first_wrapper_idx(nci, sii->curidx);
- if (iface_idx < 0) {
- NCI_ERROR(("nci_core_cflags: First Wrapper is not found\n"));
- ASSERT(0u);
- return 0u;
- }
-
- /* If Wrapper is of NIC400, then call AI functionality */
- if (core->desc[iface_idx].master && (core->desc[iface_idx].node_type == NODE_TYPE_NIC400)) {
- aidmp_t *ai = sii->curwrap;
-
- if (mask || val) {
- w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
- W_REG(sii->osh, &ai->ioctrl, w);
- }
- return R_REG(sii->osh, &ai->ioctrl);
- } else
-#endif /* BOOKER_NIC400_INF */
- {
- volatile dmp_regs_t *io = sii->curwrap;
- volatile uint32 reg_read;
-
- /* BOOKER */
- /* Point to OOBR base */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- io = (volatile dmp_regs_t*)
- REG_MAP(GET_OOBR_BASE(nci->cc_erom2base), SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Save Original Bar0 Win1 */
- orig_bar0_win1 =
- OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- io = (volatile dmp_regs_t*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("nci_core_cflags Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- break;
-
- }
-
- /* Point to DMP Control */
- io = (dmp_regs_t*)(NCI_ADD_ADDR(io, nci->cores[sii->curidx].dmp_regs_off));
-
- if (mask || val) {
- w = ((R_REG(sii->osh, &io->dmpctrl) & ~mask) | val);
- W_REG(sii->osh, &io->dmpctrl, w);
- }
-
- reg_read = R_REG(sii->osh, &io->dmpctrl);
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN,
- PCI_ACCESS_SIZE, orig_bar0_win1);
- }
-
- return reg_read;
- }
-}
-
-void
-BCMPOSTTRAPFN(nci_core_cflags_wo)(const si_t *sih, uint32 mask, uint32 val)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *core = &nci->cores[sii->curidx];
- volatile dmp_regs_t *io = sii->curwrap;
- uint32 orig_bar0_win1 = 0;
- int32 iface_idx;
- uint32 w;
-
- BCM_REFERENCE(iface_idx);
-
- if ((core[sii->curidx].coreid) == PMU_CORE_ID) {
- NCI_ERROR(("nci_core_cflags: Accessing PMU DMP register (ioctrl)\n"));
- return;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
- ASSERT((val & ~mask) == 0);
-
-#ifdef BOOKER_NIC400_INF
- iface_idx = nci_find_first_wrapper_idx(nci, sii->curidx);
- if (iface_idx < 0) {
- NCI_ERROR(("nci_core_cflags_wo: First Wrapper is not found\n"));
- ASSERT(0u);
- return;
- }
-
- /* If Wrapper is of NIC400, then call AI functionality */
- if (core->desc[iface_idx].master && (core->desc[iface_idx].node_type == NODE_TYPE_NIC400)) {
- aidmp_t *ai = sii->curwrap;
- if (mask || val) {
- w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
- W_REG(sii->osh, &ai->ioctrl, w);
- }
- } else
-#endif /* BOOKER_NIC400_INF */
- {
- /* BOOKER */
- /* Point to OOBR base */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- io = (volatile dmp_regs_t*)
- REG_MAP(GET_OOBR_BASE(nci->cc_erom2base), SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Save Original Bar0 Win1 */
- orig_bar0_win1 =
- OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- io = (volatile dmp_regs_t*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("nci_core_cflags_wo Invalid bustype %d\n",
- BUSTYPE(sih->bustype)));
- break;
- }
-
- /* Point to DMP Control */
- io = (dmp_regs_t*)(NCI_ADD_ADDR(io, nci->cores[sii->curidx].dmp_regs_off));
-
- if (mask || val) {
- w = ((R_REG(sii->osh, &io->dmpctrl) & ~mask) | val);
- W_REG(sii->osh, &io->dmpctrl, w);
- }
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN,
- PCI_ACCESS_SIZE, orig_bar0_win1);
- }
- }
-}
-
-uint32
-nci_core_sflags(const si_t *sih, uint32 mask, uint32 val)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- nci_cores_t *core = &nci->cores[sii->curidx];
- uint32 orig_bar0_win1 = 0;
- int32 iface_idx;
- uint32 w;
-
- BCM_REFERENCE(iface_idx);
-
- if ((core[sii->curidx].coreid) == PMU_CORE_ID) {
- NCI_ERROR(("nci_core_sflags: Accessing PMU DMP register (ioctrl)\n"));
- return 0;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
-
- ASSERT((val & ~mask) == 0);
- ASSERT((mask & ~SISF_CORE_BITS) == 0);
-
-#ifdef BOOKER_NIC400_INF
- iface_idx = nci_find_first_wrapper_idx(nci, sii->curidx);
- if (iface_idx < 0) {
- NCI_ERROR(("nci_core_sflags: First Wrapper is not found\n"));
- ASSERT(0u);
- return 0u;
- }
-
- /* If Wrapper is of NIC400, then call AI functionality */
- if (core->desc[iface_idx].master && (core->desc[iface_idx].node_type == NODE_TYPE_NIC400)) {
- aidmp_t *ai = sii->curwrap;
- if (mask || val) {
- w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
- W_REG(sii->osh, &ai->iostatus, w);
- }
-
- return R_REG(sii->osh, &ai->iostatus);
- } else
-#endif /* BOOKER_NIC400_INF */
- {
- volatile dmp_regs_t *io = sii->curwrap;
- volatile uint32 reg_read;
-
- /* BOOKER */
- /* Point to OOBR base */
- switch (BUSTYPE(sih->bustype)) {
- case SI_BUS:
- io = (volatile dmp_regs_t*)
- REG_MAP(GET_OOBR_BASE(nci->cc_erom2base), SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Save Original Bar0 Win1 */
- orig_bar0_win1 =
- OSL_PCI_READ_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE);
-
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN, PCI_ACCESS_SIZE,
- GET_OOBR_BASE(nci->cc_erom2base));
- io = (volatile dmp_regs_t*)sii->curmap;
- break;
-
- default:
- NCI_ERROR(("nci_core_sflags Invalid bustype %d\n", BUSTYPE(sih->bustype)));
- return 0u;
- }
-
- /* Point to DMP Control */
- io = (dmp_regs_t*)(NCI_ADD_ADDR(io, nci->cores[sii->curidx].dmp_regs_off));
-
- if (mask || val) {
- w = ((R_REG(sii->osh, &io->dmpstatus) & ~mask) | val);
- W_REG(sii->osh, &io->dmpstatus, w);
- }
-
- reg_read = R_REG(sii->osh, &io->dmpstatus);
-
- /* Point back to original base */
- if (BUSTYPE(sih->bustype) == PCI_BUS) {
- OSL_PCI_WRITE_CONFIG(nci->osh, PCI_BAR0_WIN,
- PCI_ACCESS_SIZE, orig_bar0_win1);
- }
-
- return reg_read;
- }
-}
-
-/* TODO: Used only by host */
-int
-nci_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read)
-{
- return 0;
-}
-
-int
-nci_backplane_access_64(si_t *sih, uint addr, uint size, uint64 *val, bool read)
-{
- return 0;
-}
-
-uint
-nci_num_slaveports(const si_t *sih, uint coreidx)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = (const nci_cores_t *)&nci->cores[coreidx];
- uint32 iface_idx;
- uint32 numports = 0;
-
- NCI_TRACE(("nci_get_curmap coreidx %u\n", coreidx));
- for (iface_idx = 0; iface_idx < core_info->iface_cnt; iface_idx++) {
- NCI_TRACE(("nci_get_curmap iface_idx %u BP_ID %u master %u\n",
- iface_idx, ID_BPID(core_info->desc[iface_idx].iface_desc_1),
- IS_MASTER(core_info->desc[iface_idx].iface_desc_1)));
- /* hack for core idx 8, coreidx without APB Backplane ID */
- if (IS_MASTER(core_info->desc[iface_idx].iface_desc_1)) {
- continue;
- }
- if ((ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_APB1) ||
- (ID_BPID(core_info->desc[iface_idx].iface_desc_1) == BP_APB2)) {
- break;
- }
- }
- if (iface_idx < core_info->iface_cnt) {
- numports = core_info->desc[iface_idx].num_addr_reg;
- }
- return numports;
-}
-
-#if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_PHYDUMP)
-void
-nci_dumpregs(const si_t *sih, struct bcmstrbuf *b)
-{
- const si_info_t *sii = SI_INFO(sih);
-
- bcm_bprintf(b, "ChipNum:%x, ChipRev;%x, BusType:%x, BoardType:%x, BoardVendor:%x\n\n",
- sih->chip, sih->chiprev, sih->bustype, sih->boardtype, sih->boardvendor);
- BCM_REFERENCE(sii);
- /* TODO: Implement dump regs for nci. */
-}
-#endif /* BCMDBG || BCMDBG_DUMP || BCMDBG_PHYDUMP */
-
-#ifdef BCMDBG
-static void
-_nci_view(osl_t *osh, aidmp_t *ai, uint32 cid, uint32 addr, bool verbose)
-{
- /* TODO: This is WIP and will be developed once the
- * implementation is done based on the NCI.
- */
-}
-
-void
-nci_view(si_t *sih, bool verbose)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = (const nci_cores_t *)nci->cores;
- osl_t *osh;
- /* TODO: We need to do the structure mapping correctly based on the BOOKER/NIC type */
- aidmp_t *ai;
- uint32 cid, addr;
-
- ai = sii->curwrap;
- osh = sii->osh;
-
- if ((core_info[sii->curidx].coreid) == PMU_CORE_ID) {
- SI_ERROR(("Cannot access pmu DMP\n"));
- return;
- }
- cid = core_info[sii->curidx].coreid;
- addr = nci_get_nth_wrapper(sih, 0u);
- _nci_view(osh, ai, cid, addr, verbose);
-}
-
-void
-nci_viewall(si_t *sih, bool verbose)
-{
- const si_info_t *sii = SI_INFO(sih);
- nci_info_t *nci = sii->nci_info;
- const nci_cores_t *core_info = (const nci_cores_t *)nci->cores;
- osl_t *osh;
- aidmp_t *ai;
- uint32 cid, addr;
- uint i;
-
- osh = sii->osh;
- for (i = 0; i < sii->numcores; i++) {
- nci_setcoreidx(sih, i);
-
- if ((core_info[i].coreid) == PMU_CORE_ID) {
- SI_ERROR(("Skipping pmu DMP\n"));
- continue;
- }
- ai = sii->curwrap;
- cid = core_info[i].coreid;
- addr = nci_get_nth_wrapper(sih, 0u);
- _nci_view(osh, ai, cid, addr, verbose);
- }
-}
-#endif /* BCMDBG */
-
-uint32
-nci_clear_backplane_to(si_t *sih)
-{
- /* TODO: This is WIP and will be developed once the
- * implementation is done based on the NCI.
- */
- return 0;
-}
-
-#if defined (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC)
-static bool g_disable_backplane_logs = FALSE;
-
-static uint32 last_axi_error = AXI_WRAP_STS_NONE;
-static uint32 last_axi_error_log_status = 0;
-static uint32 last_axi_error_core = 0;
-static uint32 last_axi_error_wrap = 0;
-static uint32 last_axi_errlog_lo = 0;
-static uint32 last_axi_errlog_hi = 0;
-static uint32 last_axi_errlog_id = 0;
-
-/* slave error is ignored, so account for those cases */
-static uint32 si_ignore_errlog_cnt = 0;
-
-static void
-nci_reset_APB(const si_info_t *sii, aidmp_t *ai, int *ret,
- uint32 errlog_status, uint32 errlog_id)
-{
- /* only reset APB Bridge on timeout (not slave error, or dec error) */
- switch (errlog_status & AIELS_ERROR_MASK) {
- case AIELS_SLAVE_ERR:
- NCI_PRINT(("AXI slave error\n"));
- *ret |= AXI_WRAP_STS_SLAVE_ERR;
- break;
-
- case AIELS_TIMEOUT:
- nci_reset_axi_to(sii, ai);
- *ret |= AXI_WRAP_STS_TIMEOUT;
- break;
-
- case AIELS_DECODE:
- NCI_PRINT(("AXI decode error\n"));
-#ifdef USE_HOSTMEM
- /* Ignore known cases of CR4 prefetch abort bugs */
- if ((errlog_id & (BCM_AXI_ID_MASK | BCM_AXI_ACCESS_TYPE_MASK)) !=
- (BCM43xx_AXI_ACCESS_TYPE_PREFETCH | BCM43xx_CR4_AXI_ID))
-#endif /* USE_HOSTMEM */
- {
- *ret |= AXI_WRAP_STS_DECODE_ERR;
- }
- break;
- default:
- ASSERT(0); /* should be impossible */
- }
- if (errlog_status & AIELS_MULTIPLE_ERRORS) {
- NCI_PRINT(("Multiple AXI Errors\n"));
- /* Set multiple errors bit only if actual error is not ignored */
- if (*ret) {
- *ret |= AXI_WRAP_STS_MULTIPLE_ERRORS;
- }
- }
- return;
-}
-/*
- * API to clear the back plane timeout per core.
- * Caller may passs optional wrapper address. If present this will be used as
- * the wrapper base address. If wrapper base address is provided then caller
- * must provide the coreid also.
- * If both coreid and wrapper is zero, then err status of current bridge
- * will be verified.
- */
-
-uint32
-nci_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void *wrap)
-{
- int ret = AXI_WRAP_STS_NONE;
- aidmp_t *ai = NULL;
- uint32 errlog_status = 0;
- const si_info_t *sii = SI_INFO(sih);
- uint32 errlog_lo = 0, errlog_hi = 0, errlog_id = 0, errlog_flags = 0;
- uint32 current_coreidx = si_coreidx(sih);
- uint32 target_coreidx = nci_findcoreidx(sih, coreid, coreunit);
-
-#if defined(AXI_TIMEOUTS_NIC)
- si_axi_error_t * axi_error = sih->err_info ?
- &sih->err_info->axi_error[sih->err_info->count] : NULL;
-#endif /* AXI_TIMEOUTS_NIC */
- bool restore_core = FALSE;
-
- if ((sii->axi_num_wrappers == 0) ||
-#ifdef AXI_TIMEOUTS_NIC
- (!PCIE(sii)) ||
-#endif /* AXI_TIMEOUTS_NIC */
- FALSE) {
- SI_VMSG(("nci_clear_backplane_to_per_core, axi_num_wrappers:%d, Is_PCIE:%d,"
- " BUS_TYPE:%d, ID:%x\n",
- sii->axi_num_wrappers, PCIE(sii),
- BUSTYPE(sii->pub.bustype), sii->pub.buscoretype));
- return AXI_WRAP_STS_NONE;
- }
-
- if (wrap != NULL) {
- ai = (aidmp_t *)wrap;
- } else if (coreid && (target_coreidx != current_coreidx)) {
- if (nci_setcoreidx(sih, target_coreidx) == NULL) {
- /* Unable to set the core */
- NCI_PRINT(("Set Code Failed: coreid:%x, unit:%d, target_coreidx:%d\n",
- coreid, coreunit, target_coreidx));
- errlog_lo = target_coreidx;
- ret = AXI_WRAP_STS_SET_CORE_FAIL;
- goto end;
- }
- restore_core = TRUE;
- ai = (aidmp_t *)si_wrapperregs(sih);
- } else {
- /* Read error status of current wrapper */
- ai = (aidmp_t *)si_wrapperregs(sih);
-
- /* Update CoreID to current Code ID */
- coreid = nci_coreid(sih, sii->curidx);
- }
-
- /* read error log status */
- errlog_status = R_REG(sii->osh, &ai->errlogstatus);
-
- if (errlog_status == ID32_INVALID) {
- /* Do not try to peek further */
- NCI_PRINT(("nci_clear_backplane_to_per_core, errlogstatus:%x - "
- "Slave Wrapper:%x\n", errlog_status, coreid));
- ret = AXI_WRAP_STS_WRAP_RD_ERR;
- errlog_lo = (uint32)(uintptr)&ai->errlogstatus;
- goto end;
- }
-
- if ((errlog_status & AIELS_ERROR_MASK) != 0) {
- uint32 tmp;
- uint32 count = 0;
- /* set ErrDone to clear the condition */
- W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
-
- /* SPINWAIT on errlogstatus timeout status bits */
- while ((tmp = R_REG(sii->osh, &ai->errlogstatus)) & AIELS_ERROR_MASK) {
-
- if (tmp == ID32_INVALID) {
- NCI_PRINT(("nci_clear_backplane_to_per_core: prev errlogstatus:%x,"
- " errlogstatus:%x\n",
- errlog_status, tmp));
- ret = AXI_WRAP_STS_WRAP_RD_ERR;
-
- errlog_lo = (uint32)(uintptr)&ai->errlogstatus;
- goto end;
- }
- /*
- * Clear again, to avoid getting stuck in the loop, if a new error
- * is logged after we cleared the first timeout
- */
- W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
-
- count++;
- OSL_DELAY(10);
- if ((10 * count) > AI_REG_READ_TIMEOUT) {
- errlog_status = tmp;
- break;
- }
- }
-
- errlog_lo = R_REG(sii->osh, &ai->errlogaddrlo);
- errlog_hi = R_REG(sii->osh, &ai->errlogaddrhi);
- errlog_id = R_REG(sii->osh, &ai->errlogid);
- errlog_flags = R_REG(sii->osh, &ai->errlogflags);
-
- /* we are already in the error path, so OK to check for the slave error */
- if (nci_ignore_errlog(sii, ai, errlog_lo, errlog_hi, errlog_id, errlog_status)) {
- si_ignore_errlog_cnt++;
- goto end;
- }
-
- nci_reset_APB(sii, ai, &ret, errlog_status, errlog_id);
-
- NCI_PRINT(("\tCoreID: %x\n", coreid));
- NCI_PRINT(("\t errlog: lo 0x%08x, hi 0x%08x, id 0x%08x, flags 0x%08x"
- ", status 0x%08x\n",
- errlog_lo, errlog_hi, errlog_id, errlog_flags,
- errlog_status));
- }
-
-end:
- if (ret != AXI_WRAP_STS_NONE) {
- last_axi_error = ret;
- last_axi_error_log_status = errlog_status;
- last_axi_error_core = coreid;
- last_axi_error_wrap = (uint32)ai;
- last_axi_errlog_lo = errlog_lo;
- last_axi_errlog_hi = errlog_hi;
- last_axi_errlog_id = errlog_id;
- }
-
-#if defined(AXI_TIMEOUTS_NIC)
- if (axi_error && (ret != AXI_WRAP_STS_NONE)) {
- axi_error->error = ret;
- axi_error->coreid = coreid;
- axi_error->errlog_lo = errlog_lo;
- axi_error->errlog_hi = errlog_hi;
- axi_error->errlog_id = errlog_id;
- axi_error->errlog_flags = errlog_flags;
- axi_error->errlog_status = errlog_status;
- sih->err_info->count++;
-
- if (sih->err_info->count == SI_MAX_ERRLOG_SIZE) {
- sih->err_info->count = SI_MAX_ERRLOG_SIZE - 1;
- NCI_PRINT(("AXI Error log overflow\n"));
- }
- }
-#endif /* AXI_TIMEOUTS_NIC */
-
- if (restore_core) {
- if (nci_setcoreidx(sih, current_coreidx) == NULL) {
- /* Unable to set the core */
- return ID32_INVALID;
- }
- }
- return ret;
-}
-
-/* TODO: It needs to be handled based on BOOKER/NCI DMP. */
-/* reset AXI timeout */
-static void
-nci_reset_axi_to(const si_info_t *sii, aidmp_t *ai)
-{
- /* reset APB Bridge */
- OR_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
- /* sync write */
- (void)R_REG(sii->osh, &ai->resetctrl);
- /* clear Reset bit */
- AND_REG(sii->osh, &ai->resetctrl, ~(AIRC_RESET));
- /* sync write */
- (void)R_REG(sii->osh, &ai->resetctrl);
- NCI_PRINT(("AXI timeout\n"));
- if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) {
- NCI_PRINT(("reset failed on wrapper %p\n", ai));
- g_disable_backplane_logs = TRUE;
- }
-}
-
-void
-nci_wrapper_get_last_error(const si_t *sih, uint32 *error_status, uint32 *core, uint32 *lo,
- uint32 *hi, uint32 *id)
-{
- *error_status = last_axi_error_log_status;
- *core = last_axi_error_core;
- *lo = last_axi_errlog_lo;
- *hi = last_axi_errlog_hi;
- *id = last_axi_errlog_id;
-}
-
-uint32
-nci_get_axi_timeout_reg(void)
-{
- return (GOODREGS(last_axi_errlog_lo) ? last_axi_errlog_lo : 0);
-}
-#endif /* AXI_TIMEOUTS || AXI_TIMEOUTS_NIC */
-
-/* TODO: This function should be able to handle NIC as well as BOOKER */
-bool
-nci_ignore_errlog(const si_info_t *sii, const aidmp_t *ai,
- uint32 lo_addr, uint32 hi_addr, uint32 err_axi_id, uint32 errsts)
-{
- uint32 ignore_errsts = AIELS_SLAVE_ERR;
- uint32 ignore_errsts_2 = 0;
- uint32 ignore_hi = BT_CC_SPROM_BADREG_HI;
- uint32 ignore_lo = BT_CC_SPROM_BADREG_LO;
- uint32 ignore_size = BT_CC_SPROM_BADREG_SIZE;
- bool address_check = TRUE;
- uint32 axi_id = 0;
- uint32 axi_id2 = 0;
- bool extd_axi_id_mask = FALSE;
- uint32 axi_id_mask;
-
- NCI_PRINT(("err check: core %p, error %d, axi id 0x%04x, addr(0x%08x:%08x)\n",
- ai, errsts, err_axi_id, hi_addr, lo_addr));
-
- /* ignore the BT slave errors if the errlog is to chipcommon addr 0x190 */
- switch (CHIPID(sii->pub.chip)) {
- case BCM4397_CHIP_GRPID: /* TODO: Are these IDs same for 4397 as well? */
-#ifdef BTOVERPCIE
- axi_id = BCM4378_BT_AXI_ID;
- /* For BT over PCIE, ignore any slave error from BT. */
- /* No need to check any address range */
- address_check = FALSE;
-#endif /* BTOVERPCIE */
- axi_id2 = BCM4378_ARM_PREFETCH_AXI_ID;
- extd_axi_id_mask = TRUE;
- ignore_errsts_2 = AIELS_DECODE;
- break;
- default:
- return FALSE;
- }
-
- axi_id_mask = extd_axi_id_mask ? AI_ERRLOGID_AXI_ID_MASK_EXTD : AI_ERRLOGID_AXI_ID_MASK;
-
- /* AXI ID check */
- err_axi_id &= axi_id_mask;
- errsts &= AIELS_ERROR_MASK;
-
- /* check the ignore error cases. 2 checks */
- if (!(((err_axi_id == axi_id) && (errsts == ignore_errsts)) ||
- ((err_axi_id == axi_id2) && (errsts == ignore_errsts_2)))) {
- /* not the error ignore cases */
- return FALSE;
-
- }
-
- /* check the specific address checks now, if specified */
- if (address_check) {
- /* address range check */
- if ((hi_addr != ignore_hi) ||
- (lo_addr < ignore_lo) || (lo_addr >= (ignore_lo + ignore_size))) {
- return FALSE;
- }
- }
-
- NCI_PRINT(("err check: ignored\n"));
- return TRUE;
-}
-
-/* TODO: Check the CORE to AXI ID mapping for 4397 */
-uint32
-nci_findcoreidx_by_axiid(const si_t *sih, uint32 axiid)
-{
- uint coreid = 0;
- uint coreunit = 0;
- const nci_axi_to_coreidx_t *axi2coreidx = NULL;
- switch (CHIPID(sih->chip)) {
- case BCM4397_CHIP_GRPID:
- axi2coreidx = axi2coreidx_4397;
- break;
- default:
- NCI_PRINT(("Chipid mapping not found\n"));
- break;
- }
-
- if (!axi2coreidx) {
- return (BADIDX);
- }
-
- coreid = axi2coreidx[axiid].coreid;
- coreunit = axi2coreidx[axiid].coreunit;
-
- return nci_findcoreidx(sih, coreid, coreunit);
-}
-
-void nci_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size)
-{
- /* Adding just a wrapper. Will implement when required. */
-}
-
-/*
- * this is not declared as static const, although that is the right thing to do
- * reason being if declared as static const, compile/link process would that in
- * read only section...
- * currently this code/array is used to identify the registers which are dumped
- * during trap processing
- * and usually for the trap buffer, .rodata buffer is reused, so for now just static
-*/
-/* TODO: Should we do another mapping for BOOKER and used correct one based on type of DMP. */
-#ifdef DONGLEBUILD
-static uint32 BCMPOST_TRAP_RODATA(wrapper_offsets_to_dump)[] = {
- OFFSETOF(aidmp_t, ioctrl),
- OFFSETOF(aidmp_t, iostatus),
- OFFSETOF(aidmp_t, resetctrl),
- OFFSETOF(aidmp_t, resetstatus),
- OFFSETOF(aidmp_t, resetreadid),
- OFFSETOF(aidmp_t, resetwriteid),
- OFFSETOF(aidmp_t, errlogctrl),
- OFFSETOF(aidmp_t, errlogdone),
- OFFSETOF(aidmp_t, errlogstatus),
- OFFSETOF(aidmp_t, errlogaddrlo),
- OFFSETOF(aidmp_t, errlogaddrhi),
- OFFSETOF(aidmp_t, errlogid),
- OFFSETOF(aidmp_t, errloguser),
- OFFSETOF(aidmp_t, errlogflags),
- OFFSETOF(aidmp_t, itipoobaout),
- OFFSETOF(aidmp_t, itipoobbout),
- OFFSETOF(aidmp_t, itipoobcout),
- OFFSETOF(aidmp_t, itipoobdout)
-};
-
-static uint32
-BCMRAMFN(nci_get_sizeof_wrapper_offsets_to_dump)(void)
-{
- return (sizeof(wrapper_offsets_to_dump));
-}
-
-static uint32
-BCMRAMFN(nci_get_wrapper_base_addr)(uint32 **offset)
-{
- uint32 arr_size = ARRAYSIZE(wrapper_offsets_to_dump);
-
- *offset = &wrapper_offsets_to_dump[0];
- return arr_size;
-}
-
-#ifdef UART_TRAP_DBG
-/* TODO: Is br_wrapba populated for 4397 NCI? */
-void
-nci_dump_APB_Bridge_registers(const si_t *sih)
-{
- aidmp_t *ai;
- const si_info_t *sii = SI_INFO(sih);
-
- ai = (aidmp_t *)sii->br_wrapba[0];
- printf("APB Bridge 0\n");
- printf("lo 0x%08x, hi 0x%08x, id 0x%08x, flags 0x%08x",
- R_REG(sii->osh, &ai->errlogaddrlo),
- R_REG(sii->osh, &ai->errlogaddrhi),
- R_REG(sii->osh, &ai->errlogid),
- R_REG(sii->osh, &ai->errlogflags));
- printf("\n status 0x%08x\n", R_REG(sii->osh, &ai->errlogstatus));
-}
-#endif /* UART_TRAP_DBG */
-
-uint32
-BCMATTACHFN(nci_wrapper_dump_buf_size)(const si_t *sih)
-{
- uint32 buf_size = 0;
- uint32 wrapper_count = 0;
- const si_info_t *sii = SI_INFO(sih);
-
- wrapper_count = sii->axi_num_wrappers;
- if (wrapper_count == 0) {
- return 0;
- }
-
- /* cnt indicates how many registers, tag_id 0 will say these are address/value */
- /* address/value pairs */
- buf_size += 2 * (nci_get_sizeof_wrapper_offsets_to_dump() * wrapper_count);
-
- return buf_size;
-}
-
-uint32*
-nci_wrapper_dump_binary_one(const si_info_t *sii, uint32 *p32, uint32 wrap_ba)
-{
- uint i;
- uint32 *addr;
- uint32 arr_size;
- uint32 *offset_base;
-
- arr_size = nci_get_wrapper_base_addr(&offset_base);
-
- for (i = 0; i < arr_size; i++) {
- addr = (uint32 *)(wrap_ba + *(offset_base + i));
- *p32++ = (uint32)addr;
- *p32++ = R_REG(sii->osh, addr);
- }
- return p32;
-}
-
-uint32
-nci_wrapper_dump_binary(const si_t *sih, uchar *p)
-{
- uint32 *p32 = (uint32 *)p;
- uint32 i;
- const si_info_t *sii = SI_INFO(sih);
-
- for (i = 0; i < sii->axi_num_wrappers; i++) {
- p32 = nci_wrapper_dump_binary_one(sii, p32, sii->axi_wrapper[i].wrapper_addr);
- }
- return 0;
-}
-
-#if defined(ETD)
-uint32
-nci_wrapper_dump_last_timeout(const si_t *sih, uint32 *error, uint32 *core, uint32 *ba, uchar *p)
-{
-#if defined (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC)
- uint32 *p32;
- uint32 wrap_ba = last_axi_error_wrap;
- uint i;
- uint32 *addr;
-
- const si_info_t *sii = SI_INFO(sih);
-
- if (last_axi_error != AXI_WRAP_STS_NONE) {
- if (wrap_ba) {
- p32 = (uint32 *)p;
- uint32 arr_size;
- uint32 *offset_base;
-
- arr_size = nci_get_wrapper_base_addr(&offset_base);
- for (i = 0; i < arr_size; i++) {
- addr = (uint32 *)(wrap_ba + *(offset_base + i));
- *p32++ = R_REG(sii->osh, addr);
- }
- }
- *error = last_axi_error;
- *core = last_axi_error_core;
- *ba = wrap_ba;
- }
-#else
- *error = 0;
- *core = 0;
- *ba = 0;
-#endif /* AXI_TIMEOUTS || AXI_TIMEOUTS_NIC */
- return 0;
-}
-#endif /* ETD */
-
-bool
-nci_check_enable_backplane_log(const si_t *sih)
-{
-#if defined (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC)
- if (g_disable_backplane_logs) {
- return FALSE;
- }
- else {
- return TRUE;
- }
-#else /* (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC) */
- return FALSE;
-#endif /* (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC) */
-}
-#endif /* DONGLEBUILD */
}
}
- channel = wl_ext_autochannel(dev, ACS_DRV_BIT, band);
+ chosen = wl_ext_autochannel(dev, ACS_DRV_BIT, band);
+ channel = wf_chspec_ctlchan(chosen);
if (channel) {
acs_band = CHSPEC_BAND(channel);
goto done2;
}
param.band = chan_info->band;
- err = wl_ext_iovar_getbuf(dev, "bw_cap", ¶m, sizeof(param),
+ err = wldev_iovar_getbuf(dev, "bw_cap", ¶m, sizeof(param),
iovar_buf, WLC_IOCTL_SMLEN, NULL);
if (err) {
if (err != BCME_UNSUPPORTED) {
- AEXT_ERROR(dev->name, "bw_cap failed, %d\n", err);
+ AEXT_TRACE(dev->name, "bw_cap failed, %d\n", err);
return err;
} else {
err = wl_ext_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
static int
wl_ext_channel(struct net_device *dev, char* command, int total_len)
{
+ struct dhd_pub *dhd = dhd_get_pub(dev);
struct wl_chan_info chan_info;
- int ret;
- char band[16]="";
- int channel = 0;
- channel_info_t ci;
- int bytes_written = 0;
- chanspec_t fw_chspec;
+ char chan[16]="";
+ int ret, bytes_written = 0;
+ chanspec_t chanspec;
+ u32 fw_chanspec = 0;
+
+ /* get: dhd_priv channel
+ * set: dhd_priv channel [6|36|2g6|5g36|6g5]
+ */
AEXT_TRACE(dev->name, "cmd %s", command);
- sscanf(command, "%*s %d %s", &channel, band);
- if (strnicmp(band, "band=auto", strlen("band=auto")) == 0) {
- chan_info.band = WLC_BAND_AUTO;
+ sscanf(command, "%*s %s", chan);
+ memset(&chan_info, 0, sizeof(struct wl_chan_info));
+ if (strnicmp(chan, "2g", strlen("2g")) == 0) {
+ chan_info.band = WLC_BAND_2G;
+ chan_info.chan = (int)simple_strtol(chan+2, NULL, 10);
+ }
+ else if (strnicmp(chan, "5g", strlen("5g")) == 0) {
+ chan_info.band = WLC_BAND_5G;
+ chan_info.chan = (int)simple_strtol(chan+2, NULL, 10);
}
#ifdef WL_6G_BAND
- else if (strnicmp(band, "band=6g", strlen("band=6g")) == 0) {
+ else if (strnicmp(chan, "6g", strlen("6g")) == 0) {
chan_info.band = WLC_BAND_6G;
+ chan_info.chan = (int)simple_strtol(chan+2, NULL, 10);
}
#endif /* WL_6G_BAND */
- else if (strnicmp(band, "band=5g", strlen("band=5g")) == 0) {
- chan_info.band = WLC_BAND_5G;
- }
- else if (strnicmp(band, "band=2g", strlen("band=2g")) == 0) {
- chan_info.band = WLC_BAND_2G;
+ else if (strlen(chan)) {
+ chan_info.chan = (int)simple_strtol(chan, NULL, 10);
+ if (chan_info.chan <= CH_MAX_2G_CHANNEL)
+ chan_info.band = WLC_BAND_2G;
+ else
+ chan_info.band = WLC_BAND_5G;
}
- else if (channel <= CH_MAX_2G_CHANNEL)
- chan_info.band = WLC_BAND_2G;
- else
- chan_info.band = WLC_BAND_5G;
- if (channel > 0) {
- chan_info.chan = channel;
- ret = wl_ext_set_chanspec(dev, &chan_info, &fw_chspec);
+ if (chan_info.chan > 0) {
+ ret = wl_ext_set_chanspec(dev, &chan_info, &chanspec);
} else {
- if (!(ret = wl_ext_ioctl(dev, WLC_GET_CHANNEL, &ci,
- sizeof(channel_info_t), FALSE))) {
- AEXT_TRACE(dev->name, "hw_channel %d\n", ci.hw_channel);
- AEXT_TRACE(dev->name, "target_channel %d\n", ci.target_channel);
- AEXT_TRACE(dev->name, "scan_channel %d\n", ci.scan_channel);
- bytes_written = snprintf(command, sizeof(channel_info_t)+2,
- "channel %d", ci.hw_channel);
- AEXT_TRACE(dev->name, "command result is %s\n", command);
+ ret = wl_ext_iovar_getint(dev, "chanspec", (s32 *)&fw_chanspec);
+ if (ret == BCME_OK) {
+ chanspec = fw_chanspec;
+ chanspec = wl_ext_chspec_driver_to_host(dhd, chanspec);
+ chan_info.band = CHSPEC2WLC_BAND(chanspec);
+ chan_info.chan = wf_chspec_ctlchan(chanspec);
+ if (chan_info.band == WLC_BAND_6G) {
+ bytes_written = snprintf(command, total_len,
+ "channel 6g%d", chan_info.chan);
+ } else {
+ bytes_written = snprintf(command, total_len,
+ "channel %d", chan_info.chan);
+ }
ret = bytes_written;
}
}
{
int ret, i;
int bytes_written = -1;
- u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
- wl_uint32_list_t *list;
+ wl_uint32_list_t *list = NULL;
+ chanspec_t chspec;
+ u32 channel;
AEXT_TRACE(dev->name, "cmd %s", command);
- memset(valid_chan_list, 0, sizeof(valid_chan_list));
- list = (wl_uint32_list_t *)(void *) valid_chan_list;
- list->count = htod32(WL_NUMCHANNELS);
- ret = wl_ext_ioctl(dev, WLC_GET_VALID_CHANNELS, valid_chan_list,
- sizeof(valid_chan_list), 0);
- if (ret<0) {
+ list = kzalloc(sizeof(u32)*(MAX_CTRL_CHANSPECS + 1), GFP_KERNEL);
+ if (list == NULL) {
+ AEXT_ERROR(dev->name, "kzalloc failed\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ ret = wl_construct_ctl_chanspec_list(dev, list);
+ if (ret < 0) {
AEXT_ERROR(dev->name, "get channels failed with %d\n", ret);
+ goto exit;
} else {
- bytes_written = snprintf(command, total_len, "channels");
- for (i = 0; i < dtoh32(list->count); i++) {
- bytes_written += snprintf(command+bytes_written, total_len, " %d",
- dtoh32(list->element[i]));
+ bytes_written = 0;
+ for (i = 0; i < list->count; i++) {
+ chspec = list->element[i];
+ channel = wf_chspec_ctlchan(chspec);
+#ifdef WL_6G_BAND
+ if (CHSPEC_IS6G(chspec) && (channel >= CH_MIN_6G_CHANNEL) &&
+ (channel <= CH_MAX_6G_CHANNEL)) {
+ bytes_written += snprintf(command+bytes_written, total_len, "6g%d ",
+ channel);
+ } else
+#endif
+ {
+ bytes_written += snprintf(command+bytes_written, total_len, "%d ",
+ channel);
+ }
}
AEXT_TRACE(dev->name, "command result is %s\n", command);
ret = bytes_written;
}
+exit:
+ if (list)
+ kfree(list);
return ret;
}
s32 err = BCME_OK;
param.band = band;
- err = wl_ext_iovar_getbuf(net, "bw_cap", ¶m, sizeof(param), buf,
+ err = wldev_iovar_getbuf(net, "bw_cap", ¶m, sizeof(param), buf,
sizeof(buf), NULL);
if (err) {
if (err != BCME_UNSUPPORTED) {
- AEXT_ERROR(net->name, "bw_cap failed, %d\n", err);
+ AEXT_TRACE(net->name, "bw_cap failed, %d\n", err);
return err;
} else {
err = wl_ext_iovar_getint(net, "mimo_bw_cap", &bw_cap);
s32 distance_6g;
#endif /* WL_6G_BAND */
s32 cen_ch, distance, distance_2g, distance_5g, chanspec, min_ap=999;
- u8 valid_chan_list[sizeof(u32)*(MAX_CTRL_CHANSPECS + 1)];
- wl_uint32_list_t *list;
+ wl_uint32_list_t *list = NULL;
int ret;
chanspec_t chspec;
u32 channel;
memset(six_g_band8, -1, sizeof(six_g_band8));
#endif /* WL_6G_BAND */
- memset(valid_chan_list, 0, sizeof(valid_chan_list));
- list = (wl_uint32_list_t *)(void *) valid_chan_list;
+ list = kzalloc(sizeof(u32)*(MAX_CTRL_CHANSPECS + 1), GFP_KERNEL);
+ if (list == NULL) {
+ AEXT_ERROR(net->name, "kzalloc failed\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
ret = wl_construct_ctl_chanspec_list(net, list);
if (ret < 0) {
AEXT_ERROR(net->name, "get channels failed with %d\n", ret);
- return 0;
+ goto exit;
} else {
for (i = 0; i < list->count; i++) {
chspec = list->element[i];
}
exit:
- return 0;
+ if (list)
+ kfree(list);
+ return ret;
}
#endif /* WL_CFG80211 || WL_ESCAN */
kfree(reqbuf);
}
- return channel;
+ return chosen;
}
#endif /* WL_CFG80211 */
{
int ret = -1, i, cnt = 0;
int retry = 0, retry_max, retry_interval = 250, up = 1;
- wl_scan_info_t scan_info;
+ wl_scan_info_t *scan_info = NULL;
+
+ scan_info = kmalloc(sizeof(wl_scan_info_t), GFP_KERNEL);
+ if (scan_info == NULL) {
+ AEXT_ERROR(dev->name, "kzalloc failed\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
retry_max = WL_ESCAN_TIMER_INTERVAL_MS/retry_interval;
ret = wldev_ioctl_get(dev, WLC_GET_UP, &up, sizeof(s32));
if (ret < 0 || up == 0) {
ret = wldev_ioctl_set(dev, WLC_UP, &up, sizeof(s32));
}
- memset(&scan_info, 0, sizeof(wl_scan_info_t));
+ memset(scan_info, 0, sizeof(wl_scan_info_t));
if (band == WLC_BAND_2G || band == WLC_BAND_AUTO) {
for (i=0; i<13; i++) {
- scan_info.channels.channel[i+cnt] = wf_create_chspec_from_primary(i+1,
+ scan_info->channels.channel[i+cnt] = wf_create_chspec_from_primary(i+1,
WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_2G);
}
cnt += 13;
}
if (band == WLC_BAND_5G || band == WLC_BAND_AUTO) {
for (i=0; i<4; i++) {
- scan_info.channels.channel[i+cnt] = wf_create_chspec_from_primary(36+i*4,
+ scan_info->channels.channel[i+cnt] = wf_create_chspec_from_primary(36+i*4,
WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_5G);
}
cnt += 4;
for (i=0; i<4; i++) {
- scan_info.channels.channel[i+cnt] = wf_create_chspec_from_primary(149+i*4,
+ scan_info->channels.channel[i+cnt] = wf_create_chspec_from_primary(149+i*4,
WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_5G);
}
cnt += 4;
#ifdef WL_6G_BAND
if (band == WLC_BAND_6G || band == WLC_BAND_AUTO) {
for (i=0; i<59; i++) {
- scan_info.channels.channel[i+cnt] = wf_create_chspec_from_primary(1+i*4,
+ scan_info->channels.channel[i+cnt] = wf_create_chspec_from_primary(1+i*4,
WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_6G);
}
cnt += 59;
#endif /* WL_6G_BAND */
if (band == WLC_BAND_2G)
fast_scan = FALSE;
- scan_info.channels.count = cnt;
+ scan_info->channels.count = cnt;
if (fast_scan)
- scan_info.scan_time = 40;
- scan_info.bcast_ssid = TRUE;
+ scan_info->scan_time = 40;
+ scan_info->bcast_ssid = TRUE;
retry = retry_max;
while (retry--) {
- ret = wl_escan_set_scan(dev, &scan_info);
+ ret = wl_escan_set_scan(dev, scan_info);
if (!ret)
break;
OSL_SLEEP(retry_interval);
ret = -1;
}
+exit:
+ if (scan_info)
+ kfree(scan_info);
return ret;
}
-int
+static int
wl_ext_drv_apcs(struct net_device *dev, uint32 band)
{
- int ret = 0, channel = 0;
+ int ret = 0, chanspec = 0;
struct dhd_pub *dhd = dhd_get_pub(dev);
struct wl_escan_info *escan = NULL;
int retry = 0, retry_max, retry_interval = 250;
retry = retry_max;
while (retry--) {
if (escan->escan_state == ESCAN_STATE_IDLE) {
- if (band == WLC_BAND_5G)
- channel = escan->best_5g_ch;
+ if (band == WLC_BAND_5G) {
+ chanspec = wf_create_chspec_from_primary(wf_chspec_primary20_chan(escan->best_5g_ch),
+ WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_5G);
+ }
#ifdef WL_6G_BAND
- else if (band == WLC_BAND_6G)
- channel = escan->best_6g_ch;
+ else if (band == WLC_BAND_6G) {
+ chanspec = wf_create_chspec_from_primary(wf_chspec_primary20_chan(escan->best_6g_ch),
+ WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_6G);
+ }
#endif /* WL_6G_BAND */
- else
- channel = escan->best_2g_ch;
- WL_MSG(dev->name, "selected channel = %d\n", channel);
+ else {
+ chanspec = wf_create_chspec_from_primary(wf_chspec_primary20_chan(escan->best_2g_ch),
+ WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_2G);
+ }
+ WL_MSG(dev->name, "selected channel = %d(0x%x)\n",
+ wf_chspec_ctlchan(chanspec), chanspec);
goto done;
}
AEXT_INFO(dev->name, "escan_state=%d, %d tried, ret = %d\n",
done:
escan->autochannel = 0;
- return channel;
+ return chanspec;
}
#endif /* WL_ESCAN */
int
wl_ext_autochannel(struct net_device *dev, uint acs, uint32 band)
{
- int channel = 0;
- uint16 chan_2g, chan_5g;
+ int chosen = 0;
+ uint16 chan_2g, chan_5g, channel;
- AEXT_INFO(dev->name, "acs=0x%x, band=%d \n", acs, band);
+ AEXT_INFO(dev->name, "acs=0x%x, band=%s\n", acs, WLCBAND2STR(band));
#ifdef WL_CFG80211
if (acs & ACS_FW_BIT) {
int ret = 0;
ret = wldev_ioctl_get(dev, WLC_GET_CHANNEL_SEL, &channel, sizeof(channel));
- channel = 0;
+ chosen = 0;
if (ret != BCME_UNSUPPORTED)
- channel = wl_ext_fw_apcs(dev, band);
- if (channel)
- return channel;
+ chosen = wl_ext_fw_apcs(dev, band);
+ if (chosen)
+ return chosen;
}
#endif
#ifdef WL_ESCAN
if (acs & ACS_DRV_BIT)
- channel = wl_ext_drv_apcs(dev, band);
+ chosen = wl_ext_drv_apcs(dev, band);
#endif /* WL_ESCAN */
- if (channel == 0) {
+ if (chosen == 0) {
wl_ext_get_default_chan(dev, &chan_2g, &chan_5g, TRUE);
if (band == WLC_BAND_5G) {
+ chosen = wf_create_chspec_from_primary(wf_chspec_primary20_chan(chan_5g),
+ WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_5G);
channel = chan_5g;
} else {
+ chosen = wf_create_chspec_from_primary(wf_chspec_primary20_chan(chan_2g),
+ WL_CHANSPEC_BW_20, WL_CHANSPEC_BAND_2G);
channel = chan_2g;
}
- AEXT_ERROR(dev->name, "ACS failed. Fall back to default channel (%d) \n", channel);
+ AEXT_ERROR(dev->name, "ACS failed. Fall back to default channel (%s-%d) \n",
+ CHSPEC2BANDSTR(chosen), channel);
}
- return channel;
+ return chosen;
}
#if defined(RSSIAVG)
#define WLCBAND2STR(band) ((band == WLC_BAND_2G) ? "2g" : (band == WLC_BAND_5G) ? \
"5g" : "0g")
#endif /* WL_6G_BAND */
+#define WLCWIDTH2STR(width) ((width == WL_CHANSPEC_BW_20) ? "20" : (width == WL_CHANSPEC_BW_40) ? \
+ "40" : (width == WL_CHANSPEC_BW_80) ? "80" : (width == WL_CHANSPEC_BW_160) ? "160" : "0")
#endif
*/
REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
/* IEEE 802.11a, channel 36..64 */
- REG_RULE(5150-10, 5350+10, 40, 6, 20, 0),
+ REG_RULE(5150-10, 5350+10, 80, 6, 20, 0),
/* IEEE 802.11a, channel 100..165 */
- REG_RULE(5470-10, 5850+10, 40, 6, 20, 0),
+ REG_RULE(5470-10, 5850+10, 80, 6, 20, 0),
#ifdef WL_6G_BAND
REG_RULE(6025-80, 6985+80, 160, 6, 20, 0),
REG_RULE(5935-10, 7115+10, 20, 6, 20, 0),
};
#endif /* CFG80211_6G_SUPPORT */
+#ifdef WL_CAP_HE
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) || defined(CONFIG_6GHZ_BKPORT)
+static struct ieee80211_sband_iftype_data __wl_he_cap = {
+ .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP),
+ .he_cap = {
+ .has_he = true,
+ .he_cap_elem = {
+ .mac_cap_info[0] = (IEEE80211_HE_MAC_CAP0_HTC_HE |
+ IEEE80211_HE_MAC_CAP0_TWT_REQ),
+ .mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US,
+ .mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_BSR,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
+ .mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) */
+
+ .phy_cap_info[0] =
+ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
+ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
+ .phy_cap_info[1] =
+ IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
+ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
+ .phy_cap_info[2] =
+ IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
+ .phy_cap_info[3] =
+ IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER,
+ .phy_cap_info[4] =
+ IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
+ IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_MASK |
+ IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4,
+ .phy_cap_info[5] =
+ IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2,
+ .phy_cap_info[6] =
+ IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
+ IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0))
+ IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
+ IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
+#else
+ IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB |
+ IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB |
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0) */
+ IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
+ IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
+ .phy_cap_info[7] =
+ IEEE80211_HE_PHY_CAP7_MAX_NC_1,
+ .phy_cap_info[8] =
+ IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
+ IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))
+ .phy_cap_info[9] =
+ IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
+ IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU,
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) */
+ },
+ .he_mcs_nss_supp = {
+ .rx_mcs_80 = cpu_to_le16(0xfffa),
+ .tx_mcs_80 = cpu_to_le16(0xfffa),
+ .rx_mcs_160 = cpu_to_le16((0xfffa)),
+ .tx_mcs_160 = cpu_to_le16((0xfffa)),
+ }
+ },
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
+ .he_6ghz_capa = {.capa = cpu_to_le16(0x3038)},
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) */
+};
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) */
+#endif /* WL_CAP_HE */
+
static struct ieee80211_supported_band __wl_band_2ghz = {
.band = IEEE80211_BAND_2GHZ,
.channels = __wl_2ghz_channels,
.n_channels = ARRAY_SIZE(__wl_2ghz_channels),
.bitrates = wl_g_rates,
- .n_bitrates = wl_g_rates_size
+ .n_bitrates = wl_g_rates_size,
+#ifdef WL_CAP_HE
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) || defined(CONFIG_6GHZ_BKPORT)
+ .iftype_data = &__wl_he_cap,
+ .n_iftype_data = 1
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) */
+#endif /* WL_CAP_HE */
};
static struct ieee80211_supported_band __wl_band_5ghz_a = {
.channels = __wl_5ghz_a_channels,
.n_channels = ARRAY_SIZE(__wl_5ghz_a_channels),
.bitrates = wl_a_rates,
- .n_bitrates = wl_a_rates_size
+ .n_bitrates = wl_a_rates_size,
+#ifdef WL_CAP_HE
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) || defined(CONFIG_6GHZ_BKPORT)
+ .iftype_data = &__wl_he_cap,
+ .n_iftype_data = 1
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) */
+#endif /* WL_CAP_HE */
};
#ifdef CFG80211_6G_SUPPORT
.channels = __wl_6ghz_channels,
.n_channels = ARRAY_SIZE(__wl_6ghz_channels),
.bitrates = wl_a_rates,
- .n_bitrates = wl_a_rates_size
+ .n_bitrates = wl_a_rates_size,
+#ifdef WL_CAP_HE
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) || defined(CONFIG_6GHZ_BKPORT)
+ .iftype_data = &__wl_he_cap,
+ .n_iftype_data = 1
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) */
+#endif /* WL_CAP_HE */
};
#endif /* CFG80211_6G_SUPPORT */
}
if (conn_in_progress || connected ||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
- wdev->u.client.ssid_len
+ wdev->u.client.ssid_len)
#else
- wdev->ssid_len
-#endif
- ) {
+ wdev->ssid_len)
+#endif /* CFG80211_BKPORT_MLO */
+ {
#ifdef WL_EXT_IAPSTA
wl_ext_in4way_sync(dev, 0, WL_EXT_STATUS_PRE_DISCONNECTING, NULL);
#endif
* disassoc indicates state mismatch with upper layer. Check for state
* and issue disconnect indication if required.
*/
-
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
- // terence 20220911: fix me
- if (wdev->links[0].client.current_bss || wdev->u.client.ssid_len)
+ if (wdev->connected || wdev->u.client.ssid_len)
#else
if (wdev->current_bss || wdev->ssid_len)
-#endif
+#endif /* CFG80211_BKPORT_MLO */
{
WL_INFORM_MEM(("report disconnect event\n"));
CFG80211_DISCONNECTED(dev, 0, NULL, 0, false, GFP_KERNEL);
chan = &band->channels[idx];
/* Setting current channel to the requested channel */
if ((err = wl_cfg80211_set_channel(wiphy, ndev, chan,
- NL80211_CHAN_HT20) < 0)) {
+ NL80211_CHAN_WIDTH_20) < 0)) {
/*
* FIXME:
*
ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
if (ndev) {
wdev = ndev->ieee80211_ptr;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
+ wdev->u.client.ssid_len =
+ min(ssid->SSID_len, (uint32)DOT11_MAX_SSID_LEN);
+ memcpy(wdev->u.client.ssid, ssid->SSID, wdev->u.client.ssid_len);
+#else
wdev->ssid_len = min(ssid->SSID_len, (uint32)DOT11_MAX_SSID_LEN);
memcpy(wdev->ssid, ssid->SSID, wdev->ssid_len);
+#endif /* CFG80211_BKPORT_MLO */
WL_ERR(("SSID is %s\n", ssid->SSID));
wl_update_prof(cfg, ndev, NULL, ssid, WL_PROF_SSID);
} else {
(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) || \
defined(WL_FILS_ROAM_OFFLD) || defined(CFG80211_ROAM_API_GE_4_12)
memset(&roam_info, 0, sizeof(struct cfg80211_roam_info));
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(CFG80211_BKPORT_MLO)
roam_info.links[0].channel = notify_channel;
roam_info.links[0].bssid = curbssid;
#else
roam_info.channel = notify_channel;
roam_info.bssid = curbssid;
-#endif
+#endif /* CFG80211_BKPORT_MLO */
roam_info.req_ie = conn_info->req_ie;
roam_info.req_ie_len = conn_info->req_ie_len;
roam_info.resp_ie = conn_info->resp_ie;
resp_params = (struct cfg80211_connect_resp_params *)params;
resp_params->status = status;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(CFG80211_BKPORT_MLO)
resp_params->links[0].bssid = curbssid;
resp_params->links[0].bss = CFG80211_GET_BSS(wiphy, NULL, curbssid,
ssid->SSID, ssid->SSID_len);
resp_params->bss = CFG80211_GET_BSS(wiphy, NULL, curbssid,
ssid->SSID, ssid->SSID_len);
#endif
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(CFG80211_BKPORT_MLO)
if (!resp_params->links[0].bss)
#else
if (!resp_params->bss)
-#endif
+#endif /* CFG80211_BKPORT_MLO */
{
WL_ERR(("null bss\n"));
return BCME_ERROR;
if (!ndev->ieee80211_ptr->u.client.ssid_len)
#else
if (!ndev->ieee80211_ptr->ssid_len)
-#endif
+#endif /* CFG80211_BKPORT_MLO */
{
/* In certain cases, the delayed cfg80211 work from
* disconnect context will induce race conditions in
return err;
}
-static int wl_construct_reginfo(struct bcm_cfg80211 *cfg, s32 bw_cap)
+static int wl_construct_reginfo(struct bcm_cfg80211 *cfg, s32 bw_cap_2g,
+ s32 bw_cap_5g, s32 bw_cap_6g)
{
struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
struct ieee80211_channel *band_chan_arr = NULL;
(channel <= CH_MAX_2G_CHANNEL)) {
band_chan_arr = __wl_2ghz_channels;
array_size = ARRAYSIZE(__wl_2ghz_channels);
- ht40_allowed = (bw_cap == WLC_N_BW_40ALL)? true : false;
}
#ifdef CFG80211_6G_SUPPORT
else if (CHSPEC_IS6G(chspec) && (channel >= CH_MIN_6G_CHANNEL) &&
(channel <= CH_MAX_6G_CHANNEL)) {
band_chan_arr = __wl_6ghz_channels;
array_size = ARRAYSIZE(__wl_6ghz_channels);
- ht40_allowed = (bw_cap == WLC_N_BW_20ALL)? false : true;
+ ht40_allowed = WL_BW_CAP_40MHZ(bw_cap_6g);
}
#endif /* CFG80211_6G_SUPPORT */
else if (
(CHSPEC_IS5G(chspec) && channel >= CH_MIN_5G_CHANNEL)) {
band_chan_arr = __wl_5ghz_a_channels;
array_size = ARRAYSIZE(__wl_5ghz_a_channels);
- ht40_allowed = (bw_cap == WLC_N_BW_20ALL)? false : true;
+ ht40_allowed = WL_BW_CAP_40MHZ(bw_cap_5g);
} else {
WL_ERR(("Invalid channel Sepc. 0x%x.\n", chspec));
continue;
if (!ht40_allowed && CHSPEC_IS40(chspec))
continue;
for (j = 0; j < array_size; j++) {
- if (band_chan_arr[j].hw_value == chspec) {
+ if (band_chan_arr[j].hw_value == wf_chspec_primary20_chspec(chspec)) {
break;
}
}
band_chan_arr[index].center_freq =
wl_channel_to_frequency(channel, CHSPEC_BAND(chspec));
#endif
- band_chan_arr[index].hw_value = chspec;
+ band_chan_arr[index].hw_value = wf_chspec_primary20_chspec(chspec);
band_chan_arr[index].beacon_found = false;
band_chan_arr[index].flags &= ~IEEE80211_CHAN_DISABLED;
/* assuming the order is HT20, HT40 Upper,
* HT40 lower from chanspecs
*/
- u32 ht40_flag = band_chan_arr[index].flags & IEEE80211_CHAN_NO_HT40;
+ u32 ht40_flag =
+ band_chan_arr[index].flags & IEEE80211_CHAN_NO_HT40;
if (CHSPEC_SB_UPPER(chspec)) {
if (ht40_flag == IEEE80211_CHAN_NO_HT40)
band_chan_arr[index].flags &=
~IEEE80211_CHAN_NO_HT40;
- band_chan_arr[index].flags |= IEEE80211_CHAN_NO_HT40PLUS;
+ band_chan_arr[index].flags |=
+ IEEE80211_CHAN_NO_HT40PLUS;
} else {
/* It should be one of
* IEEE80211_CHAN_NO_HT40 or IEEE80211_CHAN_NO_HT40PLUS
}
+ WL_CHANNEL_COPY_FLAG(__wl_2ghz_channels);
+ WL_CHANNEL_COPY_FLAG(__wl_5ghz_a_channels);
+#ifdef CFG80211_6G_SUPPORT
+ WL_CHANNEL_COPY_FLAG(__wl_6ghz_channels);
+#endif /* CFG80211_6G_SUPPORT */
+
__wl_band_2ghz.n_channels = ARRAYSIZE(__wl_2ghz_channels);
__wl_band_5ghz_a.n_channels = ARRAYSIZE(__wl_5ghz_a_channels);
#ifdef CFG80211_6G_SUPPORT
s32 err = 0;
s32 index = 0;
s32 nmode = 0;
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) || defined(CUSTOMER_HW5)
u32 j = 0;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
s32 vhtmode = 0;
s32 txstreams = 0;
s32 rxstreams = 0;
s32 stbc_tx = 0;
s32 txbf_bfe_cap = 0;
s32 txbf_bfr_cap = 0;
-#endif /* KERNEL >= 3.6 || CUSTOMER_HW5 */
- s32 bw_cap = 0;
+#endif
+ s32 txchain = 0;
+ s32 rxchain = 0;
+ s32 bw_cap_2g = 0, bw_cap_5g = 0, bw_cap_6g = 0;
s32 cur_band = -1;
struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS] = {NULL, };
+ WL_INFORM(("%s: Enter\n", __FUNCTION__));
bzero(bandlist, sizeof(bandlist));
err = wldev_ioctl_get(dev, WLC_GET_BANDLIST, bandlist,
sizeof(bandlist));
WL_ERR(("error reading nmode (%d)\n", err));
}
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) || defined(CUSTOMER_HW5)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
err = wldev_iovar_getint(dev, "vhtmode", &vhtmode);
if (unlikely(err)) {
WL_ERR(("error reading vhtmode (%d)\n", err));
WL_ERR(("error reading txbf_bfr_cap (%d)\n", err));
}
}
-#endif /* KERNEL >= 3.6 || CUSTOMER_HW5 */
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) */
+
+ err = wldev_iovar_getint(dev, "txchain", &txchain);
+ if (unlikely(err)) {
+ WL_ERR(("error reading txchain (%d)\n", err));
+ } else if (txchain == 0x03) {
+ txchain = 2;
+ } else {
+ txchain = 1;
+ }
+ err = wldev_iovar_getint(dev, "rxchain", &rxchain);
+ if (unlikely(err)) {
+ WL_ERR(("error reading rxchain (%d)\n", err));
+ } else if (rxchain == 0x03) {
+ rxchain = 2;
+ } else {
+ rxchain = 1;
+ }
/* For nmode and vhtmode check bw cap */
if (nmode ||
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) || defined(CUSTOMER_HW5)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
vhtmode ||
-#endif /* KERNEL >= 3.6 || CUSTOMER_HW5 */
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) */
0) {
- err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
+ uint32 value;
+
+ value = WLC_BAND_2G;
+ err = wldev_iovar_getint(dev, "bw_cap", &value);
+ if (unlikely(err)) {
+ WL_ERR(("error get bw_cap 2g (%d)\n", err));
+ }
+ bw_cap_2g = dtoh32(value);
+ value = WLC_BAND_5G;
+ err = wldev_iovar_getint(dev, "bw_cap", &value);
+ if (unlikely(err)) {
+ WL_ERR(("error get bw_cap 5g (%d)\n", err));
+ }
+ bw_cap_5g = dtoh32(value);
+ value = WLC_BAND_6G;
+ err = wldev_iovar_getint(dev, "bw_cap", &value);
if (unlikely(err)) {
- WL_ERR(("error get mimo_bw_cap (%d)\n", err));
+ WL_ERR(("error get bw_cap 6g (%d)\n", err));
}
+ bw_cap_6g = dtoh32(value);
}
#ifdef WL_6G_BAND
wl_is_6g_supported(cfg, bandlist, bandlist[0]);
#endif /* WL_6G_BAND */
- err = wl_construct_reginfo(cfg, bw_cap);
+ err = wl_construct_reginfo(cfg, bw_cap_2g, bw_cap_5g, bw_cap_6g);
if (err) {
WL_ERR(("wl_construct_reginfo() fails err=%d\n", err));
if (err != BCME_UNSUPPORTED)
wiphy = bcmcfg_to_wiphy(cfg);
nband = bandlist[0];
+ wiphy->available_antennas_tx = txchain;
+ wiphy->available_antennas_rx = rxchain;
+
for (i = 1; i <= nband && i < ARRAYSIZE(bandlist); i++) {
index = -1;
bands[IEEE80211_BAND_2GHZ] =
&__wl_band_2ghz;
index = IEEE80211_BAND_2GHZ;
- if (bw_cap == WLC_N_BW_40ALL)
- bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
+ (void)memset_s(bands[index]->ht_cap.mcs.rx_mask, IEEE80211_HT_MCS_MASK_LEN,
+ 0, IEEE80211_HT_MCS_MASK_LEN);
+ if (nmode && (WL_BW_CAP_40MHZ(bw_cap_2g))) {
+ bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
+ IEEE80211_HT_CAP_SGI_40;
+ bands[index]->ht_cap.mcs.rx_mask[4] = 0x01;
+ bands[index]->ht_cap.mcs.rx_highest =
+ cpu_to_le16(150 * rxchain); /* Mbps */
+ } else {
+ bands[index]->ht_cap.mcs.rx_highest =
+ cpu_to_le16(72 * rxchain); /* Mbps */
+ }
} else {
if (bandlist[i] == WLC_BAND_6G) {
#ifdef CFG80211_6G_SUPPORT
continue;
}
- if (nmode && (bw_cap == WLC_N_BW_40ALL || bw_cap == WLC_N_BW_20IN2G_40IN5G))
- bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
+ (void)memset_s(bands[index]->ht_cap.mcs.rx_mask, IEEE80211_HT_MCS_MASK_LEN,
+ 0, IEEE80211_HT_MCS_MASK_LEN);
+ if (nmode && (WL_BW_CAP_40MHZ(bw_cap_5g))) {
+ bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
+ IEEE80211_HT_CAP_SGI_40;
+ bands[index]->ht_cap.mcs.rx_mask[4] = 0x01;
+ bands[index]->ht_cap.mcs.rx_highest = cpu_to_le16(150 * rxchain);
+ } else {
+ bands[index]->ht_cap.mcs.rx_highest = cpu_to_le16(72 * rxchain);
+ }
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) || defined(CUSTOMER_HW5)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
/* VHT capabilities. */
if (vhtmode) {
/* Supported */
bands[index]->vht_cap.vht_supported = TRUE;
+ bands[index]->vht_cap.vht_mcs.tx_highest =
+ cpu_to_le16(433 * txstreams); /* Mbps */
+ bands[index]->vht_cap.vht_mcs.rx_highest =
+ cpu_to_le16(433 * txstreams); /* Mbps */
for (j = 1; j <= VHT_CAP_MCS_MAP_NSS_MAX; j++) {
/* TX stream rates. */
}
/* Capabilities */
+ bands[index]->vht_cap.cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN
+ | IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
/* 80 MHz is mandatory */
bands[index]->vht_cap.cap |=
IEEE80211_VHT_CAP_SHORT_GI_80;
- if (WL_BW_CAP_160MHZ(bw_cap)) {
+ if (WL_BW_CAP_160MHZ(bw_cap_5g)) {
bands[index]->vht_cap.cap |=
IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
bands[index]->vht_cap.cap |=
bands[index]->vht_cap.vht_mcs.rx_mcs_map,
bands[index]->vht_cap.vht_mcs.tx_mcs_map));
}
-#endif /* KERNEL >= 3.6 || CUSTOMER_HW5 */
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) */
}
if ((index >= 0) && nmode) {
bands[index]->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
bands[index]->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
/* An HT shall support all EQM rates for one spatial stream */
- bands[index]->ht_cap.mcs.rx_mask[0] = 0xff;
+ for (j = 0; j < rxchain; j++) {
+ bands[index]->ht_cap.mcs.rx_mask[j] = 0xff;
+ }
+ bands[index]->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
}
}
struct wireless_dev *wdev = ndev->ieee80211_ptr;
struct cfg80211_bss *bss = CFG80211_GET_BSS(wiphy, NULL, latest_bssid,
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
- wdev->u.client.ssid, wdev->u.client.ssid_len
+ wdev->u.client.ssid, wdev->u.client.ssid_len);
#else
- wdev->ssid, wdev->ssid_len
-#endif
- );
+ wdev->ssid, wdev->ssid_len);
+#endif /* CFG80211_BKPORT_MLO */
BCM_REFERENCE(bss);
while (ie) {
if (count >= MAX_VNDR_IE_NUMBER)
break;
- if (ie->id == DOT11_MNG_VS_ID || (ie->id == DOT11_MNG_ID_EXT_ID)) {
+#ifdef HOSTAPD_EID_EXTENSION_SUPPORT
+ if (ie->id == DOT11_MNG_VS_ID || (ie->id == DOT11_MNG_ID_EXT_ID))
+#else
+ if (ie->id == DOT11_MNG_VS_ID)
+#endif
+ {
vndrie = (const vndr_ie_t *) ie;
if (ie->id == DOT11_MNG_ID_EXT_ID) {
/* len should be bigger than sizeof ID extn field at least */
return 0;
}
+#ifdef GET_FW_IE_DATA
+static void
+wl_dump_ie_buf(vndr_ie_buf_t *ie_getbuf)
+{
+ uchar *iebuf;
+ uchar *data;
+ int tot_ie, pktflag, iecount, datalen;
+ vndr_ie_info_t *ie_info;
+ vndr_ie_t *ie;
+
+ memcpy(&tot_ie, (void *)&ie_getbuf->iecount, sizeof(int));
+ tot_ie = dtoh32(tot_ie);
+ iebuf = (uchar *)&ie_getbuf->vndr_ie_list[0];
+
+ printf("-----------------\n");
+ printf("Total IEs %d\n", tot_ie);
+ for (iecount = 0; iecount < tot_ie; iecount++) {
+ ie_info = (vndr_ie_info_t *) iebuf;
+ memcpy(&pktflag, (void *)&ie_info->pktflag, sizeof(uint32));
+ pktflag = dtoh32(pktflag);
+ iebuf += sizeof(uint32);
+ ie = &ie_info->vndr_ie_data;
+ data = &ie->data[0];
+ datalen = ie->len - VNDR_IE_MIN_LEN;
+ printf("index=%d, pktflag=0x%x\n", iecount, pktflag);
+ prhex("IE", (u8 *)ie, ie->len+VNDR_IE_HDR_LEN);
+
+ iebuf += ie->len + VNDR_IE_HDR_LEN;
+ }
+ printf("-----------------\n");
+ printf("\n");
+}
+#endif /* GET_FW_IE_DATA */
+
static void
wl_print_fw_ie_data(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx)
{
bssidx, &cfg->ioctl_buf_sync);
if (ret == BCME_OK) {
ies = (vndr_ie_buf_t *)cfg->ioctl_buf;
- WL_INFORM_MEM(("FW IE count:%d\n", ies->iecount));
#ifdef GET_FW_IE_DATA
- if (wl_dbg_level & WL_DBG_DBG) {
- int i = 0;
- /* If debug enabled, print each IE */
- for (i = 0; i < ies->iecount; i++) {
- vndr_ie_info_t *info = &ies->vndr_ie_list[i];
- WL_DBG_MEM(("pktflag:0x%x\n", info->pktflag));
- prhex("IE:", (u8 *)&info->vndr_ie_data,
- info->vndr_ie_data.len + TLV_HDR_LEN);
- }
- }
+ wl_dump_ie_buf((vndr_ie_buf_t *)cfg->ioctl_buf);
+#else
+ WL_MSG(ndev->name, "FW IE count:%d\n", ies->iecount);
#endif /* GET_FW_IE_DATA */
} else {
WL_ERR(("IE retrieval failed! ret:%d\n", ret));
u32 parsed_ie_buf_len = 0;
struct parsed_vndr_ies old_vndr_ies;
struct parsed_vndr_ies new_vndr_ies;
+ int del_add_cnt = 0;
s32 i;
u8 *ptr;
s32 remained_buf_len;
curr_ie_buf += del_add_ie_buf_len;
total_ie_buf_len += del_add_ie_buf_len;
+ del_add_cnt++;
}
}
*mgmt_ie_len += vndrie_info->ie_len;
curr_ie_buf += del_add_ie_buf_len;
total_ie_buf_len += del_add_ie_buf_len;
+ del_add_cnt++;
}
}
if (total_ie_buf_len && cfg->ioctl_buf != NULL) {
- ret = wldev_iovar_setbuf_bsscfg(ndev, "vndr_ie", g_mgmt_ie_buf,
+#ifdef VNDR_IE_WAR
+ curr_ie_buf = g_mgmt_ie_buf;
+ for (i=0; i<del_add_cnt; i++) {
+ vndr_ie_setbuf_t *vndr_ie_setbuf = (vndr_ie_setbuf_t *)curr_ie_buf;
+ u32 curr_ie_buf_len;
+ curr_ie_buf_len =
+ (u8*)&vndr_ie_setbuf->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[0] -
+ (u8*)vndr_ie_setbuf;
+ curr_ie_buf_len += vndr_ie_setbuf->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len;
+ ret = wldev_iovar_setbuf_bsscfg(ndev, "vndr_ie", curr_ie_buf,
+ curr_ie_buf_len, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
+ bssidx, &cfg->ioctl_buf_sync);
+ if (ret)
+ break;
+ curr_ie_buf += curr_ie_buf_len;
+ }
+#else
+ ret = wldev_iovar_setbuf_bsscfg(ndev, "vndr_ie", g_mgmt_ie_buf,
total_ie_buf_len, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
bssidx, &cfg->ioctl_buf_sync);
+#endif
if (ret) {
WL_ERR(("vndr_ie set error :%d\n", ret));
if (ret == BCME_NOTFOUND) {
} \
} while (0)
+#define WL_CHANNEL_COPY_FLAG(band_chan_arr) \
+do { \
+ u32 arr_size, k; \
+ arr_size = ARRAYSIZE(band_chan_arr); \
+ for (k = 0; k < arr_size; k++) { \
+ band_chan_arr[k].orig_flags = band_chan_arr[k].flags; \
+ } \
+} while (0)
+
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
#define CFG80211_PUT_BSS(wiphy, bss) cfg80211_put_bss(wiphy, bss);
#else
cca_congest_ext_channel_req_v2_t *per_chspec_stats = NULL;
uint per_chspec_stats_size = 0;
cca_congest_ext_channel_req_v3_t *all_chan_results;
- cca_congest_ext_channel_req_v3_t all_chan_req;
+ cca_congest_ext_channel_req_v3_t *all_chan_req = NULL;
+ uint all_chan_req_size = sizeof(cca_congest_ext_channel_req_v3_t);
#else
/* cca_get_stats_ext iovar for Wifi channel statics */
struct cca_congest_ext_channel_req_v2 *cca_v2_results;
- struct cca_congest_ext_channel_req_v2 cca_v2_req;
+ struct cca_congest_ext_channel_req_v2 *cca_v2_req = NULL;
+ uint cca_v2_req_size = sizeof(cca_congest_ext_channel_req_v2_t);
#endif /* CHAN_STATS_SUPPORT */
const wl_cnt_wlc_t *wlc_cnt;
scb_val_t scbval;
#ifdef CHAN_STATS_SUPPORT
/* Option to get all channel statistics */
- all_chan_req.num_of_entries = 0;
- all_chan_req.ver = WL_CCA_EXT_REQ_VER_V3;
+ all_chan_req = (void *)MALLOCZ(cfg->osh, all_chan_req_size);
+ if (all_chan_req == NULL) {
+ err = BCME_NOMEM;
+ WL_ERR(("all_chan_req alloc failed\n"));
+ goto exit;
+ }
+ all_chan_req->num_of_entries = 0;
+ all_chan_req->ver = WL_CCA_EXT_REQ_VER_V3;
err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cca_get_stats_ext",
- &all_chan_req, sizeof(all_chan_req), iovar_buf, WLC_IOCTL_MAXLEN, NULL);
+ all_chan_req, all_chan_req_size, iovar_buf, WLC_IOCTL_MAXLEN, NULL);
if (err != BCME_OK && err != BCME_UNSUPPORTED) {
WL_ERR(("cca_get_stats_ext iovar err = %d\n", err));
}
}
#else
- cca_v2_req.ver = WL_CCA_EXT_REQ_VER_V2;
- cca_v2_req.chanspec =
+ cca_v2_req = (void *)MALLOCZ(cfg->osh, cca_v2_req_size);
+ if (cca_v2_req == NULL) {
+ err = BCME_NOMEM;
+ WL_ERR(("cca_v2_req alloc failed\n"));
+ goto exit;
+ }
+ cca_v2_req->ver = WL_CCA_EXT_REQ_VER_V2;
+ cca_v2_req->chanspec =
wl_chspec_host_to_driver(wf_chspec_primary20_chspec(cur_chanspec));
- err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cca_get_stats_ext", &cca_v2_req,
- sizeof(cca_v2_req), iovar_buf, WLC_IOCTL_MAXLEN, NULL);
+ err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cca_get_stats_ext", cca_v2_req,
+ cca_v2_req_size, iovar_buf, WLC_IOCTL_MAXLEN, NULL);
if (err != BCME_OK && err != BCME_UNSUPPORTED) {
WL_ERR(("cca_get_stats_ext iovar err = %d\n", err));
WL_ERR(("Vendor Command reply failed ret:%d \n", err));
exit:
+#ifdef CHAN_STATS_SUPPORT
+ if (all_chan_req) {
+ MFREE(cfg->osh, all_chan_req, all_chan_req_size);
+ }
+#else
+ if (cca_v2_req) {
+ MFREE(cfg->osh, cca_v2_req, cca_v2_req_size);
+ }
+#endif /* CHAN_STATS_SUPPORT */
if (outdata) {
MFREE(cfg->osh, outdata, WLC_IOCTL_MAXLEN);
}
* role to station type while bringing down the interface
*/
if (p2p_ndev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION) {
- WL_DBG_MEM(("%s, Change to GC base role\n", __FUNCTION__));
+ WL_DBG_MEM(("%s, Change to GC base role\n", p2p_ndev->name));
return WL_IF_TYPE_P2P_GC;
}
WL_DBG(("%s:Mac addr" MACDBG "\n",
__FUNCTION__, MAC2STRDBG(mac_addr)));
+#if defined(SPECIFIC_MAC_GEN_SCHEME)
if ((wl_iftype == WL_IF_TYPE_P2P_DISC) || (wl_iftype == WL_IF_TYPE_AP) ||
(wl_iftype == WL_IF_TYPE_P2P_GO) || (wl_iftype == WL_IF_TYPE_P2P_GC)) {
/* Avoid invoking release mac addr code for interfaces using
*/
return BCME_OK;
}
+#else
+ if (wl_iftype == WL_IF_TYPE_P2P_DISC) {
+ return BCME_OK;
+ }
+#endif /* SPECIFIC_MAC_GEN_SCHEME */
/* Fetch last two bytes of mac address */
org_toggle_bytes = ntoh16(*((u16 *)&ndev->dev_addr[4]));
* released. Ensure to call wl_release_vif_macaddress to free up
* the mac address.
*/
-#if defined (SPECIFIC_MAC_GEN_SCHEME)
+#if defined(SPECIFIC_MAC_GEN_SCHEME)
if (wl_iftype == WL_IF_TYPE_P2P_DISC || wl_iftype == WL_IF_TYPE_AP) {
mac_addr[0] |= 0x02;
} else if ((wl_iftype == WL_IF_TYPE_P2P_GO) || (wl_iftype == WL_IF_TYPE_P2P_GC)) {
if (wl_iftype == WL_IF_TYPE_P2P_DISC) {
mac_addr[0] |= 0x02;
}
-#endif /* SEPCIFIC_MAC_GEN_SCHEME */
+#endif /* SPECIFIC_MAC_GEN_SCHEME */
else {
/* For locally administered mac addresses, we keep the
* OUI part constant and just work on the last two bytes.
if (is_p2p_group_iface(ndev->ieee80211_ptr) && (type == NL80211_IFTYPE_STATION)) {
/* For role downgrade cases, we keep interface role as GC */
netinfo->iftype = WL_IF_TYPE_P2P_GC;
- WL_DBG_MEM(("[%s] Set base role to GC, current role"
+ WL_DBG_MEM(("[%s] Set base role to GC, current role"
"ndev->ieee80211_ptr->iftype = %d\n",
- __FUNCTION__, ndev->ieee80211_ptr->iftype));
+ ndev->name, ndev->ieee80211_ptr->iftype));
} else {
netinfo->iftype = wl_iftype;
}
s32
wl_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
struct ieee80211_channel *chan,
- enum nl80211_channel_type channel_type)
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+ enum nl80211_channel_type channel_type
+#else
+ enum nl80211_chan_width width
+#endif
+)
{
chanspec_t chspec = INVCHANSPEC;
chanspec_t cur_chspec = INVCHANSPEC;
- u32 bw = WL_CHANSPEC_BW_20;
+ u32 band_width = WL_CHANSPEC_BW_20, bw = WL_CHANSPEC_BW_20;
s32 err = BCME_OK;
struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
#if defined(CUSTOM_SET_CPUCORE) || defined(APSTA_RESTRICTED_CHANNEL)
u16 center_freq = chan->center_freq;
dev = ndev_to_wlc_ndev(dev, cfg);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+ switch (channel_type) {
+ case NL80211_CHAN_HT40MINUS:
+ /* secondary channel is below the control channel */
+ band_width = WL_CHANSPEC_BW_40;
+ break;
+ case NL80211_CHAN_HT40PLUS:
+ /* secondary channel is above the control channel */
+ band_width = WL_CHANSPEC_BW_40;
+ break;
+ default:
+ band_width = WL_CHANSPEC_BW_20;
+ }
+#else
+ switch (width)
+ {
+ case NL80211_CHAN_WIDTH_160:
+ band_width = WL_CHANSPEC_BW_160;
+ break;
+ case NL80211_CHAN_WIDTH_80P80:
+ case NL80211_CHAN_WIDTH_80:
+ band_width = WL_CHANSPEC_BW_80;
+ break;
+ case NL80211_CHAN_WIDTH_40:
+ band_width = WL_CHANSPEC_BW_40;
+ break;
+ default:
+ band_width = WL_CHANSPEC_BW_20;
+ break;
+ }
+#endif
+
#ifdef WL_EXT_IAPSTA
if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP ||
dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
#endif
chspec = wl_freq_to_chanspec(center_freq);
- WL_MSG(dev->name, "netdev_ifidx(%d) chan_type(%d) target channel(%s-%d %sMHz)\n",
- dev->ifindex, channel_type, CHSPEC2BANDSTR(chspec),
- CHSPEC_CHANNEL(chspec), wf_chspec_to_bw_str(chspec));
+ WL_MSG(dev->name, "netdev_ifidx(%d) chan_width(%d) target channel(%s-%d %sMHz)\n",
+ dev->ifindex, width, CHSPEC2BANDSTR(chspec),
+ CHSPEC_CHANNEL(chspec), WLCWIDTH2STR(band_width));
#ifdef WL_P2P_6G
if (!(cfg->p2p_6g_enabled)) {
}
#endif /* WL_P2P_6G */
-#ifdef NOT_YET
- switch (channel_type) {
- case NL80211_CHAN_HT40MINUS:
- /* secondary channel is below the control channel */
- chspec = CH40MHZ_CHSPEC(CHSPEC_CHANNEL(chspec), WL_CHANSPEC_CTL_SB_UPPER);
- break;
- case NL80211_CHAN_HT40PLUS:
- /* secondary channel is above the control channel */
- chspec = CH40MHZ_CHSPEC(CHSPEC_CHANNEL(chspec), WL_CHANSPEC_CTL_SB_LOWER);
- break;
- default:
- chspec = CH20MHZ_CHSPEC(CHSPEC_CHANNEL(chspec));
-
- }
-#endif /* NOT_YET */
-
#if defined(APSTA_RESTRICTED_CHANNEL)
/* Some customer platform used limited number of channels
* for SoftAP interface on STA/SoftAP concurrent mode.
if (err < 0) {
WL_ERR(("Failed to get bandwidth information, err=%d\n", err));
return err;
+ } else if (bw < band_width) {
+ WL_ERR(("capability force band_width=0x%X to be 0x%X\n", band_width, bw));
+ band_width = bw;
}
+#ifdef HOSTAPD_BW_SUPPORT
+ WL_MSG(dev->name, "hostapd bw(%sMHz) <= chip bw(%sMHz)\n",
+ wf_chspec_to_bw_str(band_width), wf_chspec_to_bw_str(bw));
+#else
+ WL_MSG(dev->name, "hostapd bw(%sMHz) => chip bw(%sMHz)\n",
+ wf_chspec_to_bw_str(band_width), wf_chspec_to_bw_str(bw));
+ band_width = bw;
+#endif
/* In case of 5G downgrade BW to 80MHz as 160MHz channels falls in DFS */
if (CHSPEC_IS5G(chspec) && (bw == WL_CHANSPEC_BW_160)) {
}
set_channel:
cur_chspec = wf_create_chspec_from_primary(wf_chspec_primary20_chan(chspec),
- bw, CHSPEC_BAND(chspec));
+ band_width, CHSPEC_BAND(chspec));
#ifdef WL_6G_BAND
if (cfg->acs_chspec &&
CHSPEC_IS6G(cfg->acs_chspec) &&
dev->ieee80211_ptr->u.ap.preset_chandef.chan,
#else
dev->ieee80211_ptr->preset_chandef.chan,
-#endif
- NL80211_CHAN_HT20) < 0)) {
+#endif /* CFG80211_BKPORT_MLO */
+ info->chandef.width) < 0)) {
WL_ERR(("Set channel failed \n"));
goto fail;
}
wl_cfg80211_stop_ap(wiphy, dev, 0);
#else
wl_cfg80211_stop_ap(wiphy, dev);
-#endif
+#endif /* CFG80211_BKPORT_MLO */
if (dev_role == NL80211_IFTYPE_AP) {
#ifdef WL_EXT_IAPSTA
if (!wl_ext_iapsta_iftype_enabled(dev, WL_IF_TYPE_AP)) {
struct net_device *dev
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 2) || defined(CFG80211_BKPORT_MLO)
, unsigned int link_id
-#endif
+#endif /* CFG80211_BKPORT_MLO */
)
{
int err = 0;
cfg80211_ch_switch_notify(dev, &chandef, 0);
#else
cfg80211_ch_switch_notify(dev, &chandef);
-#endif
+#endif /* CFG80211_BKPORT_MLO */
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
freq = chandef.freq;
cfg80211_ch_switch_notify(dev, freq, chandef.chan_type);
s32
wl_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
struct ieee80211_channel *chan,
- enum nl80211_channel_type channel_type);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+ enum nl80211_channel_type channel_type
+#else
+ enum nl80211_chan_width width
+#endif
+);
#endif /* ((LINUX_VERSION < VERSION(3, 6, 0)) || WL_COMPAT_WIRELESS */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
defined(WL_COMPAT_WIRELESS)
unsigned int link_id);
#else
extern s32 wl_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *dev);
-#endif
+#endif /* CFG80211_BKPORT_MLO */
extern s32 wl_cfg80211_change_beacon(struct wiphy *wiphy, struct net_device *dev,
struct cfg80211_beacon_data *info);
#else
u8 *scan_params = NULL, *params = NULL;
s32 params_size;
u32 n_channels = 0;
- wl_uint32_list_t *list;
- u8 valid_chan_list[sizeof(u32)*(MAX_CTRL_CHANSPECS + 1)];
+ wl_uint32_list_t *list = NULL;
mutex_lock(&escan->usr_sync);
if (escan->escan_state == ESCAN_STATE_DOWN) {
}
/* if scan request is not empty parse scan request paramters */
- memset(valid_chan_list, 0, sizeof(valid_chan_list));
- list = (wl_uint32_list_t *)(void *) valid_chan_list;
+ list = kzalloc(sizeof(u32)*(MAX_CTRL_CHANSPECS + 1), GFP_KERNEL);
+ if (list == NULL) {
+ ESCAN_ERROR(dev->name, "kzalloc failed\n");
+ err = -ENOMEM;
+ goto exit;
+ }
if (scan_info->channels.count) {
memcpy(list, &scan_info->channels, sizeof(wl_channel_list_t));
}
kfree(params);
exit:
+ if (list)
+ kfree(list);
if (unlikely(err)) {
wl_escan_reset(escan);
}
ENC_TKIPAES
} encmode_t;
+typedef enum MAPSTA_MODE {
+ MCHAN_APSTA_NOT_ALLOW = 0,
+ MCHAN_APSTA_SBSC,
+ MCHAN_APSTA_NO_RESTRICT
+} mapsta_mode_t;
+
#ifdef STA_MGMT
typedef struct wl_sta_info {
int ifidx;
#endif /* WL_EXT_RECONNECT && WL_CFG80211 */
} wl_if_info_t;
+u8 *g_ioctl_buf = NULL;
+
typedef struct wl_apsta_params {
struct wl_if_info if_info[MAX_IF_NUM];
#ifdef WLDWDS
struct wl_dwds_info dwds_info[MAX_DWDS_IF_NUM];
#endif /* WLDWDS */
- u8 *ioctl_buf;
bool init;
int rsdb;
bool vsdb;
if (!auto_chan) {
auto_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
cur_chan_info->band);
+ auto_chan = wf_chspec_ctlchan(auto_chan);
}
if (auto_chan)
cur_chan_info->chan = auto_chan;
if (!auto_chan) {
auto_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
cur_chan_info->band);
+ auto_chan = wf_chspec_ctlchan(auto_chan);
}
if (auto_chan) {
cur_chan_info->chan = auto_chan;
} else {
auto_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
cur_chan_info->band);
+ auto_chan = wf_chspec_ctlchan(auto_chan);
if (auto_chan) {
cur_chan_info->chan = auto_chan;
}
if (!auto_chan) {
auto_chan = wl_ext_autochannel(tgt_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
tgt_chan_info->band);
+ auto_chan = wf_chspec_ctlchan(auto_chan);
}
if (auto_chan) {
tgt_chan_info->chan = auto_chan;
if (!auto_chan) {
auto_chan = wl_ext_autochannel(tgt_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
tgt_chan_info->band);
+ auto_chan = wf_chspec_ctlchan(auto_chan);
}
} else {
tgt_chan_info->chan = 0;
if (wl_ext_master_if(cur_if) && apsta_params->acs) {
chan_info->chan = wl_ext_autochannel(cur_if->dev, apsta_params->acs,
chan_info->band);
+ chan_info->chan = wf_chspec_ctlchan(chan_info->chan);
}
chan_info->chan = wl_ext_move_cur_channel(apsta_params, cur_if);
if (chan_info->chan) {
}
}
} else {
- WL_ERR(("Unknown auth_alg=%d or auth_seq=%d\n", auth_alg, auth_seq));
+ IAPSTA_ERROR(dev->name, "Unknown auth_alg=%d or auth_seq=%d\n",
+ auth_alg, auth_seq);
}
return;
static void
wl_ampdu_dump(struct net_device *dev)
{
- struct dhd_pub *dhd = dhd_get_pub(dev);
- struct wl_apsta_params *apsta_params = dhd->iapsta_params;
- char *ioctl_buf = apsta_params->ioctl_buf, *buf = NULL;
+ char *ioctl_buf = g_ioctl_buf, *buf = NULL;
char *tx_pch_start, *tx_pch_end, *rx_pch_start, *rx_pch_end;
int ret = 0, max_len, tx_len, rx_len;
if (!(android_msg_level & ANDROID_AMPDU_LEVEL))
return;
- if (!ioctl_buf)
- return;
-
memset(ioctl_buf, 0, WL_DUMP_BUF_LEN);
ret = bcm_mkiovar("dump", "ampdu", strlen("ampdu"), ioctl_buf, WL_DUMP_BUF_LEN);
if (ret == 0) {
static void
wl_tvpm_dump(struct net_device *dev)
{
- struct dhd_pub *dhd = dhd_get_pub(dev);
- struct wl_apsta_params *apsta_params = dhd->iapsta_params;
wl_tvpm_req_t* tvpm_req = NULL;
size_t reqlen = sizeof(wl_tvpm_req_t) + sizeof(wl_tvpm_status_t);
- uint8 *outbuf = apsta_params->ioctl_buf;
+ uint8 *outbuf = g_ioctl_buf;
size_t outlen = WLC_IOCTL_MEDLEN;
wl_tvpm_status_t* status;
int ret, phy_temp = 0;
wldev_ioctl(dev, WLC_GET_RSSI, &scb_val, sizeof(scb_val_t), 0);
rssi_ant_p->count = 1;
rssi_ant_p->rssi_ant[0] = dtoh32(scb_val.val);
+ } else {
+ rssi_ant_p->count = 0;
}
}
for (i=0; i<rssi_ant_p->count && rssi_ant_p->rssi_ant[i]; i++) {
static void
wl_sta_info_dump(struct net_device *dev, struct ether_addr *mac)
{
- struct dhd_pub *dhd = dhd_get_pub(dev);
- struct wl_apsta_params *apsta_params = dhd->iapsta_params;
- void *buf = apsta_params->ioctl_buf;
+ void *buf = g_ioctl_buf;
sta_info_v4_t *sta = NULL;
char rssi_buf[16];
int ret;
tmp_if = &apsta_params->if_info[i];
if (tmp_if->dev &&
(tmp_if->ifmode == ISTA_MODE || tmp_if->ifmode == IGC_MODE) &&
- wl_ext_associated(tmp_if->dev)) {
+ wl_get_isam_status(tmp_if, STA_CONNECTED)) {
wl_tput_monitor(dhd, tmp_if->ifidx, &tmp_if->tput_info);
monitor_if[i] = TRUE;
}
{
struct dhd_pub *dhd = dhd_get_pub(cur_if->dev);
struct wl_apsta_params *apsta_params = dhd->iapsta_params;
- char *iovar_buf = apsta_params->ioctl_buf;
+ char *iovar_buf = g_ioctl_buf;
uint32 corerev = 0;
wl_cnt_info_t *cntinfo;
uint16 ver;
(chan_5g && cur_if->chan_info.band == WLC_BAND_5G)) {
cur_if->chan_info.chan = wl_ext_autochannel(cur_if->dev, apsta_params->acs,
cur_if->chan_info.band);
+ cur_if->chan_info.chan = wf_chspec_ctlchan(cur_if->chan_info.chan);
} else {
IAPSTA_ERROR(ifname, "invalid channel\n");
ret = -1;
return rsdb;
}
+static void
+wl_ext_iapsta_get_mapsta_mode(struct net_device *net)
+{
+ struct dhd_pub *dhd = dhd_get_pub(net);
+ struct wl_apsta_params *apsta_params = dhd->iapsta_params;
+ int ret, mapsta_mode;
+
+ ret = wldev_iovar_getint(net, "mapsta_mode", &mapsta_mode);
+ if (ret) {
+ IAPSTA_INFO(net->name, "not supported %d\n", ret);
+ mapsta_mode = MCHAN_APSTA_NOT_ALLOW;
+ }
+
+ if (mapsta_mode == MCHAN_APSTA_SBSC)
+ apsta_params->rsdb = 1;
+ else if (mapsta_mode == MCHAN_APSTA_NO_RESTRICT)
+ apsta_params->vsdb = TRUE;
+
+ IAPSTA_INFO(net->name, "mapsta_mode=%d(rsdb=%d, vsdb=%d)\n",
+ mapsta_mode, apsta_params->rsdb, apsta_params->vsdb);
+}
+
static void
wl_ext_iapsta_postinit(struct net_device *net, struct wl_if_info *cur_if)
{
if (cur_if->ifidx == 0) {
apsta_params->rsdb = wl_ext_iapsta_get_rsdb(net, dhd);
apsta_params->vsdb = FALSE;
+ wl_ext_iapsta_get_mapsta_mode(net);
apsta_params->csa = 0;
apsta_params->acs = 0;
apsta_params->radar = wl_ext_radar_detect(net);
struct dhd_pub *dhd = dhd_get_pub(net);
struct wl_apsta_params *apsta_params = dhd->iapsta_params;
- if (!apsta_params->ioctl_buf) {
- apsta_params->ioctl_buf = kmalloc(WL_DUMP_BUF_LEN, GFP_KERNEL);
- if (unlikely(!apsta_params->ioctl_buf)) {
- IAPSTA_ERROR(net->name, "Can not allocate ioctl_buf\n");
- }
- }
init_waitqueue_head(&apsta_params->netif_change_event);
mutex_init(&apsta_params->usr_sync);
mutex_init(&apsta_params->in4way_sync);
struct dhd_pub *dhd = dhd_get_pub(net);
struct wl_apsta_params *apsta_params = dhd->iapsta_params;
- if (apsta_params->ioctl_buf) {
- kfree(apsta_params->ioctl_buf);
- apsta_params->ioctl_buf = NULL;
- }
memset(apsta_params, 0, sizeof(struct wl_apsta_params));
}
return 0;
}
-int
-wl_ext_iapsta_attach(struct net_device *net)
+void
+wl_ext_iapsta_dettach(struct net_device *net)
{
struct dhd_pub *dhd = dhd_get_pub(net);
- struct wl_apsta_params *iapsta_params;
IAPSTA_TRACE(net->name, "Enter\n");
- iapsta_params = kzalloc(sizeof(struct wl_apsta_params), GFP_KERNEL);
- if (unlikely(!iapsta_params)) {
- IAPSTA_ERROR(net->name, "Can not allocate apsta_params\n");
- return -ENOMEM;
+ if (g_ioctl_buf) {
+ kfree(g_ioctl_buf);
+ g_ioctl_buf = NULL;
}
- dhd->iapsta_params = (void *)iapsta_params;
- return 0;
+ if (dhd->iapsta_params) {
+ wl_ext_iapsta_deinit_priv(net);
+ kfree(dhd->iapsta_params);
+ dhd->iapsta_params = NULL;
+ }
}
-void
-wl_ext_iapsta_dettach(struct net_device *net)
+int
+wl_ext_iapsta_attach(struct net_device *net)
{
struct dhd_pub *dhd = dhd_get_pub(net);
+ struct wl_apsta_params *iapsta_params;
+ int ret = 0;
IAPSTA_TRACE(net->name, "Enter\n");
- if (dhd->iapsta_params) {
- wl_ext_iapsta_deinit_priv(net);
- kfree(dhd->iapsta_params);
- dhd->iapsta_params = NULL;
+ iapsta_params = kzalloc(sizeof(struct wl_apsta_params), GFP_KERNEL);
+ if (unlikely(!iapsta_params)) {
+ IAPSTA_ERROR(net->name, "Can not allocate apsta_params\n");
+ ret = -ENOMEM;
+ goto exit;
}
+ dhd->iapsta_params = (void *)iapsta_params;
+
+ if (!g_ioctl_buf) {
+ g_ioctl_buf = kmalloc(WL_DUMP_BUF_LEN, GFP_KERNEL);
+ if (unlikely(!g_ioctl_buf)) {
+ IAPSTA_ERROR(net->name, "Can not allocate g_ioctl_buf\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
+ }
+
+exit:
+ if (ret)
+ wl_ext_iapsta_dettach(net);
+ return ret;
}
#endif /* WL_EXT_IAPSTA */
struct dhd_pub *dhd = dhd_get_pub(dev);
struct iw_freq *fwrq = &wrqu->freq;
int error;
+ u32 val;
chanspec_t chanspec = 0;
int ctl_chan;
WL_TRACE(("%s: SIOCGIWFREQ\n", dev->name));
DHD_CHECK(dhd, dev);
- if ((error = dev_wlc_intvar_get(dev, "chanspec", (s32 *)&chanspec)))
+ if ((error = dev_wlc_intvar_get(dev, "chanspec", &val)))
return error;
+ chanspec = val;
chanspec = wl_ext_chspec_driver_to_host(dhd, chanspec);
ctl_chan = wf_chspec_ctlchan(chanspec);
struct dhd_pub *dhd = dhd_get_pub(dev);
wlc_ssid_t ssid;
#ifdef WL_ESCAN
- wl_scan_info_t scan_info;
+ wl_scan_info_t *scan_info = NULL;
+ int err;
#else
wl_wext_info_t *wext_info = NULL;
iscan_info_t *iscan;
}
}
#endif
- memset(&scan_info, 0, sizeof(wl_scan_info_t));
- scan_info.bcast_ssid = TRUE;
- memcpy(scan_info.ssid.SSID, ssid.SSID, ssid.SSID_len);
- scan_info.ssid.SSID_len = ssid.SSID_len;
- return wl_escan_set_scan(dev, &scan_info);
+ scan_info = kmalloc(sizeof(wl_scan_info_t), GFP_KERNEL);
+ if (scan_info == NULL) {
+ WL_ERROR(("kzalloc failed\n"));
+ return -ENOMEM;
+ }
+ memset(scan_info, 0, sizeof(wl_scan_info_t));
+ scan_info->bcast_ssid = TRUE;
+ memcpy(scan_info->ssid.SSID, ssid.SSID, ssid.SSID_len);
+ scan_info->ssid.SSID_len = ssid.SSID_len;
+ err = wl_escan_set_scan(dev, scan_info);
+ kfree(scan_info);
+ return err;
#else
wext_info = dhd->wext_info;
iscan = &wext_info->iscan;
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_dhd-driver.git / commitdiff