ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC

Now, the clock/reset controller driver is available for this SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index 5f57a96e4e133e861466387df78ce44c256a907c..a75189f7d8fe68aa089e7bbefe8f81d14576db69 100644 (file)
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -242,6 +242,9 @@
                        status = "disabled";
                        reg = <0x5a800100 0x100>;
                        interrupts = <0 80 4>;
+                       clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+                       resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+                                <&mio_rst 12>;
                };
 
                usb1: usb@5a810100 {
@@ -249,6 +252,9 @@
                        status = "disabled";
                        reg = <0x5a810100 0x100>;
                        interrupts = <0 81 4>;
+                       clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+                       resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+                                <&mio_rst 13>;
                };
 
                usb2: usb@5a820100 {
@@ -256,6 +262,9 @@
                        status = "disabled";
                        reg = <0x5a820100 0x100>;
                        interrupts = <0 82 4>;
+                       clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+                       resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+                                <&mio_rst 14>;
                };
 
                usb3: usb@5a830100 {
@@ -263,6 +272,9 @@
                        status = "disabled";
                        reg = <0x5a830100 0x100>;
                        interrupts = <0 83 4>;
+                       clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
+                       resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
+                                <&mio_rst 15>;
                };
 
                sysctrl@f1840000 {