printk("gpu: %s, %s, %d\n", __FILE__, __func__, __LINE__);
}
+int mali_reset_info(struct platform_device *pdev, struct device_node *gpu_dn,
+ struct mali_plat_info_t *mpdata)
+{
+ struct device_node *reset_dn, *apb_reset_dn;
+ int ret = 0;
+
+ reset_dn = of_get_child_by_name(gpu_dn, "reset_cfg");
+ if (!reset_dn) {
+ mpdata->reset_flag = 0;
+ dev_info(&pdev->dev, "no reset_cfg\n");
+ } else {
+ ret = of_property_read_u32(reset_dn,"reg_level",
+ &mpdata->module_reset.reg_level);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_level for reset\n");
+ return -ENOMEM;
+ }
+ ret = of_property_read_u32(reset_dn,"reg_mask",
+ &mpdata->module_reset.reg_mask);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_mask for reset\n");
+ return -ENOMEM;
+ }
+ ret = of_property_read_u32(reset_dn,"reg_bit",
+ &mpdata->module_reset.reg_bit);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_bit for reset\n");
+ return -ENOMEM;
+ }
+ mpdata->reset_flag = 1;
+ }
+ apb_reset_dn = of_get_child_by_name(gpu_dn, "capb_reset");
+ if (!apb_reset_dn) {
+ mpdata->reset_flag = 0;
+ dev_info(&pdev->dev, "no apb_reset\n");
+ } else {
+ ret = of_property_read_u32(apb_reset_dn,"reg_level",
+ &mpdata->apb_reset.reg_level);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_level for apb_reset\n");
+ return -ENOMEM;
+ }
+ ret = of_property_read_u32(apb_reset_dn,"reg_mask",
+ &mpdata->apb_reset.reg_mask);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_mask for apb_reset\n");
+ return -ENOMEM;
+ }
+ ret = of_property_read_u32(apb_reset_dn,"reg_bit",
+ &mpdata->apb_reset.reg_bit);
+ if (ret) {
+ dev_err(&pdev->dev, "no reg_bit for apb_reset\n");
+ return -ENOMEM;
+ }
+ mpdata->reset_flag = 1;
+ }
+ return ret;
+}
+
int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
{
struct device_node *gpu_dn = pdev->dev.of_node;
return -ENOMEM;
}
clk_sample = mpdata->clk_sample;
+ /* mali external reset reg */
+ ret = mali_reset_info(pdev, gpu_dn, mpdata);
+ if (ret)
+ return ret;
+ /* dvfs clk table */
of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) {
dvfs_clk_hdl = (phandle) u;
gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl);
#ifdef CONFIG_MALI_DEVFREQ
static unsigned long t83x_static_power(unsigned long voltage)
{
-#if 0
- struct thermal_zone_device *tz;
- unsigned long temperature, temp;
- unsigned long temp_squared, temp_cubed, temp_scaling_factor;
- const unsigned long coefficient = (410UL << 20) / (729000000UL >> 10);
- const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
-
- tz = thermal_zone_get_zone_by_name("gpu");
- if (IS_ERR(tz)) {
- pr_warn_ratelimited("Error getting gpu thermal zone (%ld), not yet ready?\n",
- PTR_ERR(tz));
- temperature = FALLBACK_STATIC_TEMPERATURE;
- } else {
- int ret;
-
- ret = tz->ops->get_temp(tz, &temperature);
- if (ret) {
- pr_warn_ratelimited("Error reading temperature for gpu thermal zone: %d\n",
- ret);
- temperature = FALLBACK_STATIC_TEMPERATURE;
- }
- }
-
- /* Calculate the temperature scaling factor. To be applied to the
- * voltage scaled power.
- */
- temp = temperature / 1000;
- temp_squared = temp * temp;
- temp_cubed = temp_squared * temp;
- temp_scaling_factor =
- (2 * temp_cubed)
- - (80 * temp_squared)
- + (4700 * temp)
- + 32000;
-
- return (((coefficient * voltage_cubed) >> 20)
- * temp_scaling_factor)
- / 1000000;
-#else
return 0;
-#endif
}
static unsigned long t83x_dynamic_power(unsigned long freq,
+++ /dev/null
-/*
- * mali_kbase_meson.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <mali_kbase.h>
-#include "mali_kbase_meson.h"
-
-int meson_gpu_reset(struct kbase_device *kbdev)
-{
- struct meson_context *platform = kbdev->platform_context;
- void __iomem *reg_base_reset = platform->reg_base_reset;
- u32 value;
-
- //JOHNT
- // Level reset mail
-
- // Level reset mail
- //writel(~(0x1<<14), reg_base_reset + P_RESET2_MASK * 4);
- //writel(~(0x1<<14), reg_base_reset + P_RESET2_LEVEL * 4);
-
- //writel(0xffffffff, reg_base_reset + P_RESET2_LEVEL * 4);
- //writel(0xffffffff, reg_base_reset + P_RESET0_LEVEL * 4);
-
- MESON_PRINT("%s, %d\n", __func__, __LINE__);
- MESON_PRINT("reg_base=%p, reset0=%p\n", reg_base_reset, reg_base_reset + RESET0_MASK * 4);
- udelay(100);
-#if 0
- value = readl(reg_base_reset + RESET0_REGISTER * 4);
- MESON_PRINT("line(%d), RESET0_REGISTER=%x\n", __LINE__, value);
-#endif
-
- udelay(100);
- MESON_PRINT("%s, %d\n", __func__, __LINE__);
- value = readl(reg_base_reset + RESET0_MASK * 4);
- value = value & (~(0x1<<20));
- writel(value, reg_base_reset + RESET0_MASK * 4);
-
- udelay(100);
-#if 0
- value = readl(reg_base_reset + RESET0_REGISTER * 4);
- MESON_PRINT("line(%d), RESET0_REGISTER=%x\n", __LINE__, value);
- udelay(100);
-#endif
-
- value = readl(reg_base_reset + RESET0_LEVEL * 4);
- value = value & (~(0x1<<20));
- //MESON_PRINT("line(%d), value=%x\n", __LINE__, value);
- writel(value, reg_base_reset + RESET0_LEVEL * 4);
- udelay(100);
-
-#if 0
- value = readl(reg_base_reset + RESET0_REGISTER * 4);
- MESON_PRINT("line(%d), RESET0_REGISTER=%x\n", __LINE__, value);
- udelay(100);
-#endif
-
-///////////////
-#if 0
- value = readl(reg_base_reset + RESET2_REGISTER * 4);
- MESON_PRINT("line(%d), RESET2_REGISTER=%x\n", __LINE__, value);
-#endif
-
- udelay(100);
- value = readl(reg_base_reset + RESET2_MASK * 4);
- value = value & (~(0x1<<14));
- //MESON_PRINT("line(%d), value=%x\n", __LINE__, value);
- writel(value, reg_base_reset + RESET2_MASK * 4);
-
-#if 0
- value = readl(reg_base_reset + RESET2_REGISTER * 4);
- MESON_PRINT("line(%d), RESET2_REGISTER=%x\n", __LINE__, value);
-#endif
-
- value = readl(reg_base_reset + RESET2_LEVEL * 4);
- value = value & (~(0x1<<14));
- //MESON_PRINT("line(%d), value=%x\n", __LINE__, value);
- writel(value, reg_base_reset + RESET2_LEVEL * 4);
- udelay(100);
-
-#if 0
- value = readl(reg_base_reset + RESET2_REGISTER * 4);
- MESON_PRINT("line(%d), RESET2_REGISTER=%x\n", __LINE__, value);
-#endif
-
- udelay(100);
- value = readl(reg_base_reset + RESET0_LEVEL * 4);
- value = value | ((0x1<<20));
- //MESON_PRINT("line(%d), value=%x\n", __LINE__, value);
- writel(value, reg_base_reset + RESET0_LEVEL * 4);
-#if 0
- value = readl(reg_base_reset + RESET2_REGISTER * 4);
- MESON_PRINT("line(%d), RESET2_REGISTER=%x\n", __LINE__, value);
-#endif
-
- udelay(100);
- value = readl(reg_base_reset + RESET2_LEVEL * 4);
- value = value | ((0x1<<14));
- //MESON_PRINT("line(%d), value=%x\n", __LINE__, value);
- writel(value, reg_base_reset + RESET2_LEVEL * 4);
-#if 0
- value = readl(reg_base_reset + RESET2_REGISTER * 4);
- MESON_PRINT("line(%d), RESET2_REGISTER=%x\n", __LINE__, value);
-#endif
-
- udelay(10); // OR POLL for reset done
-
- return 0;
-}
-
-void meson_gpu_pwr_on(struct kbase_device *kbdev, u32 mask)
-{
- u32 part1_done = 0;
- u32 value = 0;
- u32 count = 0;
-
- kbdev->pm.backend.gpu_powered = true;
- MESON_PRINT("%s, %d begin\n", __func__,__LINE__);
-
-#if 0
- value = 0x10 | (0x1<<16);
-#else
- value = 0xfff | (0x20<<16);
-#endif
- while (part1_done != value) {
- Mali_WrReg(GPU_CONTROL_REG(PWR_KEY), 0x2968A819);
- Mali_WrReg(GPU_CONTROL_REG(PWR_OVERRIDE1), value);
- part1_done = Mali_RdReg(GPU_CONTROL_REG(PWR_OVERRIDE1));
- MESON_PRINT("write again, count=%d, overrider1=%x\n", count, part1_done);
- udelay(20);
- count ++;
- if (0 == (count %100)) MESON_PRINT("write again, count%d\n", count);
- }
- part1_done = Mali_RdReg(GPU_CONTROL_REG(PWR_OVERRIDE1));
- MESON_PRINT("write again, count=%d, overrider1=%x\n", count, part1_done);
-
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
-
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- if ((mask & 0x1) != 0 ) {
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- Mali_WrReg(0x00000190, 0xffffffff); // Power on all cores
- Mali_WrReg(0x00000194, 0xffffffff); // Power on all cores
- Mali_WrReg(0x000001a0, 0xffffffff); // Power on all cores
- Mali_WrReg(0x000001a4, 0xffffffff); // Power on all cores
- }
- MESON_PRINT("power on %d\n", __LINE__);
-
- if ( (mask >> 1) != 0 ) {
- Mali_WrReg(0x00000180, mask >> 1); // Power on all cores
- Mali_WrReg(0x00000184, 0x0); // Power on all cores
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- }
-
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- if ( mask != 0 ) {
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- udelay(10);
- part1_done = Mali_RdReg(0x0000020);
- while(part1_done ==0) {
- part1_done = Mali_RdReg(0x00000020);
- udelay(10);
- }
-
- MESON_PRINT("%s, %d\n", __func__,__LINE__);
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
- }
- MESON_PRINT("%s, %d end\n", __func__,__LINE__);
-}
-
-void meson_gpu_pwr_off(struct kbase_device *kbdev, u32 mask)
-{
-#if 1
- u32 part1_done;
- part1_done = 0;
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
-
- if ( (mask >> 1) != 0 ) {
- Mali_WrReg(0x000001C0, mask >> 1); // Power off all cores
- Mali_WrReg(0x000001C4, 0x0); // Power off all cores
- }
-
- if ( (mask & 0x1) != 0 ) {
- Mali_WrReg(0x000001D0, 0xffffffff); // Power off all cores
- Mali_WrReg(0x000001D4, 0xffffffff); // Power off all cores
- Mali_WrReg(0x000001E0, 0xffffffff); // Power off all cores
- Mali_WrReg(0x000001E4, 0xffffffff); // Power off all cores
- }
-
- if ( mask != 0 ) {
- part1_done = Mali_RdReg(0x0000020);
- while((part1_done ==0)) { part1_done = Mali_RdReg(0x00000020); }
- MESON_PRINT("Mali_pwr_off:gpu_irq : %x\n", part1_done);
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
- }
-#endif
-}
-
-
-
-
-static int kbase_platform_meson_init(struct kbase_device *kbdev)
-{
-#if 0
- int err;
-#endif
- struct device_node *gpu_dn = kbdev->dev->of_node;
-#ifdef CONFIG_MALI_MIDGARD_DVFS
- unsigned long flags;
-#endif /* CONFIG_MALI_MIDGARD_DVFS */
- struct meson_context *platform;
- u32 part1_done = 0;
-
- platform = kmalloc(sizeof(struct meson_context), GFP_KERNEL);
-
- if (!platform)
- return -ENOMEM;
-
- memset(platform, 0, sizeof(struct meson_context));
-
- kbdev->platform_context = (void *) platform;
-
- platform->reg_base_reset = of_iomap(gpu_dn, 1);
- _dev_info(kbdev->dev, "reset io source 0x%p\n",platform->reg_base_reset);
-
- platform->reg_base_aobus = of_iomap(gpu_dn, 2);
- _dev_info(kbdev->dev, "ao io source 0x%p\n", platform->reg_base_aobus);
-
- platform->reg_base_hiubus = of_iomap(gpu_dn, 3);
- _dev_info(kbdev->dev, "hiu io source 0x%p\n", platform->reg_base_hiubus);
-
- platform->clk_mali = devm_clk_get(kbdev->dev, "gpu_mux");
- if (IS_ERR(platform->clk_mali)) {
- dev_err(kbdev->dev, "failed to get clock pointer\n");
- } else {
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
- clk_prepare_enable(platform->clk_mali);
- clk_set_rate(platform->clk_mali, 285000000);
-#else
- clk_set_rate(platform->clk_mali, 285000000);
- clk_prepare_enable(platform->clk_mali);
-#endif
- }
- MESON_PRINT("%s, %d begin\n", __func__, __LINE__);
- meson_gpu_reset(kbdev);
- meson_gpu_pwr_on(kbdev, 0xe);
-
- part1_done = Mali_RdReg(GPU_CONTROL_REG(PWR_OVERRIDE1));
- MESON_PRINT("line%d, overrider1=%x\n", __LINE__, part1_done);
- meson_gpu_pwr_off(kbdev, 0xe);
-#if 1
- part1_done = Mali_RdReg(GPU_CONTROL_REG(PWR_OVERRIDE1));
- MESON_PRINT("line%d, overrider1=%x\n", __LINE__, part1_done);
-
- meson_gpu_reset(kbdev);
- meson_gpu_pwr_on(kbdev, 0xe);
- part1_done = Mali_RdReg(GPU_CONTROL_REG(PWR_OVERRIDE1));
- MESON_PRINT("line%d, overrider1=%x\n", __LINE__, part1_done);
-#endif
-#if 0
- platform->cmu_pmu_status = 0;
- platform->dvfs_wq = NULL;
- platform->polling_speed = 100;
- gpu_debug_level = DVFS_WARNING;
-#endif
-
- mutex_init(&platform->gpu_clock_lock);
- mutex_init(&platform->gpu_dvfs_handler_lock);
- spin_lock_init(&platform->gpu_dvfs_spinlock);
-#if 0
- err = gpu_control_module_init(kbdev);
- if (err)
- goto clock_init_fail;
-
- /* dvfs gobernor init*/
- gpu_dvfs_governor_init(kbdev, G3D_DVFS_GOVERNOR_DEFAULT);
-#endif
-#ifdef CONFIG_MALI_MIDGARD_DVFS
- spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags);
- platform->wakeup_lock = 0;
- spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags);
-#endif /* CONFIG_MALI_MIDGARD_DVFS */
-#if 0
- /* dvfs handler init*/
- gpu_dvfs_handler_init(kbdev);
-
- err = gpu_notifier_init(kbdev);
- if (err)
- goto notifier_init_fail;
-
- err = gpu_create_sysfs_file(kbdev->dev);
- if (err)
- goto sysfs_init_fail;
-#endif
-
- MESON_PRINT("%s, %d end\n", __func__, __LINE__);
- return 0;
-#if 0
-clock_init_fail:
-notifier_init_fail:
-sysfs_init_fail:
- kfree(platform);
-
- return err;
-#endif
-}
-
-/**
- ** Meson hardware specific termination
- **/
-static void kbase_platform_meson_term(struct kbase_device *kbdev)
-{
- struct meson_context *platform;
- platform = (struct meson_context *) kbdev->platform_context;
-#if 0
- gpu_notifier_term();
-
-#ifdef CONFIG_MALI_MIDGARD_DVFS
- gpu_dvfs_handler_deinit(kbdev);
-#endif /* CONFIG_MALI_MIDGARD_DVFS */
-
- gpu_control_module_term(kbdev);
-#endif
-
- kfree(kbdev->platform_context);
- kbdev->platform_context = 0;
-
-#if 0
- gpu_remove_sysfs_file(kbdev->dev);
-#endif
-}
-
-struct kbase_platform_funcs_conf platform_funcs = {
- .platform_init_func = &kbase_platform_meson_init,
- .platform_term_func = &kbase_platform_meson_term,
-};
-
+++ /dev/null
-/*
- * mali_kbase_meson.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/clk-provider.h>
-#include <linux/clk.h>
-
-#define RESET0_MASK 0x00
-#define RESET1_MASK 0x01
-#define RESET2_MASK 0x02
-
-#define RESET0_LEVEL 0x10
-#define RESET1_LEVEL 0x11
-#define RESET2_LEVEL 0x12
-
-#define Mali_WrReg(regnum, value) writel((value),(kbdev->reg + (regnum)))
-#define Mali_RdReg(regnum) readl(kbdev->reg + (regnum))
-#define MESON_PRINT(...)
-
-struct meson_context {
- struct mutex gpu_clock_lock;
- struct mutex gpu_dvfs_handler_lock;
- spinlock_t gpu_dvfs_spinlock;
-#ifdef CONFIG_MALI_MIDGARD_DVFS
- int utilization;
- int util_gl_share;
- int util_cl_share[2];
-#ifdef CONFIG_CPU_THERMAL_IPA
- int norm_utilisation;
- int freq_for_normalisation;
- unsigned long long power;
-#endif /* CONFIG_CPU_THERMAL_IPA */
- int max_lock;
- int min_lock;
-#if 0
- int user_max_lock[NUMBER_LOCK];
- int user_min_lock[NUMBER_LOCK];
-#endif
- int target_lock_type;
- int down_requirement;
- bool wakeup_lock;
- int governor_num;
- int governor_type;
- char governor_list[100];
- bool dvfs_status;
-#ifdef CONFIG_CPU_THERMAL_IPA
- int time_tick;
- u32 time_busy;
- u32 time_idle;
-#endif /* CONFIG_CPU_THERMAL_IPA */
-#endif
- int cur_clock;
- int cur_voltage;
- int voltage_margin;
- bool tmu_status;
- int debug_level;
- int polling_speed;
- struct workqueue_struct *dvfs_wq;
- void __iomem *reg_base_reset;
- void __iomem *reg_base_aobus;
- void __iomem *reg_base_hiubus;
- struct clk *clk_mali;
- struct clk *clk_gp;
-};
-
#include <linux/io.h>
#include <backend/gpu/mali_kbase_device_internal.h>
#include "mali_kbase_config_platform.h"
-
#include "mali_scaling.h"
static void enable_gpu_power_control(struct kbase_device *kbdev)
{
-#if 0
- unsigned int i;
-
-#if defined(CONFIG_REGULATOR)
- for (i = 0; i < kbdev->nr_regulators; i++) {
- if (WARN_ON(kbdev->regulators[i] == NULL))
- ;
- else if (!regulator_is_enabled(kbdev->regulators[i]))
- WARN_ON(regulator_enable(kbdev->regulators[i]));
- }
-
- for (i = 0; i < kbdev->nr_clocks; i++) {
- if ((NULL != kbdev->clocks[i]) && (!__clk_is_enabled(kbdev->clocks[i])))
- clk_prepare_enable(kbdev->clocks[i]);
- }
-#endif
-#endif
}
static void disable_gpu_power_control(struct kbase_device *kbdev)
{
-#if 0
- unsigned int i;
-
- for (i = 0; i < kbdev->nr_clocks; i++) {
- if ((NULL != kbdev->clocks[i]) && __clk_is_enabled(kbdev->clocks[i])) {
- clk_disable_unprepare(kbdev->clocks[i]);
- }
-
- }
-
-#if defined(CONFIG_REGULATOR)
- for (i = 0; i < kbdev->nr_regulators; i++) {
- if (WARN_ON(kbdev->regulators[i] == NULL))
- ;
- else if (regulator_is_enabled(kbdev->regulators[i]))
- WARN_ON(regulator_disable(kbdev->regulators[i]));
- }
-#endif
-#endif
}
+void *reg_base_reset = NULL;
static int first = 1;
//remove this if sc2 worked fine.
extern u64 kbase_pm_get_ready_cores(struct kbase_device *kbdev, enum kbase_pm_core_type type);
//[0]:CG [1]:SC0 [2]:SC2
-static void Mali_pwr_on_with_kdev ( struct kbase_device *kbdev, uint32_t mask)
+static void Mali_pwr_on_with_kdev( struct kbase_device *kbdev, uint32_t mask)
{
- uint32_t part1_done;
- uint32_t shader_present;
- uint32_t tiler_present;
- uint32_t l2_present;
-
- part1_done = 0;
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
-
- shader_present = Mali_RdReg(0x100);
- tiler_present = Mali_RdReg(0x110);
- l2_present = Mali_RdReg(0x120);
- printk("shader_present=%d, tiler_present=%d, l2_present=%d\n",
- shader_present, tiler_present, l2_present);
-
- if ( mask == 0 ) {
- Mali_WrReg(0x00000180, 0xffffffff); // Power on all cores (shader low)
- Mali_WrReg(0x00000184, 0xffffffff); // Power on all cores (shader high)
- Mali_WrReg(0x00000190, 0xffffffff); // Power on all cores (tiler low)
- Mali_WrReg(0x00000194, 0xffffffff); // Power on all cores (tiler high)
- Mali_WrReg(0x000001a0, 0xffffffff); // Power on all cores (l2 low)
- Mali_WrReg(0x000001a4, 0xffffffff); // Power on all cores (l2 high)
- } else {
- Mali_WrReg(0x00000180, mask); // Power on all cores (shader low)
- Mali_WrReg(0x00000184, 0); // Power on all cores (shader high)
- Mali_WrReg(0x00000190, mask); // Power on all cores (tiler low)
- Mali_WrReg(0x00000194, 0); // Power on all cores (tiler high)
- Mali_WrReg(0x000001a0, mask); // Power on all cores (l2 low)
- Mali_WrReg(0x000001a4, 0); // Power on all cores (l2 high)
- }
-
- part1_done = Mali_RdReg(0x0000020);
- while (0 == part1_done) { part1_done = Mali_RdReg(0x00000020); }
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
-}
+ uint32_t part1_done;
+ uint32_t shader_present;
+ uint32_t tiler_present;
+ uint32_t l2_present;
+
+ part1_done = 0;
+ Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
+
+ shader_present = Mali_RdReg(0x100);
+ tiler_present = Mali_RdReg(0x110);
+ l2_present = Mali_RdReg(0x120);
+ dev_info(kbdev->dev, "shader_present=%d, tiler_present=%d, l2_present=%d\n",
+ shader_present, tiler_present, l2_present);
+
+ if ( mask == 0 ) {
+ Mali_WrReg(0x00000180, 0xffffffff); // Power on all cores (shader low)
+ Mali_WrReg(0x00000184, 0xffffffff); // Power on all cores (shader high)
+ Mali_WrReg(0x00000190, 0xffffffff); // Power on all cores (tiler low)
+ Mali_WrReg(0x00000194, 0xffffffff); // Power on all cores (tiler high)
+ Mali_WrReg(0x000001a0, 0xffffffff); // Power on all cores (l2 low)
+ Mali_WrReg(0x000001a4, 0xffffffff); // Power on all cores (l2 high)
+ } else {
+ Mali_WrReg(0x00000180, mask); // Power on all cores (shader low)
+ Mali_WrReg(0x00000184, 0); // Power on all cores (shader high)
+ Mali_WrReg(0x00000190, mask); // Power on all cores (tiler low)
+ Mali_WrReg(0x00000194, 0); // Power on all cores (tiler high)
+ Mali_WrReg(0x000001a0, mask); // Power on all cores (l2 low)
+ Mali_WrReg(0x000001a4, 0); // Power on all cores (l2 high)
+ }
-//[0]:CG [1]:SC0 [2]:SC2
-#if 0
-static void Mali_pwr_off_with_kdev( struct kbase_device *kbdev, uint32_t mask)
-{
- uint32_t part1_done;
- part1_done = 0;
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
-
- if ( mask == 0 ) {
- Mali_WrReg(0x000001C0, 0xffffffff); // Power off all cores (tiler low)
- Mali_WrReg(0x000001C4, 0xffffffff); // Power off all cores (tiler high)
- Mali_WrReg(0x000001D0, 0xffffffff); // Power off all cores (l2 low)
- Mali_WrReg(0x000001D4, 0xffffffff); // Power off all cores (l2 high)
- Mali_WrReg(0x000001E0, 0xffffffff); // Power off all cores (shader low)
- Mali_WrReg(0x000001E4, 0xffffffff); // Power off all cores (shader high)
- } else {
- Mali_WrReg(0x000001C0, mask); // Power off all cores (tiler low)
- Mali_WrReg(0x000001C4, 0x0); // Power off all cores (tiler high)
- Mali_WrReg(0x000001D0, mask); // Power off all cores (l2 low)
- Mali_WrReg(0x000001D4, 0x0); // Power off all cores (l2 high)
- Mali_WrReg(0x000001E0, mask); // Power off all cores (shader low)
- Mali_WrReg(0x000001E4, 0x0); // Power off all cores (shader high)
- }
-
- part1_done = Mali_RdReg(0x0000020);
- while((part1_done ==0)) { part1_done = Mali_RdReg(0x00000020); }
- Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
+ part1_done = Mali_RdReg(0x0000020);
+ while (0 == part1_done) { part1_done = Mali_RdReg(0x00000020); }
+ Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
}
-#endif
-static int pm_callback_power_on(struct kbase_device *kbdev)
+/*reset function before t7 by register*/
+static void mali_reset_v0(int reset_g12a)
{
- int ret = 1; /* Assume GPU has been powered off */
- int error;
-#if 1
- //remove this if sc2 worked fine.
- struct mali_plat_info_t *mpdata = (struct mali_plat_info_t *) kbdev->platform_context;
- void *reg_base_reset = mpdata->reg_base_reset;
u32 value;
- int reset_g12a = mpdata->reset_g12a;
-#endif
-
- if (first == 0) goto out;
-
- first = 0;
if (reset_g12a) {
value = Rd(RESET0_MASK);
value = value & (~(0x1<<20));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET0_MASK, value);
value = Rd(RESET0_LEVEL);
value = value & (~(0x1<<20));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET0_LEVEL, value);
- ///////////////
+
value = Rd(RESET2_MASK);
value = value & (~(0x1<<14));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET2_MASK, value);
value = Rd(RESET2_LEVEL);
value = value & (~(0x1<<14));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET2_LEVEL, value);
value = Rd(RESET0_LEVEL);
value = value | ((0x1<<20));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET0_LEVEL, value);
value = Rd(RESET2_LEVEL);
value = value | ((0x1<<14));
- //printk("line(%d), value=%x\n", __LINE__, value);
Wr(RESET2_LEVEL, value);
} else {
- //JOHNT
- //remove this if sc2 worked fine.
+ /* JOHNT: remove this if sc2 worked fine. */
value = ~(1 << 2);
- dev_dbg(kbdev->dev, "line(%d),mask ~(1<<14)\n", __LINE__);
Wr(RESETCTRL_RESET1_MASK, value);
- dev_dbg(kbdev->dev, "line(%d),level ~(1<<14)\n", __LINE__);
Wr(RESETCTRL_RESET1_LEVEL, value);
- dev_dbg(kbdev->dev, "line(%d),level 0xFFFFFFFF\n", __LINE__);
Wr(RESETCTRL_RESET1_LEVEL, 0xFFFFFFFF);
}
- udelay(10); // OR POLL for reset done
- dev_dbg(kbdev->dev, "delay 10us\n");
+}
- Mali_WrReg(GPU_CONTROL_REG(PWR_KEY), 0x2968A819);
- Mali_WrReg(GPU_CONTROL_REG(PWR_OVERRIDE1), 0xfff | (0x20<<16));
- Mali_pwr_on_with_kdev(kbdev, 0x1);
- dev_dbg(kbdev->dev, "pm_callback_power_on %p\n",
- (void *)kbdev->dev->pm_domain);
+/*
+ * reset note:
+ * there have mali reset and mali_capb bus reset.
+ * reset step:[vlsi suggestion]
+ * step1. mali-reset and mali-capb-reset level and mask config to 0
+ * step2. mali-reset and mali-capb-reset level config to 1
+ * Todo: sync old ic similar with t7,reset reg config by dts
+ */
+static void mali_reset(void)
+{
+ mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ u32 value = 0;
+ int reset_g12a = pmali_plat->reset_g12a;
- enable_gpu_power_control(kbdev);
+ if (!pmali_plat->reset_flag) {
+ mali_reset_v0(reset_g12a);
+ return;
+ }
-out:
+ /*
+ * for t7 , if old ic also sync with the follow method,
+ * need sync the dts similar with T7
+ */
+ value = Rd(pmali_plat->module_reset.reg_mask);
+ value = value & (~(0x1<<pmali_plat->module_reset.reg_bit));
+ Wr(pmali_plat->module_reset.reg_mask, value);
+
+ value = Rd(pmali_plat->module_reset.reg_level);
+ value = value & (~(0x1<<pmali_plat->module_reset.reg_bit));
+ Wr(pmali_plat->module_reset.reg_level, value);
+
+ value = Rd(pmali_plat->apb_reset.reg_mask);
+ value = value & (~(0x1<<pmali_plat->apb_reset.reg_bit));
+ Wr(pmali_plat->apb_reset.reg_mask, value);
+
+ value = Rd(pmali_plat->apb_reset.reg_level);
+ value = value & (~(0x1<<pmali_plat->apb_reset.reg_bit));
+ Wr(pmali_plat->apb_reset.reg_level, value);
+
+ value = Rd(pmali_plat->apb_reset.reg_level);
+ value = value | ((0x1<<pmali_plat->apb_reset.reg_bit));
+ Wr(pmali_plat->apb_reset.reg_level, value);
+
+ value = Rd(pmali_plat->module_reset.reg_level);
+ value = value | ((0x1<<pmali_plat->module_reset.reg_bit));
+ Wr(pmali_plat->module_reset.reg_level, value);
+}
+
+static int pm_callback_power_on(struct kbase_device *kbdev)
+{
+ int ret = 1; /* Assume GPU has been powered off */
+ int error;
+
+ /* remove this if sc2 worked fine. */
+ struct mali_plat_info_t *mpdata = (struct mali_plat_info_t *) kbdev->platform_context;
+ reg_base_reset = mpdata->reg_base_reset;
+
+
+ if (first == 0) goto out;
+ pm_runtime_enable(kbdev->dev);
error = pm_runtime_get_sync(kbdev->dev);
if (error == 1) {
/*
ret = 0;
}
udelay(100);
+ dev_info(kbdev->dev, "pm_runtime_get_sync returned %d\n", error);
+ first = 0;
+
+ mali_reset();
+ udelay(10); // OR POLL for reset done
+ dev_dbg(kbdev->dev, "delay 10us\n");
+
+ Mali_WrReg(GPU_CONTROL_REG(PWR_KEY), 0x2968A819);
+ Mali_WrReg(GPU_CONTROL_REG(PWR_OVERRIDE1), 0xfff | (0x20<<16));
+ Mali_pwr_on_with_kdev(kbdev, 0x1);
+ dev_dbg(kbdev->dev, "pm_callback_power_on %p\n",
+ (void *)kbdev->dev->pm_domain);
+
+ enable_gpu_power_control(kbdev);
+out:
return ret;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
dev_dbg(kbdev->dev, "pm_callback_power_off\n");
- //printk("%s, %d\n", __FILE__, __LINE__);
- pm_runtime_mark_last_busy(kbdev->dev);
- pm_runtime_put_autosuspend(kbdev->dev);
+ /*
+ * the pm_runtime is no use for ic before t7,
+ * todo: add dynamic switch power on/off for t7 with external top gpu power domain
+ */
+ //pm_runtime_mark_last_busy(kbdev->dev);
+ //pm_runtime_put_autosuspend(kbdev->dev);
#ifndef KBASE_PM_RUNTIME
- disable_gpu_power_control(kbdev);
+ //disable_gpu_power_control(kbdev);
#endif
}
{
int ret = 0;
- dev_dbg(kbdev->dev, "kbase_device_runtime_init\n");
-
pm_runtime_set_autosuspend_delay(kbdev->dev, AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(kbdev->dev);
pm_runtime_set_active(kbdev->dev);
-
dev_dbg(kbdev->dev, "kbase_device_runtime_init\n");
pm_runtime_enable(kbdev->dev);
uint32_t keep_count;
uint32_t downthreshold;
uint32_t upthreshold;
- uint32_t clk_freq;
- const char *clk_parent;
- struct clk *clkp_handle;
- uint32_t clkp_freq;
+ uint32_t clk_freq;
+ const char *clk_parent;
+ struct clk *clkp_handle;
+ uint32_t clkp_freq;
} mali_dvfs_threshold_table;
/**
u32 maxclk;
} mali_scale_info_t;
+typedef struct mali_reset_info_t {
+ u32 reg_level;
+ u32 reg_mask;
+ u32 reg_bit;
+} mali_reset_info_t;
+
/**
* Platform spesific data for meson chips.
*/
u32 maxclk_sysfs;
u32 maxpp_sysfs;
+ /* mali external reset reg info */
+ u32 reset_flag;
+ mali_reset_info_t module_reset;
+ mali_reset_info_t apb_reset;
+
/* set upper limit of pp or frequency, for THERMAL thermal or band width saving.*/
u32 limit_on;
/* for boost up gpu by user. */
void (*plat_preheat)(void);
- struct platform_device *pdev;
- void __iomem *reg_base_hiubus;
- void __iomem *reg_base_aobus;
+ struct platform_device *pdev;
+ void __iomem *reg_base_hiubus;
+ void __iomem *reg_base_aobus;
struct work_struct wq_work;
- struct clk *clk_mali;
- struct clk *clk_mali_0;
- struct clk *clk_mali_1;
- void __iomem *reg_base_reset;
- u32 clk_cntl_reg;
- s32 reset_g12a;
+ struct clk *clk_mali;
+ struct clk *clk_mali_0;
+ struct clk *clk_mali_1;
+ void __iomem *reg_base_reset;
+ u32 clk_cntl_reg;
+ s32 reset_g12a;
} mali_plat_info_t;
mali_plat_info_t* get_mali_plat_data(void);
#include <asm/io.h>
#endif
-//#include <mali_kbase.h>
+#include <mali_kbase.h>
+#include <mali_kbase_defs.h>
+
#include "meson_main2.h"
int meson_gpu_data_invalid_count = 0;
int meson_gpu_fault = 0;
+extern u64 kbase_pm_get_ready_cores(struct kbase_device *kbdev, enum kbase_pm_core_type type);
static ssize_t domain_stat_read(struct class *class,
struct class_attribute *attr, char *buf)
{
unsigned int val;
+ u64 core_ready;
mali_plat_info_t* pmali_plat = get_mali_plat_data();
+ struct platform_device* ptr_plt_dev = pmali_plat->pdev;
+ struct kbase_device *kbdev = dev_get_drvdata(&ptr_plt_dev->dev);
- val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
- return sprintf(buf, "%x\n", val>>4);
- return 0;
+ core_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_SHADER);
+ val = core_ready;
+ return sprintf(buf, "%x\n", val);
}
#define PREHEAT_CMD "preheat"
+++ /dev/null
-#
-# (C) COPYRIGHT 2012-2017 ARM Limited. All rights reserved.
-#
-# This program is free software and is provided to you under the terms of the
-# GNU General Public License version 2 as published by the Free Software
-# Foundation, and any use by you of this program is subject to the terms
-# of such GNU licence.
-#
-# A copy of the licence is included with the program, and can also be obtained
-# from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
-# Boston, MA 02110-1301, USA.
-#
-#
-
-
-mali_kbase-y += \
- $(MALI_PLATFORM_DIR)/mali_kbase_config_devicetree.o \
- $(MALI_PLATFORM_DIR)/mali_kbase_runtime_pm.o
+++ /dev/null
-/*
- *
- * (C) COPYRIGHT 2015, 2017 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained
- * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- *
- */
-
-
-
-#include <mali_kbase_config.h>
-
-int kbase_platform_early_init(void)
-{
- /* Nothing needed at this stage */
- return 0;
-}
-
-static struct kbase_platform_config dummy_platform_config;
-
-struct kbase_platform_config *kbase_get_platform_config(void)
-{
- return &dummy_platform_config;
-}
-
-#ifndef CONFIG_OF
-int kbase_platform_register(void)
-{
- return 0;
-}
-
-void kbase_platform_unregister(void)
-{
-}
-#endif
+++ /dev/null
-/*
- *
- * (C) COPYRIGHT 2015, 2017, 2019 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU licence.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can access it online at
- * http://www.gnu.org/licenses/gpl-2.0.html.
- *
- * SPDX-License-Identifier: GPL-2.0
- *
- */
-
-#include <mali_kbase_config.h>
-
-static struct kbase_platform_config dummy_platform_config;
-
-struct kbase_platform_config *kbase_get_platform_config(void)
-{
- return &dummy_platform_config;
-}
-
-#ifndef CONFIG_OF
-int kbase_platform_register(void)
-{
- return 0;
-}
-
-void kbase_platform_unregister(void)
-{
-}
-#endif
+++ /dev/null
-/*
- *
- * (C) COPYRIGHT 2014-2017 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained
- * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- *
- */
-
-
-
-/**
- * Maximum frequency GPU will be clocked at. Given in kHz.
- * This must be specified as there is no default value.
- *
- * Attached value: number in kHz
- * Default value: NA
- */
-#define GPU_FREQ_KHZ_MAX (5000)
-/**
- * Minimum frequency GPU will be clocked at. Given in kHz.
- * This must be specified as there is no default value.
- *
- * Attached value: number in kHz
- * Default value: NA
- */
-#define GPU_FREQ_KHZ_MIN (5000)
-
-/**
- * CPU_SPEED_FUNC - A pointer to a function that calculates the CPU clock
- *
- * CPU clock speed of the platform is in MHz - see kbase_cpu_clk_speed_func
- * for the function prototype.
- *
- * Attached value: A kbase_cpu_clk_speed_func.
- * Default Value: NA
- */
-#define CPU_SPEED_FUNC (NULL)
-
-/**
- * GPU_SPEED_FUNC - A pointer to a function that calculates the GPU clock
- *
- * GPU clock speed of the platform in MHz - see kbase_gpu_clk_speed_func
- * for the function prototype.
- *
- * Attached value: A kbase_gpu_clk_speed_func.
- * Default Value: NA
- */
-#define GPU_SPEED_FUNC (NULL)
-
-/**
- * Power management configuration
- *
- * Attached value: pointer to @ref kbase_pm_callback_conf
- * Default value: See @ref kbase_pm_callback_conf
- */
-#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks)
-
-/**
- * Platform specific configuration functions
- *
- * Attached value: pointer to @ref kbase_platform_funcs_conf
- * Default value: See @ref kbase_platform_funcs_conf
- */
-#define PLATFORM_FUNCS (NULL)
-
-extern struct kbase_pm_callback_conf pm_callbacks;
-
-/**
- * Autosuspend delay
- *
- * The delay time (in milliseconds) to be used for autosuspend
- */
-#define AUTO_SUSPEND_DELAY (100)
+++ /dev/null
-/*
- *
- * (C) COPYRIGHT 2015, 2017 ARM Limited. All rights reserved.
- *
- * This program is free software and is provided to you under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation, and any use by you of this program is subject to the terms
- * of such GNU licence.
- *
- * A copy of the licence is included with the program, and can also be obtained
- * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- *
- */
-
-
-
-#include <mali_kbase.h>
-#include <mali_kbase_defs.h>
-#include <linux/pm_runtime.h>
-#include "mali_kbase_config_platform.h"
-
-inline int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation,
- u32 util_gl_share, u32 util_cl_share[2])
-{
- return 1;
-}
-
-static int pm_callback_power_on(struct kbase_device *kbdev)
-{
- int ret = 1; /* Assume GPU has been powered off */
- int error;
-
- dev_dbg(kbdev->dev, "pm_callback_power_on %p\n",
- (void *)kbdev->dev->pm_domain);
-
- error = pm_runtime_get_sync(kbdev->dev);
- if (error == 1) {
- /*
- * Let core know that the chip has not been
- * powered off, so we can save on re-initialization.
- */
- ret = 0;
- }
-
- dev_dbg(kbdev->dev, "pm_runtime_get_sync returned %d\n", error);
-
- return ret;
-}
-
-static void pm_callback_power_off(struct kbase_device *kbdev)
-{
- dev_dbg(kbdev->dev, "pm_callback_power_off\n");
-
- pm_runtime_mark_last_busy(kbdev->dev);
- pm_runtime_put_autosuspend(kbdev->dev);
-}
-
-#ifdef KBASE_PM_RUNTIME
-static int kbase_device_runtime_init(struct kbase_device *kbdev)
-{
- int ret = 0;
-
- dev_dbg(kbdev->dev, "kbase_device_runtime_init\n");
-
- pm_runtime_set_autosuspend_delay(kbdev->dev, AUTO_SUSPEND_DELAY);
- pm_runtime_use_autosuspend(kbdev->dev);
-
- pm_runtime_set_active(kbdev->dev);
- pm_runtime_enable(kbdev->dev);
-
- if (!pm_runtime_enabled(kbdev->dev)) {
- dev_warn(kbdev->dev, "pm_runtime not enabled");
- ret = -ENOSYS;
- }
-
- return ret;
-}
-
-static void kbase_device_runtime_disable(struct kbase_device *kbdev)
-{
- dev_dbg(kbdev->dev, "kbase_device_runtime_disable\n");
- pm_runtime_disable(kbdev->dev);
-}
-#endif
-
-static int pm_callback_runtime_on(struct kbase_device *kbdev)
-{
- dev_dbg(kbdev->dev, "pm_callback_runtime_on\n");
-
- return 0;
-}
-
-static void pm_callback_runtime_off(struct kbase_device *kbdev)
-{
- dev_dbg(kbdev->dev, "pm_callback_runtime_off\n");
-}
-
-static void pm_callback_resume(struct kbase_device *kbdev)
-{
- int ret = pm_callback_runtime_on(kbdev);
-
- WARN_ON(ret);
-}
-
-static void pm_callback_suspend(struct kbase_device *kbdev)
-{
- pm_callback_runtime_off(kbdev);
-}
-
-struct kbase_pm_callback_conf pm_callbacks = {
- .power_on_callback = pm_callback_power_on,
- .power_off_callback = pm_callback_power_off,
- .power_suspend_callback = pm_callback_suspend,
- .power_resume_callback = pm_callback_resume,
-#ifdef KBASE_PM_RUNTIME
- .power_runtime_init_callback = kbase_device_runtime_init,
- .power_runtime_term_callback = kbase_device_runtime_disable,
- .power_runtime_on_callback = pm_callback_runtime_on,
- .power_runtime_off_callback = pm_callback_runtime_off,
-#else /* KBASE_PM_RUNTIME */
- .power_runtime_init_callback = NULL,
- .power_runtime_term_callback = NULL,
- .power_runtime_on_callback = NULL,
- .power_runtime_off_callback = NULL,
-#endif /* KBASE_PM_RUNTIME */
-};
-
-
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_mali-driver.git / commitdiff