Keep it around for reference.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
return 0;
}
+#if 0
static int ci_set_boot_state(struct radeon_device *rdev)
{
return ci_enable_sclk_mclk_dpm(rdev, false);
}
+#endif
static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
{
return 0;
}
+#if 0
void ci_dpm_reset_asic(struct radeon_device *rdev)
{
ci_set_boot_state(rdev);
}
+#endif
void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
{
return (PPSMC_Result)tmp;
}
+#if 0
PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)
{
u32 tmp;
return PPSMC_Result_OK;
}
+#endif
int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
{