drm/nve0/fifo: keep mmu fault interrupts enabled at all times
authorBen Skeggs <bskeggs@redhat.com>
Thu, 9 Jan 2014 02:30:43 +0000 (12:30 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 23 Jan 2014 03:38:44 +0000 (13:38 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

index c4860e3d522d4374f88ea1aa3a31fef07458d4ce..3bf5ba8804e9618f67b1e2af86e455e81a6bdd36 100644 (file)
@@ -753,6 +753,21 @@ nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
        nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 }
 
+int
+nve0_fifo_fini(struct nouveau_object *object, bool suspend)
+{
+       struct nve0_fifo_priv *priv = (void *)object;
+       int ret;
+
+       ret = nouveau_fifo_fini(&priv->base, suspend);
+       if (ret)
+               return ret;
+
+       /* allow mmu fault interrupts, even when we're not using fifo */
+       nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
+       return 0;
+}
+
 int
 nve0_fifo_init(struct nouveau_object *object)
 {
@@ -855,7 +870,7 @@ nve0_fifo_oclass = &(struct nve0_fifo_impl) {
                .ctor = nve0_fifo_ctor,
                .dtor = nve0_fifo_dtor,
                .init = nve0_fifo_init,
-               .fini = _nouveau_fifo_fini,
+               .fini = nve0_fifo_fini,
        },
        .channels = 4096,
 }.base;