drm/nouveau/disp: audit and version display classes

The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
index f31527733e00fcb1f82a78538b5f1b2c90938b42..abb410ef09eab09b4fe149c955d4504905d1d2f1 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
@@ -30,7 +30,6 @@
 #include <subdev/vm.h>
 
 #include <core/client.h>
-#include <core/class.h>
 #include <core/enum.h>
 
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
index ac3291f781f6e4c204506e02d39d8ca521cf8917..9261694d0d3572701b8b1b4a79faf2ab1d4d340e 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
@@ -26,9 +26,7 @@
 #include <engine/fifo.h>
 #include <engine/copy.h>
 
-#include <core/class.h>
 #include <core/enum.h>
-#include <core/class.h>
 #include <core/enum.h>
 
 #include "fuc/nvc0.fuc.h"

diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
index 748a61eb3c6f25fe4c08bed0a374b2148852e0f5..c7194b3546057e14726bf2330ce27ece287bd916 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
@@ -24,7 +24,6 @@
 
 #include <core/os.h>
 #include <core/enum.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <engine/copy.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
index 2551dafbec73fd62bfb5ca8e42bf25b3959dbb89..ea5c42f31791a765c604acb13972368c41015153 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
@@ -25,7 +25,6 @@
 #include <core/client.h>
 #include <core/os.h>
 #include <core/enum.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/gpuobj.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
index c7082377ec76315e29fea6465d8afa56fac1146a..5571c09534cb6f8a07edfaf711ca0049d4d70a11 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
@@ -25,7 +25,6 @@
 #include <core/client.h>
 #include <core/os.h>
 #include <core/enum.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <subdev/timer.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index c7e9794a3abce58bd9e2d6eb860d25009ddfefc4..e4e089b65a016e45f234228e4a9cfca1f9428d65 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -28,7 +28,6 @@
 #include <core/option.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
-#include <core/class.h>
 
 #include <subdev/fb.h>
 #include <subdev/instmem.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index e0932b7c654c72d8300119aaa6fbb76d6cb26afc..b36addff06a9d09c74f578a48781f91b78432165 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/client.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 157bda97f59e2f0f1f757aabb311311a024c6f4c..39890221b91cbba988a6ab33534b757fce2d8718 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -30,7 +30,7 @@
 
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "dport.h"
 #include "outpdp.h"
@@ -335,7 +335,7 @@ nouveau_dp_train(struct work_struct *w)
        int ret;
 
        /* bring capabilities within encoder limits */
-       if (nv_mclass(disp) < NVD0_DISP_CLASS)
+       if (nv_mclass(disp) < GF110_DISP)
                outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
        if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
                outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
index 6a25f38d7fbff0c2915f1c6cdd68123bd7bf471c..d54da8b5f87ec97f5587bde7447ab2fbbbe5f918 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -35,17 +35,17 @@
 
 static struct nouveau_oclass
 gm107_disp_sclass[] = {
-       { GM107_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
-       { GM107_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
-       { GM107_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
-       { GM107_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
-       { GM107_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
+       { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
+       { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
+       { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
+       { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
+       { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 gm107_disp_base_oclass[] = {
-       { GM107_DISP_CLASS, &nvd0_disp_base_ofuncs },
+       { GM107_DISP, &nvd0_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
index 6dba53df35fca8e9dc003488bf9dd2ba854d35dc..9f0ae05f7d3750795f2462dc0d8057f9863b1370 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
@@ -26,7 +26,6 @@
 
 #include <core/client.h>
 #include <core/event.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -117,7 +116,7 @@ nv04_disp_ofuncs = {
 
 static struct nouveau_oclass
 nv04_disp_sclass[] = {
-       { NV04_DISP_CLASS, &nv04_disp_ofuncs },
+       { NV04_DISP, &nv04_disp_ofuncs },
        {},
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 7e60c11d7d36add1d8524a32860cfcb04f44e643..8dafd410656833cd2a9b78e94e4500bbc9b9b872 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -27,7 +27,6 @@
 #include <core/parent.h>
 #include <core/handle.h>
 #include <core/enum.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -410,14 +409,21 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
                    struct nouveau_oclass *oclass, void *data, u32 size,
                    struct nouveau_object **pobject)
 {
-       struct nv50_display_mast_class *args = data;
+       union {
+               struct nv50_disp_core_channel_dma_v0 v0;
+       } *args = data;
        struct nv50_disp_dmac *mast;
        int ret;
 
-       if (size < sizeof(*args))
-               return -EINVAL;
+       nv_ioctl(parent, "create disp core channel dma size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, false)) {
+               nv_ioctl(parent, "create disp core channel dma vers %d "
+                                "pushbuf %08x\n",
+                        args->v0.version, args->v0.pushbuf);
+       } else
+               return ret;
 
-       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
+       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
                                     0, sizeof(*mast), (void **)&mast);
        *pobject = nv_object(mast);
        if (ret)
@@ -557,16 +563,26 @@ nv50_disp_sync_ctor(struct nouveau_object *parent,
                    struct nouveau_oclass *oclass, void *data, u32 size,
                    struct nouveau_object **pobject)
 {
-       struct nv50_display_sync_class *args = data;
+       union {
+               struct nv50_disp_base_channel_dma_v0 v0;
+       } *args = data;
        struct nv50_disp_priv *priv = (void *)engine;
        struct nv50_disp_dmac *dmac;
        int ret;
 
-       if (size < sizeof(*args) || args->head >= priv->head.nr)
-               return -EINVAL;
+       nv_ioctl(parent, "create disp base channel dma size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, false)) {
+               nv_ioctl(parent, "create disp base channel dma vers %d "
+                                "pushbuf %08x head %d\n",
+                        args->v0.version, args->v0.pushbuf, args->v0.head);
+               if (args->v0.head > priv->head.nr)
+                       return -EINVAL;
+       } else
+               return ret;
 
-       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
-                                    args->head, sizeof(*dmac), (void **)&dmac);
+       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
+                                    args->v0.head, sizeof(*dmac),
+                                    (void **)&dmac);
        *pobject = nv_object(dmac);
        if (ret)
                return ret;
@@ -635,16 +651,26 @@ nv50_disp_ovly_ctor(struct nouveau_object *parent,
                    struct nouveau_oclass *oclass, void *data, u32 size,
                    struct nouveau_object **pobject)
 {
-       struct nv50_display_ovly_class *args = data;
+       union {
+               struct nv50_disp_overlay_channel_dma_v0 v0;
+       } *args = data;
        struct nv50_disp_priv *priv = (void *)engine;
        struct nv50_disp_dmac *dmac;
        int ret;
 
-       if (size < sizeof(*args) || args->head >= priv->head.nr)
-               return -EINVAL;
+       nv_ioctl(parent, "create disp overlay channel dma size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, false)) {
+               nv_ioctl(parent, "create disp overlay channel dma vers %d "
+                                "pushbuf %08x head %d\n",
+                        args->v0.version, args->v0.pushbuf, args->v0.head);
+               if (args->v0.head > priv->head.nr)
+                       return -EINVAL;
+       } else
+               return ret;
 
-       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
-                                    args->head, sizeof(*dmac), (void **)&dmac);
+       ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
+                                    args->v0.head, sizeof(*dmac),
+                                    (void **)&dmac);
        *pobject = nv_object(dmac);
        if (ret)
                return ret;
@@ -743,15 +769,23 @@ nv50_disp_oimm_ctor(struct nouveau_object *parent,
                    struct nouveau_oclass *oclass, void *data, u32 size,
                    struct nouveau_object **pobject)
 {
-       struct nv50_display_oimm_class *args = data;
+       union {
+               struct nv50_disp_overlay_v0 v0;
+       } *args = data;
        struct nv50_disp_priv *priv = (void *)engine;
        struct nv50_disp_pioc *pioc;
        int ret;
 
-       if (size < sizeof(*args) || args->head >= priv->head.nr)
-               return -EINVAL;
+       nv_ioctl(parent, "create disp overlay size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, false)) {
+               nv_ioctl(parent, "create disp overlay vers %d head %d\n",
+                        args->v0.version, args->v0.head);
+               if (args->v0.head > priv->head.nr)
+                       return -EINVAL;
+       } else
+               return ret;
 
-       ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head,
+       ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
                                     sizeof(*pioc), (void **)&pioc);
        *pobject = nv_object(pioc);
        if (ret)
@@ -781,15 +815,23 @@ nv50_disp_curs_ctor(struct nouveau_object *parent,
                    struct nouveau_oclass *oclass, void *data, u32 size,
                    struct nouveau_object **pobject)
 {
-       struct nv50_display_curs_class *args = data;
+       union {
+               struct nv50_disp_cursor_v0 v0;
+       } *args = data;
        struct nv50_disp_priv *priv = (void *)engine;
        struct nv50_disp_pioc *pioc;
        int ret;
 
-       if (size < sizeof(*args) || args->head >= priv->head.nr)
-               return -EINVAL;
+       nv_ioctl(parent, "create disp cursor size %d\n", size);
+       if (nvif_unpack(args->v0, 0, 0, false)) {
+               nv_ioctl(parent, "create disp cursor vers %d head %d\n",
+                        args->v0.version, args->v0.head);
+               if (args->v0.head > priv->head.nr)
+                       return -EINVAL;
+       } else
+               return ret;
 
-       ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head,
+       ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
                                     sizeof(*pioc), (void **)&pioc);
        *pobject = nv_object(pioc);
        if (ret)
@@ -1089,17 +1131,17 @@ nv50_disp_base_ofuncs = {
 
 static struct nouveau_oclass
 nv50_disp_base_oclass[] = {
-       { NV50_DISP_CLASS, &nv50_disp_base_ofuncs },
+       { NV50_DISP, &nv50_disp_base_ofuncs },
        {}
 };
 
 static struct nouveau_oclass
 nv50_disp_sclass[] = {
-       { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
-       { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
-       { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
-       { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
-       { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
+       { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
+       { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
+       { NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
+       { NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
+       { NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index 81bf80fd8dcd0625db509511c6f69c4a958d6528..9be9b45e3c5edf373826046d0075e66ad1783598 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -188,6 +188,7 @@ int  nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
                         struct nouveau_oclass *, void *, u32,
                         struct nouveau_object **);
 void nv50_disp_base_dtor(struct nouveau_object *);
+extern struct nouveau_omthds nv50_disp_base_omthds[];
 extern struct nouveau_oclass nv50_disp_cclass;
 void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
                         const struct nv50_disp_mthd_chan *);

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index 8746644d9dedfe14a8008fa0069fc4f086e7f9da..788ced1b6182f8c5cd925ed402cd6c85f772eb66 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -204,17 +204,17 @@ nv84_disp_ovly_mthd_chan = {
 
 static struct nouveau_oclass
 nv84_disp_sclass[] = {
-       { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
-       { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
-       { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
-       { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
-       { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
+       { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
+       { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
+       { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
+       { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
+       { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nv84_disp_base_oclass[] = {
-       { NV84_DISP_CLASS, &nv50_disp_base_ofuncs },
+       { G82_DISP, &nv50_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index 11cd16abcee2bdf5c7a905ce0839016750e93daa..fa79de906eaefd1dd39e90e9e2bc0d8994c6ebca 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -63,17 +63,17 @@ nv94_disp_mast_mthd_chan = {
 
 static struct nouveau_oclass
 nv94_disp_sclass[] = {
-       { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
-       { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
-       { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
-       { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
-       { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
+       { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
+       { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
+       { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
+       { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
+       { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nv94_disp_base_oclass[] = {
-       { NV94_DISP_CLASS, &nv50_disp_base_ofuncs },
+       { GT206_DISP, &nv50_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
index 381957586f0391262c65bf00d9e1fe990cf6cd98..7af15f5d48dc2c08a7ecc0c694ab1f7c04a0a524 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -80,17 +80,17 @@ nva0_disp_ovly_mthd_chan = {
 
 static struct nouveau_oclass
 nva0_disp_sclass[] = {
-       { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
-       { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
-       { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
-       { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
-       { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
+       { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
+       { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
+       { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
+       { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
+       { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nva0_disp_base_oclass[] = {
-       { NVA0_DISP_CLASS, &nv50_disp_base_ofuncs },
+       { GT200_DISP, &nv50_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 25df6b93c93ad3bd9e11fc382d605832c2dae89f..6bd39448f8dab91d621a09cc22b99a9c8b9ab591 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -35,17 +35,17 @@
 
 static struct nouveau_oclass
 nva3_disp_sclass[] = {
-       { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
-       { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
-       { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
-       { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
-       { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
+       { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
+       { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
+       { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
+       { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
+       { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nva3_disp_base_oclass[] = {
-       { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs },
+       { GT214_DISP, &nv50_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index deddd05e7c76d83634d746d77bad83c0d04b53e7..f64647b8b8d06f8a7e9233d0ac6f1b7f733f5413 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -26,7 +26,6 @@
 #include <core/client.h>
 #include <core/parent.h>
 #include <core/handle.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -716,17 +715,17 @@ nvd0_disp_base_ofuncs = {
 
 static struct nouveau_oclass
 nvd0_disp_base_oclass[] = {
-       { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs },
+       { GF110_DISP, &nvd0_disp_base_ofuncs },
        {}
 };
 
 static struct nouveau_oclass
 nvd0_disp_sclass[] = {
-       { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
-       { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
-       { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
-       { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
-       { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
+       { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
+       { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
+       { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
+       { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
+       { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 58b0ac101f16c69e359b885f885fe5aad45e1406..47fef1e398c4ca2e5c5077a689a9d957ff9a8e1b 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -200,17 +200,17 @@ nve0_disp_ovly_mthd_chan = {
 
 static struct nouveau_oclass
 nve0_disp_sclass[] = {
-       { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
-       { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
-       { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
-       { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
-       { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
+       { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
+       { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
+       { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
+       { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
+       { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nve0_disp_base_oclass[] = {
-       { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs },
+       { GK104_DISP, &nvd0_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index b6b01463eb6cab16b25f10fed9d302335e33562a..04bda4ac4ed3dab138db7f30ca7b9b9235b10126 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -25,7 +25,7 @@
 #include <engine/software.h>
 #include <engine/disp.h>
 
-#include <core/class.h>
+#include <nvif/class.h>
 
 #include "nv50.h"
 
@@ -35,17 +35,17 @@
 
 static struct nouveau_oclass
 nvf0_disp_sclass[] = {
-       { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
-       { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
-       { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
-       { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
-       { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
+       { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
+       { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
+       { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
+       { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
+       { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_oclass
 nvf0_disp_base_oclass[] = {
-       { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs },
+       { GK110_DISP, &nvd0_disp_base_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 7b32821f3622a692f161f66534a98f957ffbd0a7..ddf1760c440045fe98af821229d2a7e0ac8962ae 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/client.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
index 05487cda84a89afd7e7e79813aaa9330a9b7cdb8..39f85d6273365c7a79fa797f1d51ffcaad4ea6f4 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
index 97f0e9cd3d40b71b2a793c086eb18a617da14d39..7b7bbc3e459e4eceafd2a476cca3a65a21254cdc 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
index 3e14f46cfbd23ce9d596ff98af706f42bb5a3329..20c9dbfe3b2e9124ae07978857a92c4197a1598d 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/gpuobj.h>
-#include <core/class.h>
 #include <nvif/class.h>
 
 #include <subdev/fb.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
index 7495f7d363bbfa29961d07e8d78e7402814ebf4c..a740ddba2ee26626d3f013cf5dcd78c7ee66e92d 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
@@ -24,7 +24,6 @@
 
 #include <core/client.h>
 #include <core/gpuobj.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -51,21 +50,19 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
                case NV40_CHANNEL_DMA:
                case NV50_CHANNEL_GPFIFO:
                case G82_CHANNEL_GPFIFO:
-               case NV50_DISP_MAST_CLASS:
-               case NV84_DISP_MAST_CLASS:
-               case NV94_DISP_MAST_CLASS:
-               case NVA0_DISP_MAST_CLASS:
-               case NVA3_DISP_MAST_CLASS:
-               case NV50_DISP_SYNC_CLASS:
-               case NV84_DISP_SYNC_CLASS:
-               case NV94_DISP_SYNC_CLASS:
-               case NVA0_DISP_SYNC_CLASS:
-               case NVA3_DISP_SYNC_CLASS:
-               case NV50_DISP_OVLY_CLASS:
-               case NV84_DISP_OVLY_CLASS:
-               case NV94_DISP_OVLY_CLASS:
-               case NVA0_DISP_OVLY_CLASS:
-               case NVA3_DISP_OVLY_CLASS:
+               case NV50_DISP_CORE_CHANNEL_DMA:
+               case G82_DISP_CORE_CHANNEL_DMA:
+               case GT206_DISP_CORE_CHANNEL_DMA:
+               case GT200_DISP_CORE_CHANNEL_DMA:
+               case GT214_DISP_CORE_CHANNEL_DMA:
+               case NV50_DISP_BASE_CHANNEL_DMA:
+               case G82_DISP_BASE_CHANNEL_DMA:
+               case GT200_DISP_BASE_CHANNEL_DMA:
+               case GT214_DISP_BASE_CHANNEL_DMA:
+               case NV50_DISP_OVERLAY_CHANNEL_DMA:
+               case G82_DISP_OVERLAY_CHANNEL_DMA:
+               case GT200_DISP_OVERLAY_CHANNEL_DMA:
+               case GT214_DISP_OVERLAY_CHANNEL_DMA:
                        break;
                default:
                        return -EINVAL;

diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
index ef8031e082c2f321406183aeb4fe978cb091afe2..88ec33b20048d73a86b5f429031b79f27c9959ce 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
@@ -25,7 +25,6 @@
 #include <core/client.h>
 #include <core/device.h>
 #include <core/gpuobj.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -49,9 +48,9 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
 
        if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
                switch (nv_mclass(parent->parent)) {
-               case NVA3_DISP_MAST_CLASS:
-               case NVA3_DISP_SYNC_CLASS:
-               case NVA3_DISP_OVLY_CLASS:
+               case GT214_DISP_CORE_CHANNEL_DMA:
+               case GT214_DISP_BASE_CHANNEL_DMA:
+               case GT214_DISP_OVERLAY_CHANNEL_DMA:
                        break;
                default:
                        return -EINVAL;

diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
index d07ed0daa14d520ad3f6a01854075277f3f804f7..3fc4f0b0eacae1b86c0b3507f10a801a24ae185b 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
@@ -25,7 +25,6 @@
 #include <core/client.h>
 #include <core/device.h>
 #include <core/gpuobj.h>
-#include <core/class.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
 
@@ -48,18 +47,15 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
 
        if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
                switch (nv_mclass(parent->parent)) {
-               case NVD0_DISP_MAST_CLASS:
-               case NVD0_DISP_SYNC_CLASS:
-               case NVD0_DISP_OVLY_CLASS:
-               case NVE0_DISP_MAST_CLASS:
-               case NVE0_DISP_SYNC_CLASS:
-               case NVE0_DISP_OVLY_CLASS:
-               case NVF0_DISP_MAST_CLASS:
-               case NVF0_DISP_SYNC_CLASS:
-               case NVF0_DISP_OVLY_CLASS:
-               case GM107_DISP_MAST_CLASS:
-               case GM107_DISP_SYNC_CLASS:
-               case GM107_DISP_OVLY_CLASS:
+               case GF110_DISP_CORE_CHANNEL_DMA:
+               case GK104_DISP_CORE_CHANNEL_DMA:
+               case GK110_DISP_CORE_CHANNEL_DMA:
+               case GM107_DISP_CORE_CHANNEL_DMA:
+               case GF110_DISP_BASE_CHANNEL_DMA:
+               case GK104_DISP_BASE_CHANNEL_DMA:
+               case GK110_DISP_BASE_CHANNEL_DMA:
+               case GF110_DISP_OVERLAY_CONTROL_DMA:
+               case GK104_DISP_OVERLAY_CONTROL_DMA:
                        break;
                default:
                        return -EINVAL;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
index ad13dcdd15f98b9abc9c3739563d8cd5a0837c37..f70e2f67a4ddce8b66ef7b4c34c28174b08cde84 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
@@ -24,7 +24,6 @@
 
 #include <core/client.h>
 #include <core/os.h>
-#include <core/class.h>
 #include <core/handle.h>
 #include <core/namedb.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
index 4532f7e5618cf9f8d96d21198f35dc573f78b028..2b12b09683c82c071290f41a90c816a3fb51f315 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
@@ -24,7 +24,6 @@
 
 #include <core/client.h>
 #include <core/os.h>
-#include <core/class.h>
 #include <core/handle.h>
 
 #include <subdev/fb.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
index d145e080899afd788f27638f580d45b108dd7425..ceb9c746d94edecdb8522b1dc65b5ed18b23c0ad 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
@@ -1,6 +1,5 @@
 #include <core/client.h>
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/handle.h>
 #include <core/enum.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
index 7a80d005a9741afea220be465a860f46aaedfeef..f8a6fdd7d5e8ef9956d89dcdf4f4cf0e7da165bd 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
@@ -1,5 +1,4 @@
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/enum.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
index 3e1f32ee43d4c4c902873de190a3de41916026e4..5de9caa2ef67f284ec3962fabc76380951bb525e 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
@@ -1,5 +1,4 @@
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/enum.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
index e451db32e92a6ecb05e1e61716a116bcfc8afbac..2f9dbc7093898db6df0ec8cd760d82035126cbe7 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
@@ -1,5 +1,4 @@
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/enum.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
index 9385ac7b44a493970c32a162913494c0f8f1fde0..34dd26c70b640bdea82eeb672b656bb7294d72af 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
@@ -1,5 +1,4 @@
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/enum.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
index 9ce84b73f86a21cf0e9277e998db271965b386db..2fb5756d9f66652ec3f1e90b19e2bb6dbd5e3504 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
@@ -1,5 +1,4 @@
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/enum.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
index 6477fbf6a550ce84804d2b5c743b1802ed41548d..4f401174868d998d5a39be02bb7588647990e474 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
@@ -24,7 +24,6 @@
 
 #include <core/client.h>
 #include <core/os.h>
-#include <core/class.h>
 #include <core/handle.h>
 #include <core/engctx.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 20665c21d80e2fc6c4b243882c2e246590f6492a..38e0aa26f1cdf389f4092e09f93115559460cbb6 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/client.h>
 #include <core/handle.h>
 #include <core/engctx.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
index 7eb6d94c84e2ac10e3afc72f8db201504b47a8e1..d88c700b2f6946499f774cdcb5c356a8e587936b 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
@@ -24,7 +24,6 @@
 
 #include <core/client.h>
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/handle.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
index d4e7ec0ba68ca66a8c3600df9532a33c43bfbc11..bdb2f20ff7b14ea6f8f837127cbc40114ad1db63 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <subdev/fb.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
index 3d8c2133e0e83d6afefad197aa17e1e18ab1abfe..72c7f33fd29b9212285db328ce8492aa3b6039bf 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/client.h>
 #include <core/engctx.h>
 #include <core/handle.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
index 37a2bd9e80786937db8a16cec05e09a3f6a151b2..cae33f86b11ac69f902c27e1b9b24b906f556119 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <subdev/vm.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
index 96f5aa92677b3850d91baee160c34f8c354f9bc7..e9cc8b116a242d4733eeaaa66e048d518fd724c6 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <subdev/vm.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
index c571758e4a27c1b3b8c140c833ff24754504b225..64df15c7f0516b3d199a188b34b00d82b2578b37 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <engine/software.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
index a62f11a78430e3949e057d77000d0776b63e35e9..f54a2253decadfb9624ba1508bfdf8b2e51e6e97 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 
 #include <engine/software.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
index 48678ed41ba47e8382fd803b0707d1ee7fd149fa..4d2994d8cc32209800977e3008c482897b92fb4f 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/namedb.h>
 #include <core/handle.h>

diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
index df299a91cf706fa931fa1389ed7da08497d89a0b..6af370d3a06da9bdaeb2f5df06aa8d6f935ef8a8 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
@@ -23,7 +23,6 @@
  */
 
 #include <core/os.h>
-#include <core/class.h>
 #include <core/engctx.h>
 #include <core/event.h>
 

diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
deleted file mode 100644 (file)
index 24b85a9..0000000
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef __NOUVEAU_CLASS_H__
-#define __NOUVEAU_CLASS_H__
-
-#include <nvif/class.h>
-
-/* 0046: NV04_DISP
- */
-
-#define NV04_DISP_CLASS                                              0x00000046
-
-struct nv04_display_class {
-};
-
-/* 5070: NV50_DISP
- * 8270: NV84_DISP
- * 8370: NVA0_DISP
- * 8870: NV94_DISP
- * 8570: NVA3_DISP
- * 9070: NVD0_DISP
- * 9170: NVE0_DISP
- * 9270: NVF0_DISP
- * 9470: GM107_DISP
- */
-
-#define NV50_DISP_CLASS                                              0x00005070
-#define NV84_DISP_CLASS                                              0x00008270
-#define NVA0_DISP_CLASS                                              0x00008370
-#define NV94_DISP_CLASS                                              0x00008870
-#define NVA3_DISP_CLASS                                              0x00008570
-#define NVD0_DISP_CLASS                                              0x00009070
-#define NVE0_DISP_CLASS                                              0x00009170
-#define NVF0_DISP_CLASS                                              0x00009270
-#define GM107_DISP_CLASS                                             0x00009470
-
-struct nv50_display_class {
-};
-
-/* 507a: NV50_DISP_CURS
- * 827a: NV84_DISP_CURS
- * 837a: NVA0_DISP_CURS
- * 887a: NV94_DISP_CURS
- * 857a: NVA3_DISP_CURS
- * 907a: NVD0_DISP_CURS
- * 917a: NVE0_DISP_CURS
- * 927a: NVF0_DISP_CURS
- * 947a: GM107_DISP_CURS
- */
-
-#define NV50_DISP_CURS_CLASS                                         0x0000507a
-#define NV84_DISP_CURS_CLASS                                         0x0000827a
-#define NVA0_DISP_CURS_CLASS                                         0x0000837a
-#define NV94_DISP_CURS_CLASS                                         0x0000887a
-#define NVA3_DISP_CURS_CLASS                                         0x0000857a
-#define NVD0_DISP_CURS_CLASS                                         0x0000907a
-#define NVE0_DISP_CURS_CLASS                                         0x0000917a
-#define NVF0_DISP_CURS_CLASS                                         0x0000927a
-#define GM107_DISP_CURS_CLASS                                        0x0000947a
-
-struct nv50_display_curs_class {
-       u32 head;
-};
-
-/* 507b: NV50_DISP_OIMM
- * 827b: NV84_DISP_OIMM
- * 837b: NVA0_DISP_OIMM
- * 887b: NV94_DISP_OIMM
- * 857b: NVA3_DISP_OIMM
- * 907b: NVD0_DISP_OIMM
- * 917b: NVE0_DISP_OIMM
- * 927b: NVE0_DISP_OIMM
- * 947b: GM107_DISP_OIMM
- */
-
-#define NV50_DISP_OIMM_CLASS                                         0x0000507b
-#define NV84_DISP_OIMM_CLASS                                         0x0000827b
-#define NVA0_DISP_OIMM_CLASS                                         0x0000837b
-#define NV94_DISP_OIMM_CLASS                                         0x0000887b
-#define NVA3_DISP_OIMM_CLASS                                         0x0000857b
-#define NVD0_DISP_OIMM_CLASS                                         0x0000907b
-#define NVE0_DISP_OIMM_CLASS                                         0x0000917b
-#define NVF0_DISP_OIMM_CLASS                                         0x0000927b
-#define GM107_DISP_OIMM_CLASS                                        0x0000947b
-
-struct nv50_display_oimm_class {
-       u32 head;
-};
-
-/* 507c: NV50_DISP_SYNC
- * 827c: NV84_DISP_SYNC
- * 837c: NVA0_DISP_SYNC
- * 887c: NV94_DISP_SYNC
- * 857c: NVA3_DISP_SYNC
- * 907c: NVD0_DISP_SYNC
- * 917c: NVE0_DISP_SYNC
- * 927c: NVF0_DISP_SYNC
- * 947c: GM107_DISP_SYNC
- */
-
-#define NV50_DISP_SYNC_CLASS                                         0x0000507c
-#define NV84_DISP_SYNC_CLASS                                         0x0000827c
-#define NVA0_DISP_SYNC_CLASS                                         0x0000837c
-#define NV94_DISP_SYNC_CLASS                                         0x0000887c
-#define NVA3_DISP_SYNC_CLASS                                         0x0000857c
-#define NVD0_DISP_SYNC_CLASS                                         0x0000907c
-#define NVE0_DISP_SYNC_CLASS                                         0x0000917c
-#define NVF0_DISP_SYNC_CLASS                                         0x0000927c
-#define GM107_DISP_SYNC_CLASS                                        0x0000947c
-
-struct nv50_display_sync_class {
-       u32 pushbuf;
-       u32 head;
-};
-
-/* 507d: NV50_DISP_MAST
- * 827d: NV84_DISP_MAST
- * 837d: NVA0_DISP_MAST
- * 887d: NV94_DISP_MAST
- * 857d: NVA3_DISP_MAST
- * 907d: NVD0_DISP_MAST
- * 917d: NVE0_DISP_MAST
- * 927d: NVF0_DISP_MAST
- * 947d: GM107_DISP_MAST
- */
-
-#define NV50_DISP_MAST_CLASS                                         0x0000507d
-#define NV84_DISP_MAST_CLASS                                         0x0000827d
-#define NVA0_DISP_MAST_CLASS                                         0x0000837d
-#define NV94_DISP_MAST_CLASS                                         0x0000887d
-#define NVA3_DISP_MAST_CLASS                                         0x0000857d
-#define NVD0_DISP_MAST_CLASS                                         0x0000907d
-#define NVE0_DISP_MAST_CLASS                                         0x0000917d
-#define NVF0_DISP_MAST_CLASS                                         0x0000927d
-#define GM107_DISP_MAST_CLASS                                        0x0000947d
-
-struct nv50_display_mast_class {
-       u32 pushbuf;
-};
-
-/* 507e: NV50_DISP_OVLY
- * 827e: NV84_DISP_OVLY
- * 837e: NVA0_DISP_OVLY
- * 887e: NV94_DISP_OVLY
- * 857e: NVA3_DISP_OVLY
- * 907e: NVD0_DISP_OVLY
- * 917e: NVE0_DISP_OVLY
- * 927e: NVF0_DISP_OVLY
- * 947e: GM107_DISP_OVLY
- */
-
-#define NV50_DISP_OVLY_CLASS                                         0x0000507e
-#define NV84_DISP_OVLY_CLASS                                         0x0000827e
-#define NVA0_DISP_OVLY_CLASS                                         0x0000837e
-#define NV94_DISP_OVLY_CLASS                                         0x0000887e
-#define NVA3_DISP_OVLY_CLASS                                         0x0000857e
-#define NVD0_DISP_OVLY_CLASS                                         0x0000907e
-#define NVE0_DISP_OVLY_CLASS                                         0x0000917e
-#define NVF0_DISP_OVLY_CLASS                                         0x0000927e
-#define GM107_DISP_OVLY_CLASS                                        0x0000947e
-
-struct nv50_display_ovly_class {
-       u32 pushbuf;
-       u32 head;
-};
-
-#endif

diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
index 49b0024910fef2262d585a761198a5b6a18552db..88cc812baaa3a93e3dcd9f1479977e7ac246ab08 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
@@ -4,7 +4,6 @@
 #include <core/device.h>
 #include <core/engine.h>
 #include <core/engctx.h>
-#include <core/class.h>
 
 struct nouveau_perfdom;
 struct nouveau_perfctr;

diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index f00e56c79ac47968a3bc42f4dcbfbc3181b3f1fb..a5a1f298c00156667c7eca9c20f3f7b26b98716e 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -404,10 +404,10 @@ nouveau_display_create_properties(struct drm_device *dev)
        struct nouveau_display *disp = nouveau_display(dev);
        int gen;
 
-       if (disp->disp.oclass < NV50_DISP_CLASS)
+       if (disp->disp.oclass < NV50_DISP)
                gen = 0;
        else
-       if (disp->disp.oclass < NVD0_DISP_CLASS)
+       if (disp->disp.oclass < GF110_DISP)
                gen = 1;
        else
                gen = 2;
@@ -479,16 +479,16 @@ nouveau_display_create(struct drm_device *dev)
 
        if (drm->vbios.dcb.entries) {
                static const u16 oclass[] = {
-                       GM107_DISP_CLASS,
-                       NVF0_DISP_CLASS,
-                       NVE0_DISP_CLASS,
-                       NVD0_DISP_CLASS,
-                       NVA3_DISP_CLASS,
-                       NV94_DISP_CLASS,
-                       NVA0_DISP_CLASS,
-                       NV84_DISP_CLASS,
-                       NV50_DISP_CLASS,
-                       NV04_DISP_CLASS,
+                       GM107_DISP,
+                       GK110_DISP,
+                       GK104_DISP,
+                       GF110_DISP,
+                       GT214_DISP,
+                       GT206_DISP,
+                       GT200_DISP,
+                       G82_DISP,
+                       NV50_DISP,
+                       NV04_DISP,
                };
                int i;
 
@@ -500,7 +500,7 @@ nouveau_display_create(struct drm_device *dev)
 
                if (ret == 0) {
                        nouveau_display_create_properties(dev);
-                       if (disp->disp.oclass < NV50_DISP_CLASS)
+                       if (disp->disp.oclass < NV50_DISP)
                                ret = nv04_display_create(dev);
                        else
                                ret = nv50_display_create(dev);

diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index f11b65195337a1cabf1e850221189eb1631d738b..12b5ba3d4fdc9ae9c7a049de637e3eb765374751 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -33,7 +33,6 @@
 
 #include <core/device.h>
 #include <core/gpuobj.h>
-#include <core/class.h>
 #include <core/option.h>
 
 #include "nouveau_drm.h"

diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index 5479013e13f4496552f7121e495444c3c9e54c68..3a6ef5018f5271226b7ae9f17dd9aff1681b9c8a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -28,8 +28,6 @@
 #include <nvif/client.h>
 #include <nvif/device.h>
 
-#include <core/class.h>
-
 #include <drmP.h>
 
 #include <drm/ttm/ttm_bo_api.h>

diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index bd85026ee067c243691e7f43987646f83cd9365f..82d6b4f6a5c2d3451396017b83148582baecd236 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -53,12 +53,6 @@
 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
 
-#define EVO_CORE_HANDLE      (0xd1500000)
-#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
-#define EVO_CHAN_OCLASS(t,c) (((c)->oclass & 0xff00) | ((t) & 0x00ff))
-#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
-                             (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
-
 /******************************************************************************
  * EVO channel
  *****************************************************************************/
@@ -119,19 +113,15 @@ struct nv50_curs {
 static int
 nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
 {
-       struct nv50_display_curs_class args = {
+       struct nv50_disp_cursor_v0 args = {
                .head = head,
        };
        static const u32 oclass[] = {
-               GM107_DISP_CURS_CLASS,
-               NVF0_DISP_CURS_CLASS,
-               NVE0_DISP_CURS_CLASS,
-               NVD0_DISP_CURS_CLASS,
-               NVA3_DISP_CURS_CLASS,
-               NV94_DISP_CURS_CLASS,
-               NVA0_DISP_CURS_CLASS,
-               NV84_DISP_CURS_CLASS,
-               NV50_DISP_CURS_CLASS,
+               GK104_DISP_CURSOR,
+               GF110_DISP_CURSOR,
+               GT214_DISP_CURSOR,
+               G82_DISP_CURSOR,
+               NV50_DISP_CURSOR,
                0
        };
 
@@ -150,19 +140,15 @@ struct nv50_oimm {
 static int
 nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
 {
-       struct nv50_display_oimm_class args = {
+       struct nv50_disp_cursor_v0 args = {
                .head = head,
        };
        static const u32 oclass[] = {
-               GM107_DISP_OIMM_CLASS,
-               NVF0_DISP_OIMM_CLASS,
-               NVE0_DISP_OIMM_CLASS,
-               NVD0_DISP_OIMM_CLASS,
-               NVA3_DISP_OIMM_CLASS,
-               NV94_DISP_OIMM_CLASS,
-               NVA0_DISP_OIMM_CLASS,
-               NV84_DISP_OIMM_CLASS,
-               NV50_DISP_OIMM_CLASS,
+               GK104_DISP_OVERLAY,
+               GF110_DISP_OVERLAY,
+               GT214_DISP_OVERLAY,
+               G82_DISP_OVERLAY,
+               NV50_DISP_OVERLAY,
                0
        };
 
@@ -208,8 +194,8 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
                 struct nv50_dmac *dmac)
 {
        struct nouveau_fb *pfb = nvkm_fb(nvif_device(disp));
+       struct nv50_disp_core_channel_dma_v0 *args = data;
        struct nvif_object pushbuf;
-       u32 handle = *(u32 *)data;
        int ret;
 
        mutex_init(&dmac->lock);
@@ -219,8 +205,8 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
        if (!dmac->ptr)
                return -ENOMEM;
 
-       ret = nvif_object_init(nvif_object(nvif_device(disp)), NULL, handle,
-                              NV_DMA_FROM_MEMORY,
+       ret = nvif_object_init(nvif_object(nvif_device(disp)), NULL,
+                              args->pushbuf, NV_DMA_FROM_MEMORY,
                               &(struct nv_dma_v0) {
                                        .target = NV_DMA_V0_TARGET_PCI_US,
                                        .access = NV_DMA_V0_ACCESS_RD,
@@ -273,19 +259,19 @@ struct nv50_mast {
 static int
 nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
 {
-       struct nv50_display_mast_class args = {
-               .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
+       struct nv50_disp_core_channel_dma_v0 args = {
+               .pushbuf = 0xb0007d00,
        };
        static const u32 oclass[] = {
-               GM107_DISP_MAST_CLASS,
-               NVF0_DISP_MAST_CLASS,
-               NVE0_DISP_MAST_CLASS,
-               NVD0_DISP_MAST_CLASS,
-               NVA3_DISP_MAST_CLASS,
-               NV94_DISP_MAST_CLASS,
-               NVA0_DISP_MAST_CLASS,
-               NV84_DISP_MAST_CLASS,
-               NV50_DISP_MAST_CLASS,
+               GM107_DISP_CORE_CHANNEL_DMA,
+               GK110_DISP_CORE_CHANNEL_DMA,
+               GK104_DISP_CORE_CHANNEL_DMA,
+               GF110_DISP_CORE_CHANNEL_DMA,
+               GT214_DISP_CORE_CHANNEL_DMA,
+               GT206_DISP_CORE_CHANNEL_DMA,
+               GT200_DISP_CORE_CHANNEL_DMA,
+               G82_DISP_CORE_CHANNEL_DMA,
+               NV50_DISP_CORE_CHANNEL_DMA,
                0
        };
 
@@ -307,20 +293,18 @@ static int
 nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
                 struct nv50_sync *base)
 {
-       struct nv50_display_sync_class args = {
-               .pushbuf = EVO_PUSH_HANDLE(SYNC, head),
+       struct nv50_disp_base_channel_dma_v0 args = {
+               .pushbuf = 0xb0007c00 | head,
                .head = head,
        };
        static const u32 oclass[] = {
-               GM107_DISP_SYNC_CLASS,
-               NVF0_DISP_SYNC_CLASS,
-               NVE0_DISP_SYNC_CLASS,
-               NVD0_DISP_SYNC_CLASS,
-               NVA3_DISP_SYNC_CLASS,
-               NV94_DISP_SYNC_CLASS,
-               NVA0_DISP_SYNC_CLASS,
-               NV84_DISP_SYNC_CLASS,
-               NV50_DISP_SYNC_CLASS,
+               GK110_DISP_BASE_CHANNEL_DMA,
+               GK104_DISP_BASE_CHANNEL_DMA,
+               GF110_DISP_BASE_CHANNEL_DMA,
+               GT214_DISP_BASE_CHANNEL_DMA,
+               GT200_DISP_BASE_CHANNEL_DMA,
+               G82_DISP_BASE_CHANNEL_DMA,
+               NV50_DISP_BASE_CHANNEL_DMA,
                0
        };
 
@@ -340,20 +324,17 @@ static int
 nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
                 struct nv50_ovly *ovly)
 {
-       struct nv50_display_ovly_class args = {
-               .pushbuf = EVO_PUSH_HANDLE(OVLY, head),
+       struct nv50_disp_overlay_channel_dma_v0 args = {
+               .pushbuf = 0xb0007e00 | head,
                .head = head,
        };
        static const u32 oclass[] = {
-               GM107_DISP_OVLY_CLASS,
-               NVF0_DISP_OVLY_CLASS,
-               NVE0_DISP_OVLY_CLASS,
-               NVD0_DISP_OVLY_CLASS,
-               NVA3_DISP_OVLY_CLASS,
-               NV94_DISP_OVLY_CLASS,
-               NVA0_DISP_OVLY_CLASS,
-               NV84_DISP_OVLY_CLASS,
-               NV50_DISP_OVLY_CLASS,
+               GK104_DISP_OVERLAY_CONTROL_DMA,
+               GF110_DISP_OVERLAY_CONTROL_DMA,
+               GT214_DISP_OVERLAY_CHANNEL_DMA,
+               GT200_DISP_OVERLAY_CHANNEL_DMA,
+               G82_DISP_OVERLAY_CHANNEL_DMA,
+               NV50_DISP_OVERLAY_CHANNEL_DMA,
                0
        };
 
@@ -628,7 +609,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
        evo_mthd(push, 0x0110, 2);
        evo_data(push, 0x00000000);
        evo_data(push, 0x00000000);
-       if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
+       if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
                evo_mthd(push, 0x0800, 5);
                evo_data(push, nv_fb->nvbo->bo.offset >> 8);
                evo_data(push, 0);
@@ -680,11 +661,11 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 
        push = evo_wait(mast, 4);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
                        evo_data(push, mode);
                } else
-               if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
                        evo_data(push, mode);
                } else {
@@ -775,7 +756,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 
        push = evo_wait(mast, 8);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        /*XXX: SCALE_CTRL_ACTIVE??? */
                        evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
                        evo_data(push, (oY << 16) | oX);
@@ -820,7 +801,7 @@ nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 
        push = evo_wait(mast, 16);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, (hue << 20) | (vib << 8));
                } else {
@@ -848,7 +829,7 @@ nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 
        push = evo_wait(mast, 16);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, nvfb->nvbo->bo.offset >> 8);
                        evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
@@ -857,7 +838,7 @@ nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
                        evo_data(push, nvfb->r_format);
                        evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, (y << 16) | x);
-                       if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
+                       if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
                                evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
                                evo_data(push, nvfb->r_handle);
                        }
@@ -890,12 +871,12 @@ nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
        u32 *push = evo_wait(mast, 16);
        if (push) {
-               if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
                        evo_data(push, 0x85000000);
                        evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
                } else
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
                        evo_data(push, 0x85000000);
                        evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
@@ -918,11 +899,11 @@ nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
        u32 *push = evo_wait(mast, 16);
        if (push) {
-               if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, 0x05000000);
                } else
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, 0x05000000);
                        evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
@@ -973,13 +954,13 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
 
        push = evo_wait(mast, 6);
        if (push) {
-               if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, 0x00000000);
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, 0x40000000);
                } else
-               if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, 0x00000000);
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
@@ -1010,14 +991,14 @@ nv50_crtc_commit(struct drm_crtc *crtc)
 
        push = evo_wait(mast, 32);
        if (push) {
-               if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, nv_crtc->fb.handle);
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
                        evo_data(push, 0xc0000000);
                        evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
                } else
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
                        evo_data(push, nv_crtc->fb.handle);
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
@@ -1112,7 +1093,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 
        push = evo_wait(mast, 64);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
                        evo_data(push, 0x00800000 | mode->clock);
                        evo_data(push, (ilace == 2) ? 2 : 0);
@@ -1205,7 +1186,7 @@ nv50_crtc_lut_load(struct drm_crtc *crtc)
                u16 g = nv_crtc->lut.g[i] >> 2;
                u16 b = nv_crtc->lut.b[i] >> 2;
 
-               if (disp->disp->oclass < NVD0_DISP_CLASS) {
+               if (disp->disp->oclass < GF110_DISP) {
                        writew(r + 0x0000, lut + (i * 0x08) + 0);
                        writew(g + 0x0000, lut + (i * 0x08) + 2);
                        writew(b + 0x0000, lut + (i * 0x08) + 4);
@@ -1523,7 +1504,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
        push = evo_wait(mast, 8);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        u32 syncs = 0x00000000;
 
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -1572,7 +1553,7 @@ nv50_dac_disconnect(struct drm_encoder *encoder)
 
                push = evo_wait(mast, 4);
                if (push) {
-                       if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+                       if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                                evo_mthd(push, 0x0400 + (or * 0x080), 1);
                                evo_data(push, 0x00000000);
                        } else {
@@ -1849,7 +1830,7 @@ nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
        struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
        u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
        if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
                        evo_data(push, (nv_encoder->ctrl = temp));
                } else {
@@ -1979,7 +1960,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
 
        nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
 
-       if (nv50_vers(mast) >= NVD0_DISP_CLASS) {
+       if (nv50_vers(mast) >= GF110_DISP) {
                u32 *push = evo_wait(mast, 3);
                if (push) {
                        u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
@@ -2154,7 +2135,7 @@ nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
        push = evo_wait(mast, 8);
        if (push) {
-               if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+               if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                        u32 ctrl = (depth << 16) | (proto << 8) | owner;
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
                                ctrl |= 0x00001000;
@@ -2183,7 +2164,7 @@ nv50_pior_disconnect(struct drm_encoder *encoder)
 
                push = evo_wait(mast, 4);
                if (push) {
-                       if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
+                       if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
                                evo_mthd(push, 0x0700 + (or * 0x040), 1);
                                evo_data(push, 0x00000000);
                        }
@@ -2380,12 +2361,12 @@ nv50_fb_ctor(struct drm_framebuffer *fb)
                 return -EINVAL;
        }
 
-       if (disp->disp->oclass < NV84_DISP_CLASS) {
+       if (disp->disp->oclass < G82_DISP) {
                nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
                                            (fb->pitches[0] | 0x00100000);
                nv_fb->r_format |= kind << 16;
        } else
-       if (disp->disp->oclass < NVD0_DISP_CLASS) {
+       if (disp->disp->oclass < GF110_DISP) {
                nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
                                           (fb->pitches[0] | 0x00100000);
        } else {
@@ -2497,7 +2478,7 @@ nv50_display_create(struct drm_device *dev)
                goto out;
 
        /* create crtc objects to represent the hw heads */
-       if (disp->disp->oclass >= NVD0_DISP_CLASS)
+       if (disp->disp->oclass >= GF110_DISP)
                crtcs = nvif_rd32(device, 0x022448);
        else
                crtcs = 2;

diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index b0998e7a5396674b769d13c9017b7f65a14103f2..15dc6a35589e46c69042d0d8ff1c904f3a7d62e4 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -12,6 +12,8 @@
 #define NV_DMA_TO_MEMORY                                             0x00000003
 #define NV_DMA_IN_MEMORY                                             0x0000003d
 
+#define NV04_DISP                                                    0x00000046
+
 #define NV03_CHANNEL_DMA                                             0x0000006b
 #define NV10_CHANNEL_DMA                                             0x0000006e
 #define NV17_CHANNEL_DMA                                             0x0000176e
@@ -24,6 +26,53 @@
 #define FERMI_CHANNEL_GPFIFO                                         0x0000906f
 #define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
 
+#define NV50_DISP                                                    0x00005070
+#define G82_DISP                                                     0x00008270
+#define GT200_DISP                                                   0x00008370
+#define GT214_DISP                                                   0x00008570
+#define GT206_DISP                                                   0x00008870
+#define GF110_DISP                                                   0x00009070
+#define GK104_DISP                                                   0x00009170
+#define GK110_DISP                                                   0x00009270
+#define GM107_DISP                                                   0x00009470
+
+#define NV50_DISP_CURSOR                                             0x0000507a
+#define G82_DISP_CURSOR                                              0x0000827a
+#define GT214_DISP_CURSOR                                            0x0000857a
+#define GF110_DISP_CURSOR                                            0x0000907a
+#define GK104_DISP_CURSOR                                            0x0000917a
+
+#define NV50_DISP_OVERLAY                                            0x0000507b
+#define G82_DISP_OVERLAY                                             0x0000827b
+#define GT214_DISP_OVERLAY                                           0x0000857b
+#define GF110_DISP_OVERLAY                                           0x0000907b
+#define GK104_DISP_OVERLAY                                           0x0000917b
+
+#define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
+#define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
+#define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
+#define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
+#define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
+#define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
+#define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c
+
+#define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
+#define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
+#define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
+#define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
+#define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
+#define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
+#define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
+#define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
+#define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
+
+#define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
+#define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
+#define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
+#define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
+#define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
+#define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e
+
 
 /*******************************************************************************
  * client
@@ -403,4 +452,41 @@ struct nv50_disp_pior_pwr_v0 {
        __u8  pad03[5];
 };
 
+/* core */
+struct nv50_disp_core_channel_dma_v0 {
+       __u8  version;
+       __u8  pad01[3];
+       __u32 pushbuf;
+};
+
+/* cursor immediate */
+struct nv50_disp_cursor_v0 {
+       __u8  version;
+       __u8  head;
+       __u8  pad02[6];
+};
+
+/* base */
+struct nv50_disp_base_channel_dma_v0 {
+       __u8  version;
+       __u8  pad01[2];
+       __u8  head;
+       __u32 pushbuf;
+};
+
+/* overlay */
+struct nv50_disp_overlay_channel_dma_v0 {
+       __u8  version;
+       __u8  pad01[2];
+       __u8  head;
+       __u32 pushbuf;
+};
+
+/* overlay immediate */
+struct nv50_disp_overlay_v0 {
+       __u8  version;
+       __u8  head;
+       __u8  pad02[6];
+};
+
 #endif