arm64: dts: Add L2 cache topology to Hi6220

This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 0c8df8a93dbe03b5a271ba99b9150465ee88d527..189d21541f9c8082eea7826ee8df624bc17d8d49 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -83,6 +83,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER0_L2>;
                        clocks = <&stub_clock 0>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cooling-min-level = <4>;
@@ -97,6 +98,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER0_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -106,6 +108,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER0_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -115,6 +118,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER0_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -124,6 +128,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER1_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -133,6 +138,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER1_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -142,6 +148,7 @@
                        device_type = "cpu";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER1_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
@@ -151,9 +158,18 @@
                        device_type = "cpu";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       next-level-cache = <&CLUSTER1_L2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                };
+
+               CLUSTER0_L2: l2-cache0 {
+                       compatible = "cache";
+               };
+
+               CLUSTER1_L2: l2-cache1 {
+                       compatible = "cache";
+               };
        };
 
        cpu_opp_table: cpu_opp_table {