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drm/exynos/hdmi: add 297MHz pixel clock support
author
Andrzej Hajda
<a.hajda@samsung.com>
Fri, 20 Jan 2017 06:52:19 +0000
(07:52 +0100)
committer
Inki Dae
<inki.dae@samsung.com>
Tue, 7 Feb 2017 04:52:49 +0000
(13:52 +0900)
297MHz is used by Ultra HD modes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
drivers/gpu/drm/exynos/exynos_hdmi.c
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diff --git
a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5ed8b1effe71203d23808072d03534f578fdfb78..bef8965c9f5371c020b2ffe6d298d185c433867d 100644
(file)
--- a/
drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/
drivers/gpu/drm/exynos/exynos_hdmi.c
@@
-587,6
+587,15
@@
static const struct hdmiphy_config hdmiphy_5433_configs[] = {
0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
},
},
+ {
+ .pixel_clock = 297000000,
+ .conf = {
+ 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
+ 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
+ 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+ 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+ },
+ },
};
static const char * const hdmi_clk_gates4[] = {