drm/i915/psr: set PSR_MASK bits for deep sleep

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

v4: rebase

v5: rebase

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484267484-21843-1-git-send-email-vathsala.nagaraju@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9c1ccd4bc77058b92e5513a3bf2238067f854ed..ca76887120ee86f4f24527c2653fd3dc0585223b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK                0xffffff
 
 #define EDP_PSR_DEBUG_CTL              _MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP      (1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP     (1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD       (1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL                   _MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE              (1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf<<4)
 #define   EDP_PSR2_IDLE_MASK           0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 935402e0f786feb23fe953753b0ea1d46dca8e0a..3611c42bff7ff1a4ba48aa0188f983facab7e805 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,7 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
        /* FIXME: selective update is probably totally broken because it doesn't
         * mesh at all with our frontbuffer tracking. And the hw alone isn't
         * good enough. */
-       val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+       val |= EDP_PSR2_ENABLE |
+               EDP_SU_TRACK_ENABLE |
+               EDP_FRAMES_BEFORE_SU_ENTRY;
 
        if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
                val |= EDP_PSR2_TP2_TIME_2500;
@@ -512,20 +514,28 @@ void intel_psr_enable(struct intel_dp *intel_dp)
                        if (dev_priv->psr.y_cord_support)
                                chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
                        I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
+                       I915_WRITE(EDP_PSR_DEBUG_CTL,
+                                  EDP_PSR_DEBUG_MASK_MEMUP |
+                                  EDP_PSR_DEBUG_MASK_HPD |
+                                  EDP_PSR_DEBUG_MASK_LPSP |
+                                  EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+                                  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
                } else {
                        /* set up vsc header for psr1 */
                        hsw_psr_setup_vsc(intel_dp);
+                       /*
+                        * Per Spec: Avoid continuous PSR exit by masking MEMUP
+                        * and HPD. also mask LPSP to avoid dependency on other
+                        * drivers that might block runtime_pm besides
+                        * preventing  other hw tracking issues now we can rely
+                        * on frontbuffer tracking.
+                        */
+                       I915_WRITE(EDP_PSR_DEBUG_CTL,
+                                  EDP_PSR_DEBUG_MASK_MEMUP |
+                                  EDP_PSR_DEBUG_MASK_HPD |
+                                  EDP_PSR_DEBUG_MASK_LPSP);
                }
 
-               /*
-                * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-                * Also mask LPSP to avoid dependency on other drivers that
-                * might block runtime_pm besides preventing other hw tracking
-                * issues now we can rely on frontbuffer tracking.
-                */
-               I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-                          EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
-
                /* Enable PSR on the panel */
                hsw_psr_enable_sink(intel_dp);