Signed-off-by: Len Brown <len.brown@intel.com>
/* Idle State Flags */
#define CPUIDLE_FLAG_TIME_VALID (0x01) /* is residency time measurable? */
#define CPUIDLE_FLAG_CHECK_BM (0x02) /* BM activity will exit state */
-#define CPUIDLE_FLAG_SHALLOW (0x20) /* low latency, minimal savings */
-#define CPUIDLE_FLAG_BALANCED (0x40) /* medium latency, moderate savings */
-#define CPUIDLE_FLAG_DEEP (0x80) /* high latency, large savings */
#define CPUIDLE_FLAG_IGNORE (0x100) /* ignore during this idle period */
#define CPUIDLE_FLAG_TLB_FLUSHED (0x200) /* tlb will be flushed */