MIPS: Clear Status IPL field when using EIC
authorPaul Burton <paul.burton@imgtec.com>
Tue, 17 May 2016 14:31:04 +0000 (15:31 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 28 May 2016 10:35:02 +0000 (12:35 +0200)
When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced. Without doing so we default to arbitrarily ignoring all or
some subset of interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Joe Perches <joe@perches.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13272/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/irq.c

index 8eb5af8059641311bfeb63b25454778a0f7bddde..f25f7eab7307e92ec22a17228a7afba68cd5327c 100644 (file)
@@ -54,6 +54,9 @@ void __init init_IRQ(void)
        for (i = 0; i < NR_IRQS; i++)
                irq_set_noprobe(i);
 
+       if (cpu_has_veic)
+               clear_c0_status(ST0_IM);
+
        arch_init_irq();
 }