ARM: shmobile: r8a7790: add EtherAVB clocks
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Mon, 15 Jun 2015 23:42:42 +0000 (02:42 +0300)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 6 Jul 2015 00:33:31 +0000 (09:33 +0900)
Add the EtherAVB clock to the R8A7790 device tree.

Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index 51ab8865ea37dc899ddd2fe0948c0d76b6582263..feb4652ed4b2d479aa0ad0f97d1c6b5bdb21e1be 100644 (file)
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
                        clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
-                                <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
+                                <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
+                                <&zs_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
-                               R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
+                               R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
+                               R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
                                R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
                        >;
                        clock-output-names =
-                               "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
-                               "sata1", "sata0";
+                               "mlb", "vin3", "vin2", "vin1", "vin0",
+                               "etheravb", "ether", "sata1", "sata0";
                };
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
index ff7ca3584e1695898eb5ddd825cfc2d7a68c46ff..e119ef372ba39754641ac5719b3487a2ba980d20 100644 (file)
 #define R8A7790_CLK_VIN2               9
 #define R8A7790_CLK_VIN1               10
 #define R8A7790_CLK_VIN0               11
+#define R8A7790_CLK_ETHERAVB           12
 #define R8A7790_CLK_ETHER              13
 #define R8A7790_CLK_SATA1              14
 #define R8A7790_CLK_SATA0              15