clk: stm32f4: Add SAI clocks

This patch introduces SAI clocks for stm32f4 socs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index fde883a733947168fdc6446c89255e19cb68541d..387e531973606e5104b19500dbbf45f35007f2bb 100644 (file)
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -948,6 +948,9 @@ static const char *lcd_parent[1] = { "pllsai-r-div" };
 
 static const char *i2s_parents[2] = { "plli2s-r", NULL };
 
+static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
+       "no-clock" };
+
 struct stm32_aux_clk {
        int idx;
        const char *name;
@@ -983,6 +986,18 @@ static const struct stm32_aux_clk stm32f429_aux_clk[] = {
                NO_GATE, 0,
                CLK_SET_RATE_PARENT
        },
+       {
+               CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
+               STM32F4_RCC_DCKCFGR, 20, 3,
+               STM32F4_RCC_APB2ENR, 22,
+               CLK_SET_RATE_PARENT
+       },
+       {
+               CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
+               STM32F4_RCC_DCKCFGR, 22, 3,
+               STM32F4_RCC_APB2ENR, 22,
+               CLK_SET_RATE_PARENT
+       },
 };
 
 static const struct stm32f4_clk_data stm32f429_clk_data = {
@@ -1115,6 +1130,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
        i2s_in_clk = of_clk_get_parent_name(np, 1);
 
        i2s_parents[1] = i2s_in_clk;
+       sai_parents[2] = i2s_in_clk;
 
        clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
                        16000000, 160000);