prop->he = 128;
}
}
- /* under 4k2k50/60hz 10/12bit mode, */
+ /* bug fix for tl1:under 4k2k50/60hz 10/12bit mode, */
/* hdmi out clk will overstep the max sample rate of vdin */
/* so need discard the last line data to avoid display err */
/* 420 : hdmiout clk = pixel clk * 2 */
/* 422 : hdmiout clk = pixel clk * colordepth / 8 */
/* 444 : hdmiout clk = pixel clk */
- if ((rx.pre.colordepth > E_COLORDEPTH_8) &&
- (prop->fps > 49) &&
- ((sig_fmt == TVIN_SIG_FMT_HDMI_4096_2160_00HZ) ||
- (sig_fmt == TVIN_SIG_FMT_HDMI_3840_2160_00HZ)))
- prop->ve = 1;
+ if (rx.hdmirxdev->data->chip_id < CHIP_ID_TL1) {
+ /* tl1 need verify this bug */
+ if ((rx.pre.colordepth > E_COLORDEPTH_8) &&
+ (prop->fps > 49) &&
+ ((sig_fmt == TVIN_SIG_FMT_HDMI_4096_2160_00HZ) ||
+ (sig_fmt == TVIN_SIG_FMT_HDMI_3840_2160_00HZ)))
+ prop->ve = 1;
+ }
}
/*
{
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* allocate buffer */
- rx.empbuff.storeA = kmalloc(EMP_BUFFER_SIZE, GFP_KERNEL);
+ if (!rx.empbuff.storeA)
+ rx.empbuff.storeA =
+ kmalloc(EMP_BUFFER_SIZE, GFP_KERNEL);
+ else
+ rx_pr("malloc emp buffer err\n");
+
if (rx.empbuff.storeA)
rx.empbuff.storeB =
rx.empbuff.storeA + (EMP_BUFFER_SIZE >> 1);
rx.empbuff.pg_addr,
EMP_BUFFER_SIZE >> PAGE_SHIFT);
rx.empbuff.pg_addr = 0;
+ rx_pr("release emp data buffer\n");
}
} else {
dma_release_from_contiguous(dev, rx.empbuff.pg_addr,
TMDS_BUFFER_SIZE >> PAGE_SHIFT);
rx.empbuff.pg_addr = 0;
+ rx_pr("release pre tmds data buffer\n");
}
- /* allocate buffer for tmds to ddr */
+ /* allocate tmds data buffer */
rx.empbuff.pg_addr =
dma_alloc_from_contiguous(dev,
TMDS_BUFFER_SIZE >> PAGE_SHIFT, 0);
if (rx.empbuff.pg_addr)
rx.empbuff.p_addr_a =
page_to_phys(rx.empbuff.pg_addr);
-
+ else
+ rx_pr("allocate tmds data buff fail\n");
rx.empbuff.dump_mode = DUMP_MODE_TMDS;
rx_pr("buffa paddr=0x%x\n", rx.empbuff.p_addr_a);
+ rx.empbuff.tmdspktcnt = 0;
+ }
+}
+
+void rx_emp_data_capture(void)
+{
+ /* data to terminal or save a file */
+ struct file *filp = NULL;
+ loff_t pos = 0;
+ void *buf = NULL;
+ char *path = "/data/emp_data.bin";
+ unsigned int offset = 0;
+ mm_segment_t old_fs = get_fs();
+
+ set_fs(KERNEL_DS);
+ filp = filp_open(path, O_RDWR|O_CREAT, 0666);
+
+ if (IS_ERR(filp)) {
+ pr_info("create %s error.\n", path);
+ return;
}
+
+ /*start buffer address*/
+ buf = rx.empbuff.ready;
+ /*write size*/
+ offset = rx.empbuff.emppktcnt * 32;
+ vfs_write(filp, buf, offset, &pos);
+ pr_info("write from 0x%x to 0x%x to %s.\n",
+ 0, 0 + offset, path);
+ vfs_fsync(filp, 0);
+ filp_close(filp, NULL);
+ set_fs(old_fs);
}
+void rx_tmds_data_capture(void)
+{
+ /* data to terminal or save a file */
+ struct file *filp = NULL;
+ loff_t pos = 0;
+ void *buf = NULL;
+ char *path = "/data/tmds_data.bin";
+ unsigned int offset = 0;
+ unsigned char *src_v_addr;
+ mm_segment_t old_fs = get_fs();
+
+ set_fs(KERNEL_DS);
+ filp = filp_open(path, O_RDWR|O_CREAT, 0666);
+
+ if (IS_ERR(filp)) {
+ pr_info("create %s error.\n", path);
+ return;
+ }
+
+ /* p addr to v addr for cpu access */
+ src_v_addr = phys_to_virt(rx.empbuff.p_addr_a);
+
+ /*start buffer address*/
+ buf = src_v_addr;
+ /*write size*/
+ offset = (rx.empbuff.tmdspktcnt * 15)/4;/*pkt to bytes*/
+ vfs_write(filp, buf, offset, &pos);
+ pr_info("write from 0x%x to 0x%x to %s.\n",
+ 0, 0 + offset, path);
+ vfs_fsync(filp, 0);
+ filp_close(filp, NULL);
+ set_fs(old_fs);
+}
+
+
+
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
static void hdmirx_early_suspend(struct early_suspend *h)
{
clk_rate/1000000);
}
#endif
- hdevp->audmeas_clk = clk_get(&pdev->dev, "hdmirx_audmeas_clk");
- if (IS_ERR(hdevp->audmeas_clk))
- rx_pr("get audmeas_clk err\n");
- else {
- clk_set_parent(hdevp->audmeas_clk, fclk_div5_clk);
- clk_set_rate(hdevp->audmeas_clk, 200000000);
- clk_rate = clk_get_rate(hdevp->audmeas_clk);
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ hdevp->meter_clk = clk_get(&pdev->dev, "cts_hdmirx_meter_clk");
+ if (IS_ERR(hdevp->meter_clk))
+ rx_pr("get cts hdmirx meter clk err\n");
+ else {
+ clk_set_parent(hdevp->meter_clk, xtal_clk);
+ clk_set_rate(hdevp->meter_clk, 24000000);
+ clk_prepare_enable(hdevp->meter_clk);
+ clk_rate = clk_get_rate(hdevp->meter_clk);
+ }
+ } else {
+ hdevp->audmeas_clk = clk_get(&pdev->dev, "hdmirx_audmeas_clk");
+ if (IS_ERR(hdevp->audmeas_clk))
+ rx_pr("get audmeas_clk err\n");
+ else {
+ clk_set_parent(hdevp->audmeas_clk, fclk_div5_clk);
+ clk_set_rate(hdevp->audmeas_clk, 200000000);
+ clk_rate = clk_get_rate(hdevp->audmeas_clk);
+ }
}
pd_fifo_buf = kmalloc_array(1, PFIFO_SIZE * sizeof(uint32_t),
struct clk *aud_out_clk;
struct clk *esm_clk;
struct clk *skp_clk;
+ struct clk *meter_clk;
const struct meson_hdmirx_data *data;
};
uint32_t pll_rate;
uint32_t clk_rate;
uint32_t phy_bw;
+ ulong timestap;
};
struct emp_buff {
void __iomem *storeA;
void __iomem *storeB;
void __iomem *ready;
- unsigned int emppktcnt;
unsigned long irqcnt;
+ unsigned int emppktcnt;
+ unsigned int tmdspktcnt;
};
struct rx_s {
extern int hdmirx_debug(const char *buf, int size);
extern void dump_reg(void);
extern void dump_edid_reg(void);
-extern void dump_state(unsigned char enable);
extern void rx_debug_loadkey(void);
extern void rx_debug_load22key(void);
extern int rx_debug_wr_reg(const char *buf, char *tmpbuf, int i);
{
unsigned long flags;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
- /* ??? */
+ /* need to do for tl1 ... */
+
+
} else {
spin_lock_irqsave(®_rw_lock, flags);
wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_ctrl_port+offset, data);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* sqofclk */
- clk = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_STAT) & 0x80000000;
+ clk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
} else {
/* phy clk */
clk = hdmirx_rd_phy(PHY_MAINFSM_STATUS1) & 0x100;
int error = 0;
int data32 = 0;
+ data32 |= 1 << 12; /* emp_err_filter, tl1*/
data32 |= 1 << 9; /* amp_err_filter */
data32 |= 1 << 8; /* isrc_err_filter */
data32 |= 1 << 7; /* gmd_err_filter */
data32 = hdmirx_rd_dwc(DWC_PDEC_CTRL);
data32 |= 1 << 31; /* PFIFO_STORE_FILTER_EN */
- data32 |= 0 << 30; /* Enable packet FIFO to store EMP */
+ data32 |= 1 << 30; /* Enable packet FIFO store EMP pkt*/
data32 |= 1 << 4; /* PD_FIFO_WE */
+ data32 |= 0 << 1; /* emp pkt rev int,0:last 1:every */
data32 |= 1 << 0; /* PDEC_BCH_EN */
data32 &= (~GCP_GLOBAVMUTE);
data32 |= GCP_GLOBAVMUTE_EN << 15;
else
hdmirx_wr_top(TOP_ACR_CNTL2, data32);
- data32 = 0;
- /* bit4: hpd override, bit5: hpd reverse */
- data32 |= 1 << 4;
- if (rx.chip_id == CHIP_ID_GXTVBB)
- data32 |= 0 << 5;
- else
- data32 |= 1 << 5;
- /* pull down all the hpd */
- hdmirx_wr_top(TOP_HPD_PWR5V, data32);
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
data32 = hdmirx_rd_dwc(DWC_HDCP_CTRL);
/* 0: Original behaviour */
/* 1: Balance path delay between HDCP14 and HDCP22. */
data32 |= 1 << 26; /* 1.4 & 2.2 */
hdmirx_wr_dwc(DWC_HDCP_CTRL, data32);
+
+ /* Configure channel switch */
+ data32 = 0;
+ data32 |= (0 << 4); /* [ 4] valid_always*/
+ data32 |= (7 << 0); /* [3:0] decoup_thresh*/
+ hdmirx_wr_top(TOP_CHAN_SWITCH_1, data32);
+
+ data32 = 0;
+ data32 |= (2 << 28); /* [29:28] source_2 */
+ data32 |= (1 << 26); /* [27:26] source_1 */
+ data32 |= (0 << 24); /* [25:24] source_0 */
+ hdmirx_wr_top(TOP_CHAN_SWITCH_0, data32);
+
+ /* Configure TMDS algin */
+ data32 = 0;
+ hdmirx_wr_top(TOP_TMDS_ALIGN_CNTL0, data32);
+ data32 = 0;
+ hdmirx_wr_top(TOP_TMDS_ALIGN_CNTL1, data32);
+
+ /* Enable channel output */
+ data32 = hdmirx_rd_top(TOP_CHAN_SWITCH_0);
+ hdmirx_wr_top(TOP_CHAN_SWITCH_0, data32 | (1<<0));
+
+ /* configure cable clock measure */
+ data32 = 0;
+ data32 |= (1 << 28); /* [31:28] meas_tolerance */
+ data32 |= (8192 << 0); /* [23: 0] ref_cycles */
+ hdmirx_wr_top(TOP_METER_CABLE_CNTL, data32);
}
+
+ /* configure hdmi clock measure */
+ data32 = 0;
+ data32 |= (1 << 28); /* [31:28] meas_tolerance */
+ data32 |= (8192 << 0); /* [23: 0] ref_cycles */
+ hdmirx_wr_top(TOP_METER_HDMI_CNTL, data32);
+
+ data32 = 0;
+ /* bit4: hpd override, bit5: hpd reverse */
+ data32 |= 1 << 4;
+ if (rx.chip_id == CHIP_ID_GXTVBB)
+ data32 |= 0 << 5;
+ else
+ data32 |= 1 << 5;
+ /* pull down all the hpd */
+ hdmirx_wr_top(TOP_HPD_PWR5V, data32);
return err;
}
void rx_set_term_enable(bool enable)
{
- hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1, PHY_TERM_OVERRIDE, enable);
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ /* need to do : for tl1 */
+ } else
+ hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1,
+ PHY_TERM_OVERRIDE, enable);
}
void rx_set_term_value(unsigned char port, bool value)
{
+ unsigned int data32;
+
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* need to do : for tl1 */
-
+ data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
+ if (port < E_PORT3) {
+ if (value)
+ data32 |= (1 << port);
+ else
+ data32 &= ~(1 << port);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+ } else if (port == ALL_PORTS) {
+ if (value)
+ data32 |= 0x7;
+ else
+ data32 &= 0xfffffff8;
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+ } else
+ rx_pr("%s port num overflow\n", __func__);
} else {
if (port < E_PORT_NUM) {
if (value)
void rx_force_rxsense_cfg(uint8_t level)
{
unsigned int term_ovr_value;
+ unsigned int data32;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
- /* need to do: for tl1 ...*/
-
+ /* enable terminal connect */
+ data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
+ if (level) {
+ if (disable_port_en)
+ term_ovr_value =
+ (~(1 << disable_port_num)) & 0x7;
+ else
+ term_ovr_value = 0x7;
+ data32 |= term_ovr_value;
+ } else {
+ data32 &= 0xfffffff8;
+ }
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
} else {
if (level) {
if (disable_port_en)
data32 |= acr_mode << 0;
hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32);
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ data32 = 0;
+ data32 |= 0 << 2;/*meas_mode*/
+ data32 |= 1 << 1;/*enable*/
+ data32 |= 1 << 0;/*reset*/
+ if (acr_mode)
+ data32 |= 2 << 16;/*aud pll*/
+ else
+ data32 |= 500 << 16;/*acr*/
+ hdmirx_wr_top(TOP_AUDMEAS_CTRL, data32);
+ hdmirx_wr_top(TOP_AUDMEAS_CYCLES_M1, 65535);
+ /*start messure*/
+ hdmirx_wr_top(TOP_AUDMEAS_CTRL, data32 & (~0x1));
+ }
+
/*
*recover to default value, bit[27:24]
*set aud_pll_lock filter
*/
void hdmirx_phy_init(void)
{
+ uint32_t data32;
+
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
- #ifdef K_BRINGUP_PTM
- return;
- #endif
/* give default value */
- aml_phy_bw_switch(100000, 0);
+ data32 = 0;
+ data32 |= rx.port << 2;
+ hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
+
+ aml_phy_bw_switch(148 * MHz, 0);/*100M,1:10*/
} else {
snps_phyg3_init();
}
tmp = rd_reg_hhi(HHI_VDAC_CNTL1);
wr_reg_hhi(HHI_VDAC_CNTL1, tmp|0x80);
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40000540);
- wr_reg_hhi(HHI_AUD_PLL_CNTL2, 0x00000000);
+ #if 0
+ /* use mpll */
+ tmp = 0;
+ tmp |= 2 << 2; /* 0:tmds_clk 1:ref_clk 2:mpll_clk */
+ wr_reg_hhi(HHI_AUD_PLL_CNTL2, tmp);
/* cntl3 2:0 000=1*cts 001=2*cts 010=4*cts 011=8*cts */
wr_reg_hhi(HHI_AUD_PLL_CNTL3, rx.physts.aud_div);
+ #else
+ /* use tmds clk */
+ tmp = 0;
+ tmp |= 0 << 2; /* 0:tmds_clk 1:ref_clk 2:mpll_clk */
+ wr_reg_hhi(HHI_AUD_PLL_CNTL2, tmp);
+ /* cntl3 2:0 000=1*cts 001=2*cts 010=4*cts 011=8*cts */
+ wr_reg_hhi(HHI_AUD_PLL_CNTL3, 0);
+ #endif
rx_pr("aud div=%d\n", rd_reg_hhi(HHI_AUD_PLL_CNTL3));
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x60000540);
rx_pr("audio pll lock:0x%x\n",
rd_reg_hhi(HHI_AUD_PLL_CNTL_I));
+ /*rx_audio_pll_sw_update();*/
} else {
/* disable pll, into reset mode */
External_Mute(1);
* tl1: have hdmi, cable clock
* other: have hdmi clock
*/
-unsigned int rx_get_clock(unsigned int clk_src)
+unsigned int rx_get_clock(enum measure_clk_top_e clk_src)
{
uint32_t clock = 0;
uint32_t tmp_data = 0;
uint32_t meas_cycles = 0;
+ uint32_t tmp_data2 = 0;
+ ulong audclk = 0;
- if (clk_src == K_MEASURE_SRC_HDMI_TMDSCLK)
+ if (clk_src == TOP_HDMI_TMDSCLK)
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
- else if (clk_src == K_MEASURE_SRC_HDMI_CABLECLK) {
+ else if (clk_src == TOP_HDMI_CABLECLK) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
tmp_data = hdmirx_rd_top(TOP_METER_CABLE_STAT);
+ } else if (clk_src == TOP_HDMI_AUDIOCLK) {
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ /*get audio clk*/
+ tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
+ tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
+ audclk = (tmp_data2 & 0xffff)|tmp_data;
+ if (tmp_data2 & (0x1 << 17))
+ audclk = (24000 * 65536) / ((audclk + 1)/1000);
+ else
+ rx_pr("audio clk measure fail\n");
+ }
+ return audclk;
} else
tmp_data = 0;
/* measure stable */
if (tmp_data & 0x80000000) {
meas_cycles = tmp_data & 0xffffff;
- clock = (2930 * meas_cycles);
+ clock = (2930 * meas_cycles);/*Hz*/
/*clock = (24000000 * meas_cycles) / 8192;*/
/*rx_pr("hdmi_clk cycle cnt=%d,frq=%d\n",cycle_cnt,clock);*/
}
-
- hdmirx_wr_top(TOP_SW_RESET, 0x6);
+ /*reset hdmi,cable clk meter*/
+ hdmirx_wr_top(TOP_SW_RESET, 0x60);
hdmirx_wr_top(TOP_SW_RESET, 0x0);
return clock;
}
/*
* function - get clk related with hdmirx
*/
-unsigned int rx_measure_clock(enum measure_clk_src clksrc)
+unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
{
unsigned int clock = 0;
if (clksrc == MEASURE_CLK_CABLE) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
clock = meson_clk_measure(30);
- /*clock = rx_get_clock(K_MEASURE_SRC_HDMI_CABLECLK);*/
+ /*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
}
} else if (clksrc == MEASURE_CLK_TMDS) {
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
hdmirx_rd_top(i + 3));
i = i + 4;
}
- rx_pr("\n***PHY registers***\n");
- rx_pr("[addr ] addr + 0x0,");
- rx_pr("addr + 0x1,addr + 0x2,");
- rx_pr("addr + 0x3\n");
- for (i = 0; i <= 0x9a;) {
- rx_pr("[0x%-3x]", i);
- rx_pr("0x%-8x", hdmirx_rd_phy(i));
+
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ rx_pr("[0x%-3x]", 0x28);
+ rx_pr("0x%-8x", hdmirx_rd_top(0x28));
rx_pr("0x%-8x,0x%-8x,0x%-8x\n",
- hdmirx_rd_phy(i + 1),
- hdmirx_rd_phy(i + 2),
- hdmirx_rd_phy(i + 3));
- i = i + 4;
+ hdmirx_rd_top(0x29),
+ hdmirx_rd_top(0x2a),
+ hdmirx_rd_top(0x2b));
}
+
+ if (rx.hdmirxdev->data->chip_id < CHIP_ID_TL1) {
+ rx_pr("\n***PHY registers***\n");
+ rx_pr("[addr ] addr + 0x0,");
+ rx_pr("addr + 0x1,addr + 0x2,");
+ rx_pr("addr + 0x3\n");
+ for (i = 0; i <= 0x9a;) {
+ rx_pr("[0x%-3x]", i);
+ rx_pr("0x%-8x", hdmirx_rd_phy(i));
+ rx_pr("0x%-8x,0x%-8x,0x%-8x\n",
+ hdmirx_rd_phy(i + 1),
+ hdmirx_rd_phy(i + 2),
+ hdmirx_rd_phy(i + 3));
+ i = i + 4;
+ }
+ } else if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ /* dump phy register */
+ rx_pr("\n***AML PHY registers***\n");
+ for (i = HHI_HDMIRX_APLL_CNTL0;
+ i <= HHI_HDMIRX_APLL_CNTL4;) {
+ rx_pr("apll cntl 0x%x:0x%8x\n", i >> 2, rd_reg_hhi(i));
+ i = i + 4;
+ }
+
+ rx_pr("MISC_CNTL0:0x%8x\n",
+ rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0));
+ rx_pr("MISC_CNTL1:0x%8x\n",
+ rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1));
+
+ for (i = HHI_HDMIRX_PHY_MISC_CNTL2;
+ i <= HHI_HDMIRX_PHY_DCHD_CNTL2;) {
+ rx_pr("phy 0x%x:0x%8x\n", i >> 2, rd_reg_hhi(i));
+ i = i + 4;
+ }
+ rx_pr("MISC_STAT0:0x%8x\n",
+ hdmirx_rd_top(TOP_MISC_STAT0));
+ rx_pr("DCHD_STAT:0x%8x\n",
+ rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT));
+ }
+
rx_pr("\n**Controller registers**\n");
rx_pr("[addr ] addr + 0x0,");
rx_pr("addr + 0x4, addr + 0x8,");
/* print_reg(0x3040, 0x3054); */
/* print_reg(0x3080, 0x3118); */
/* print_reg(0x3200, 0x32e4); */
-
}
void dump_edid_reg(void)
return ret;
}
-/*
- * for tl1 phy function
- */
-struct apll_param apll_tab[] = {
- /* bw M, N, od, div, od2, od2_div */
- {apll_bw_24_40, 160, 1, 0x5, 32, 0x4, 16},
- {apll_bw_40_80, 80, 1, 0x4, 16, 0x3, 8},
- {apll_bw_80_150, 40, 1, 0x3, 8, 0x2, 4},
- {apll_bw_150_300, 0, 2, 0x2, 4, 0x1, 2},
- {apll_bw_300_600, 40, 1, 0x1, 2, 0x0, 1},
- {apll_bw_null, 40, 1, 0x3, 8, 0x2, 4},
-};
-
unsigned int aml_check_clk_bandwidth(unsigned int cableclk,
unsigned int clkrate)
{
unsigned int bw;
unsigned int cab_clk = cableclk;
+ /*rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate);*/
/* 1:40 */
if (clkrate)
cab_clk = cableclk << 2;
/* 1:10 */
- if (cab_clk < 40000000)
+ if (cab_clk < (40 * MHz))
bw = apll_bw_24_40;
- else if (cab_clk < 80000000)
+ else if (cab_clk < (80 * MHz))
bw = apll_bw_40_80;
- else if (cab_clk < 150000000)
+ else if (cab_clk < (150 * MHz))
bw = apll_bw_80_150;
- else if (cab_clk < 300000000)
+ else if (cab_clk < (300 * MHz))
bw = apll_bw_150_300;
- else if (cab_clk < 600000000)
+ else if (cab_clk < (600 * MHz))
bw = apll_bw_300_600;
else {
bw = apll_bw_80_150;
{
unsigned int data32;
static unsigned int cnt;
+ unsigned int term_value =
+ hdmirx_rd_top(TOP_HPD_PWR5V);
rx_pr("init phy port %d, bw:%d\n", rx.port, bw);
if (bw == apll_bw_null) {
return;
} else if (bw <= apll_bw_24_40) {
- /* set port number and enable terminal connect */
- data32 = 0x30034078;
- data32 |= (1 << rx.port);
+ /* enable terminal connect */
+ data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
- /* channel reset */
- data32 = 0x300347f8;
- data32 |= (1 << rx.port);
+ /* data channel and common block reset */
+ data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
rx_pr("MISC_CNTL0=0x%x\n", data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
- wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);/*en arc*/
/* reset and select data port */
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e013130);
} else if (bw <= apll_bw_40_80) {
- /* set port number and enable terminal connect */
- data32 = 0x30034078;
- data32 |= (1 << rx.port);
+ /* enable terminal connect */
+ data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
- /* channel reset */
- data32 = 0x300347f8;
- data32 |= (1 << rx.port);
+ /* data channel and common block reset */
+ data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
rx_pr("MISC_CNTL0=0x%x\n", data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
- wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);
/* reset and select data port */
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
}
} else if (bw <= apll_bw_80_150) {
//phy default setting
- /* set port number and enable terminal connect */
- data32 = 0x30034078 | (1 << rx.port);
+ /* enable terminal connect */
+ data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
- /* channel reset */
- data32 = 0x300347f8 | (1 << rx.port);
+ /* data channel and common block reset */
+ data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
rx_pr("MISC_CNTL0=0x%x\n", data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
- wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);
/* reset and select data port */
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
}
} else if (bw <= apll_bw_150_300) {
/* 3G */
- /* set port number and enable terminal connect */
- data32 = 0x30034078 | (1 << rx.port);
+ /* enable terminal connect */
+ data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
- /* channel reset */
- data32 = 0x300347f8 | (1 << rx.port);
+ /* data channel and common block reset */
+ data32 |= 0xf << 7;
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
rx_pr("MISC_CNTL0=0x%x\n", data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
- wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);
/* reset and select data port */
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
data32 |= (1 << 11);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
udelay(5);
- wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000242);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000042);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x0800c202);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x0100fc31);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00020000);
} else {
/*6G*/
+ /* enable terminal connect */
+ data32 = 0x30034078|(term_value & 0x7);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+ /* data channel and common block reset */
+ data32 |= 0xf << 7;
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
+ rx_pr("MISC_CNTL0=0x%x\n", data32);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);
+ /* reset and select data port */
+ data32 = 0x00000010;
+ data32 |= ((1 << rx.port) << 6);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
+ /* release reset */
+ data32 |= (1 << 11);
+ wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
+ udelay(5);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000082);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x06000000);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x01004451);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x006c0041);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e080810);
+ udelay(5);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e480810);
+ udelay(1);
+ wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00180000);
}
cnt++;
}
udelay(5);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00020000);
}
+ rx_pr("set eq >>>>>\n");
}
-void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cableclk)
+/*
+ * for tl1 phy function
+ */
+struct apll_param apll_tab[] = {
+ /*od for tmds: 2/4/8/16/32*/
+ /*od2 for audio: 1/2/4/8/16*/
+ /* bw M, N, od, od_div, od2, od2_div */
+ {apll_bw_24_40, 160, 1, 0x5, 32, 0x3, 8},/*tmdsx4*/
+ {apll_bw_40_80, 80, 1, 0x4, 16, 0x3, 8},/*tmdsx2*/
+ {apll_bw_80_150, 40, 1, 0x3, 8, 0x3, 8},/*tmds*/
+ {apll_bw_150_300, 40, 2, 0x2, 4, 0x2, 4},/*tmds*/
+ {apll_bw_300_600, 40, 1, 0x1, 2, 0x1, 2},/*tmds*/
+ {apll_bw_null, 40, 1, 0x3, 8, 0x3, 8},
+};
+
+void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
{
unsigned int M, N;
unsigned int od, od_div;
unsigned int aud_pll_out;
unsigned int data, data2;
unsigned int aud_div;
+ unsigned int cableclk = cable_clk / KHz;
- rx_pr("bw:%d, clkrate:%d\n", bandwidth, cableclk);
+ rx_pr("bw:%d, cableclk:%d\n", bandwidth, cableclk);
od_div = apll_tab[bw].od_div;
od = apll_tab[bw].od;
M = apll_tab[bw].M;
od2_div = apll_tab[bw].od2_div;
od2 = apll_tab[bw].od2;
- vco_clk = (cableclk * M) / N;
- if ((vco_clk < 2970000) || (vco_clk > 6000000))
+ vco_clk = (cableclk * M) / N; /*KHz*/
+ if ((vco_clk < (2970 * KHz)) || (vco_clk > (6000 * KHz)))
rx_pr("err: M=%d,N=%d,vco_clk=%d\n", M, N, vco_clk);
- apll_out = (((cableclk * M)/N)/od_div)/5;
+ /*tmds clk out*/
+ apll_out = (vco_clk/od_div)/5;
rx_pr("M=%d,N=%d,od=%d,od_div=%d\n", M, N, od, od_div);
rx_pr("apll_out=%d, vco_clk=%d\n", apll_out, vco_clk);
rx_pr("od2=%d, od2_div=%d\n", od2, od2_div);
unsigned int tmds_align;
tmvds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01;
- sqofclk = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_STAT) & 0x80000000;
+ sqofclk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000;
tmds_align = hdmirx_rd_top(TOP_TMDS_ALIGN_STAT) & 0x3f000000;
if (tmvds_valid && sqofclk && pll_lock &&
/*hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);*/
}
- rx.empbuff.ready = 0;
+ rx.empbuff.ready = NULL;
rx.empbuff.irqcnt = 0;
+ rx.empbuff.emppktcnt = 0;
+ rx.empbuff.tmdspktcnt = 0;
}
void rx_emp_field_done_irq(void)
void rx_emp_status(void)
{
- unsigned int i, j;
- unsigned char *pdata;
-
rx_pr("p_addr_a=0x%x\n", rx.empbuff.p_addr_a);
rx_pr("p_addr_b=0x%x\n", rx.empbuff.p_addr_b);
rx_pr("irq cnt =0x%x\n", rx.empbuff.irqcnt);
rx_pr("p_addr_b=0x%p\n", rx.empbuff.ready);
- rx_pr("recv pkt cnt=0x%x\n", rx.empbuff.emppktcnt);
-
- pdata = rx.empbuff.ready;
- for (i = 0; i < rx.empbuff.emppktcnt; i++) {
- for (j = 0; j < 32; j++)
- rx_pr("0x%02lx, ", pdata[i*32 + j]);
- rx_pr("\n");
- }
+ rx_pr("dump_mode =0x%x\n", rx.empbuff.dump_mode);
+ rx_pr("recv tmp pkt cnt=0x%x\n", rx.empbuff.emppktcnt);
+ rx_pr("recv tmds pkt cnt=0x%x\n", rx.empbuff.tmdspktcnt);
}
-
void rx_tmds_to_ddr_init(void)
{
unsigned int data, data2;
unsigned int i = 0;
+ unsigned char *src_v_addr;
if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1)
return;
data2 = hdmirx_rd_top(TOP_EMP_STAT_0) & 0x7fffffff;
data = hdmirx_rd_top(TOP_EMP_STAT_1);
if (i++ > 100) {
- rx_pr("warning: wait emp finish\n");
+ rx_pr("warning: wait emp timeout\n");
break;
}
}
hdmirx_wr_top(TOP_EMP_DDR_START_A,
rx.empbuff.p_addr_a);
- /* max pkt count */
+ /* max pkt count to avoid buffer overflow */
/* one frame size: HxVx3x1.25 bytes */
- data = ((rx.empbuff.emppktcnt/8) * 8) - 1;
+ data = ((rx.empbuff.tmdspktcnt/8) * 8) - 1;
hdmirx_wr_top(TOP_EMP_CNTMAX, data);
- rx_pr("cnt max=0x%x\n", data);
+ rx_pr("pkt max cnt limit=0x%x\n", data);
+
+ /* clean hw buffer */
+ /* p addr to v addr for cpu access */
+ src_v_addr = phys_to_virt(rx.empbuff.p_addr_a);
+ memset(src_v_addr, 0, TMDS_BUFFER_SIZE);
data = 0;
data |= 0xf << 16;/*[23:16] hs_beat_rate=0xf */
data |= 0x0 << 0;/*[1:0] Endian = 0 */
hdmirx_wr_top(TOP_EMP_CNTL_0, data);
- data = 0;
- data |= 1 << 1;/*ddr_mode[1] 0: emp 1: tmds*/
- hdmirx_wr_top(TOP_EMP_CNTL_1, data);
-
- data |= 1; /*ddr_en[0] 1:enable*/
+ /* working mode: tmds data to ddr enable */
+ data = hdmirx_rd_top(TOP_EMP_CNTL_1);
+ data |= 0x1 << 1;/*ddr_mode[1] 0: emp 1: tmds*/
hdmirx_wr_top(TOP_EMP_CNTL_1, data);
/* emp int enable TOP_INTR_MASKN*/
/* emp last EMP pkt recv done bit[26]*/
top_intr_maskn_value |= _BIT(26);
hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
+
+ /*start record*/
+ data |= 0x1; /*ddr_en[0] 1:enable*/
+ hdmirx_wr_top(TOP_EMP_CNTL_1, data);
}
}
void rx_emp_lastpkt_done_irq(void)
{
- /* need to do ...*/
+ unsigned int data;
+
+ /* disable record */
+ data = hdmirx_rd_top(TOP_EMP_CNTL_1);
+ data &= ~0x1; /*ddr_en[0] 1:enable*/
+ hdmirx_wr_top(TOP_EMP_CNTL_1, data);
+
+ /*need capture data*/
+
+ rx_pr("lastpkt_done_irq\n");
+}
+
+/*
+ * get hdmi data error counter
+ * for tl1
+ * return:
+ * ch0 , ch1 , ch2 error counter value
+ */
+void rx_get_error_cnt(uint32_t *ch0, uint32_t *ch1,
+ uint32_t *ch2)
+{
+ uint32_t val;
+
+ val = hdmirx_rd_top(TOP_CHAN01_ERRCNT);
+ *ch0 = val & 0xffff;
+ *ch1 = (val >> 16) & 0xffff;
+ val = hdmirx_rd_top(TOP_CHAN2_ERRCNT);
+ *ch2 = val & 0xffff;
+}
+
+/*
+ * get hdmi audio N CTS
+ * for tl1
+ * return:
+ * audio ACR N
+ * audio ACR CTS
+ */
+void rx_get_audio_N_CTS(uint32_t *N, uint32_t *CTS)
+{
+ *N = hdmirx_rd_top(TOP_ACR_N_STAT);
+ *CTS = hdmirx_rd_top(TOP_ACR_CTS_STAT);
}
/*#define K_BRINGUP_PTM*/
+#define K_TEST_CHK_ERR_CNT
/**
* Bit field mask
#define HHI_HDMIRX_PHY_MISC_CNTL1 (0xd8<<2)/*0x041*/
#define HHI_HDMIRX_PHY_MISC_CNTL2 (0xe0<<2)/*0x042*/
#define HHI_HDMIRX_PHY_MISC_CNTL3 (0xe1<<2)/*0x043*/
-#define HHI_HDMIRX_PHY_MISC_STAT (0xee<<2)/*0x044*/
#define HHI_HDMIRX_PHY_DCHA_CNTL0 (0xe2<<2)/*0x045*/
#define HHI_HDMIRX_PHY_DCHA_CNTL1 (0xe3<<2)/*0x046*/
#define HHI_HDMIRX_PHY_DCHA_CNTL2 (0xe4<<2)/*0x047*/
#define HHI_HDMIRX_PHY_DCHD_CNTL0 (0xe5<<2)/*0x048*/
#define HHI_HDMIRX_PHY_DCHD_CNTL1 (0xe6<<2)/*0x049*/
#define HHI_HDMIRX_PHY_DCHD_CNTL2 (0xe7<<2)/*0x04A*/
+/*#define HHI_HDMIRX_PHY_MISC_STAT (0xee<<2)*//*0x044*/
#define HHI_HDMIRX_PHY_DCHD_STAT (0xef<<2)/*0x04B*/
-
-
#define TMDS_CLK_MIN (24000UL)
#define TMDS_CLK_MAX (340000UL)
extern void rx_phy_power_on(unsigned int onoff);
-#define K_MEASURE_SRC_HDMI_TMDSCLK 0
-#define K_MEASURE_SRC_HDMI_CABLECLK 1
+enum measure_clk_top_e {
+ TOP_HDMI_TMDSCLK = 0,
+ TOP_HDMI_CABLECLK,
+ TOP_HDMI_AUDIOCLK,
+};
-enum measure_clk_src {
+enum measure_clk_src_e {
MEASURE_CLK_CABLE,
MEASURE_CLK_TMDS,
MEASURE_CLK_PIXEL,
MEASURE_CLK_ESM,
};
+#define MHz 1000000
+#define KHz 1000
+
enum apllbw {
apll_bw_24_40 = 0,
apll_bw_40_80,
unsigned int od2_div;
};
-extern unsigned int rx_get_clock(unsigned int clk_src);
+extern unsigned int rx_get_clock(enum measure_clk_top_e clk_src);
extern unsigned int clk_util_clk_msr(unsigned int clk_mux);
-extern unsigned int rx_measure_clock(enum measure_clk_src clksrc);
+extern unsigned int rx_measure_clock(enum measure_clk_src_e clksrc);
extern void aml_phy_init(unsigned int bw);
extern void aml_phy_pw_onoff(unsigned int onoff);
extern unsigned int aml_check_clk_bandwidth(unsigned int cableclk,
extern void rx_emp_field_done_irq(void);
extern void rx_emp_status(void);
extern void rx_emp_lastpkt_done_irq(void);
-
+extern void rx_tmds_to_ddr_init(void);
+extern void rx_get_error_cnt(uint32_t *ch0, uint32_t *ch1, uint32_t *ch2);
+extern void rx_get_audio_N_CTS(uint32_t *N, uint32_t *CTS);
#endif
rx.aud_info.real_sr = ret_sr;
ret = true;
if (log_level & AUDIO_LOG)
- dump_state(2);
+ dump_state(RX_DUMP_AUDIO);
}
return ret;
}
if (wait_cnt == sig_stable_max)
rx_pr("*unsupport*\n");
if (unnormal_wait_max == wait_cnt) {
- dump_state(1);
+ dump_state(RX_DUMP_VIDEO);
ret = false;
}
}
if (wait_cnt == sig_stable_max)
rx_pr("*DVI*\n");
if (unnormal_wait_max == wait_cnt) {
- dump_state(1);
+ dump_state(RX_DUMP_VIDEO);
ret = false;
}
}
***********************/
void hdmirx_open_port(enum tvin_port_e port)
{
+ uint32_t fsmst = sm_pause;
+
+ /* stop fsm when swich port */
+ sm_pause = 1;
rx.port = (port - TVIN_PORT_HDMI0) & 0xf;
//rx.no_signal = false;
//rx.wait_no_sig_cnt = 0;
}
edid_update_flag = 0;
rx_pkt_initial();
-
+ sm_pause = fsmst;
rx_pr("%s:%d\n", __func__, rx.port);
}
return;
#endif
- cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
+ /*cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);*/
+ cur_cable_clk = rx_get_clock(TOP_HDMI_CABLECLK);
clk_diff = diff(rx.physts.cable_clk, cur_cable_clk);
cur_clk_rate = rx_get_scdc_clkrate_sts();
cur_phy_bw = aml_check_clk_bandwidth(cur_cable_clk, cur_clk_rate);
- if ((rx.cur_5v_sts) && (cur_cable_clk > 20000) &&
+ if ((rx.cur_5v_sts) && (cur_cable_clk > ((20 * MHz))) &&
((rx.physts.phy_bw != cur_phy_bw) ||
(rx.physts.clk_rate != cur_clk_rate) ||
- (clk_diff > 700))) {
+ (clk_diff > (1000 * KHz)))) {
if (phy_bw_cnt++ > 1) {
phy_bw_cnt = 0;
rx_pr("chg phy i=%d, cable clk:%d\n",
i, cur_cable_clk);
aml_phy_bw_switch(cur_cable_clk, cur_clk_rate);
- if ((cur_cable_clk < 20000) ||
+ if ((cur_cable_clk < (20 * MHz)) ||
aml_phy_pll_lock())
break;
}
}
}
+/*
+ * function:
+ * for check error counter start for tl1
+ *
+ */
+void rx_monitor_error_cnt_start(void)
+{
+ rx.physts.timestap = get_seconds();
+}
+
+/*
+ * function:
+ * 1min error counter check for tl1 aml phy
+ */
+void rx_monitor_error_counter(void)
+{
+ ulong timestap;
+ uint32_t ch0, ch1, ch2;
+
+ if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1)
+ return;
+
+ timestap = get_seconds();
+ if ((timestap - rx.physts.timestap) < 60) {
+
+ rx_get_error_cnt(&ch0, &ch1, &ch2);
+ if (ch0 || ch1 || ch2)
+ rx_pr("err cnt:%d,%d,%d\n", ch0, ch1, ch2);
+ }
+}
+
#ifdef USE_NEW_FSM_METHODE
void rx_err_monitor(void)
{
hdmirx_audio_fifo_rst();
rx.stable_timestamp = rx.timestamp;
rx_pr("Sig ready\n");
- dump_state(1);
+ dump_state(RX_DUMP_VIDEO);
+ #ifdef K_TEST_CHK_ERR_CNT
+ rx_monitor_error_cnt_start();
+ #endif
}
} else {
sig_stable_cnt = 0;
case FSM_SIG_READY:
rx_get_video_info();
rx.err_rec_mode = ERR_REC_EQ_RETRY;
+ #ifdef K_TEST_CHK_ERR_CNT
+ rx_monitor_error_counter();
+ #endif
/* video info change */
if ((!is_tmds_valid()) ||
(!rx_is_timing_stable())) {
if (is_aud_ch_map_change
(pre_auds_ch_alloc, rx.aud_info.auds_ch_alloc)) {
if (log_level & AUDIO_LOG)
- dump_state(2);
+ dump_state(RX_DUMP_AUDIO);
hdmirx_config_audio();
hdmirx_audio_fifo_rst();
rx_audio_pll_sw_update();
hdmirx_audio_fifo_rst();
rx_pr("STABLE->READY\n");
if (log_level & VIDEO_LOG)
- dump_state(0x1);
+ dump_state(RX_DUMP_VIDEO);
}
} else {
sig_stable_cnt = 0;
is_aud_ch_map_change
(pre_auds_ch_alloc, rx.aud_info.auds_ch_alloc)) {
if (log_level & AUDIO_LOG)
- dump_state(2);
+ dump_state(RX_DUMP_AUDIO);
rx.aud_sr_stable_cnt = 0;
break;
}
break;
}
if (rx.aud_sr_stable_cnt == aud_sr_stb_max) {
- dump_state(0x2);
+ dump_state(RX_DUMP_AUDIO);
rx_aud_pll_ctl(1);
if (is_afifo_error()) {
if (log_level & AUDIO_LOG)
return pos;
}
-static void dump_hdcp_data(void)
+static void dump_phy_status(void)
+{
+ uint32_t val0, val1, val2;
+
+ rx_pr("[PHY info]\n");
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ rx_get_error_cnt(&val0, &val1, &val2);
+ rx_pr("err cnt- ch0: %d,ch1:%d ch2:%d\n", val0, val1, val2);
+ rx_pr("PLL_LCK_STS(tmds valid) = 0x%x\n",
+ hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS));
+ rx_pr("MISC_STAT0 sqo = 0x%x\n",
+ hdmirx_rd_top(TOP_MISC_STAT0));
+ rx_pr("PHY_DCHD_STAT = 0x%x\n",
+ rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT));
+ rx_pr("APLL_CNTL0 = 0x%x\n",
+ rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));
+ rx_pr("TMDS_ALIGN_STAT = 0x%x\n",
+ hdmirx_rd_top(TOP_TMDS_ALIGN_STAT));
+ }
+}
+
+static void dump_clk_status(void)
+{
+ rx_pr("[HDMI clk info]\n");
+ rx_pr("top cableclk=%d\n",
+ rx_get_clock(TOP_HDMI_CABLECLK));
+ rx_pr("top audio meter clk=%d\n",
+ rx_get_clock(TOP_HDMI_AUDIOCLK));
+ rx_pr("top tmdsclk=%d\n",
+ rx_get_clock(TOP_HDMI_TMDSCLK));
+ rx_pr("cable clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_CABLE));
+ rx_pr("tmds clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_TMDS));
+ rx_pr("Pixel clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_PIXEL));
+ rx_pr("audio clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_AUD_PLL));
+ rx_pr("aud div clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_AUD_DIV));
+ rx_pr("mpll clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_MPLL));
+ rx_pr("esm clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_ESM));
+}
+
+static void dump_video_status(void)
+{
+ rx_get_video_info();
+
+ rx_pr("[HDMI info]\n");
+ rx_pr("colorspace %d,", rx.cur.colorspace);
+ rx_pr("dvi %d,", rx.cur.hw_dvi);
+ rx_pr("sw_dvi:%d,", rx.cur.sw_dvi);
+ rx_pr("interlace %d\n", rx.cur.interlaced);
+ rx_pr("htotal %d\n", rx.cur.htotal);
+ rx_pr("hactive %d\n", rx.cur.hactive);
+ rx_pr("vtotal %d\n", rx.cur.vtotal);
+ rx_pr("vactive %d\n", rx.cur.vactive);
+ rx_pr("repetition %d\n", rx.cur.repeat);
+ rx_pr("colordepth %d\n", rx.cur.colordepth);
+ rx_pr("frame_rate %d\n", rx.cur.frame_rate);
+ rx_pr("fmt=0x%x,", hdmirx_hw_get_fmt());
+ rx_pr("hw_vic %d,", rx.cur.hw_vic);
+ rx_pr("rx.no_signal=%d,rx.state=%d,",
+ rx.no_signal, rx.state);
+ rx_pr("skip frame=%d\n", rx.skip);
+ rx_pr("avmute_skip:0x%x\n", rx.avmute_skip);
+ rx_pr("phy addr: %#x,%#x,port: %d, up phy addr:%#x\n",
+ hdmirx_rd_top(TOP_EDID_RAM_OVR1_DATA),
+ hdmirx_rd_top(TOP_EDID_RAM_OVR2_DATA),
+ rx.port, up_phy_addr);
+ dump_clk_status();
+}
+
+static void dump_audio_status(void)
+{
+ static struct aud_info_s a;
+ uint32_t val0, val1;
+
+ rx_get_audinfo(&a);
+ rx_pr("[AudioInfo]\n");
+ rx_pr(" CT=%u CC=%u", a.coding_type,
+ a.channel_count);
+ rx_pr(" SF=%u SS=%u", a.sample_frequency,
+ a.sample_size);
+ rx_pr(" CA=%u\n", a.auds_ch_alloc);
+ rx_pr("CTS=%d, N=%d,", a.cts, a.n);
+ rx_pr("acr clk=%d\n", a.arc);
+ if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+ rx_get_audio_N_CTS(&val0, &val1);
+ rx_pr("top CTS:%d, N:%d\n", val1, val0);
+ }
+ rx_pr("audio receive data:%d\n",
+ auds_rcv_sts);
+}
+
+static void dump_hdcp_status(void)
{
- rx_pr("\n*************HDCP");
- rx_pr("***************");
+ rx_pr("HDCP version:%d\n", rx.hdcp.hdcp_version);
+ if (hdcp22_on) {
+ rx_pr("HDCP22 sts = %x\n",
+ rx_hdcp22_rd_reg(0x60));
+ rx_pr("HDCP22_on = %d\n",
+ hdcp22_on);
+ rx_pr("HDCP22_auth_sts = %d\n",
+ hdcp22_auth_sts);
+ rx_pr("HDCP22_capable_sts = %d\n",
+ hdcp22_capable_sts);
+ rx_pr("video_stable_to_esm = %d\n",
+ video_stable_to_esm);
+ rx_pr("hpd_to_esm = %d\n",
+ hpd_to_esm);
+ rx_pr("sts8fc = %x",
+ hdmirx_rd_dwc(DWC_HDCP22_STATUS));
+ rx_pr("sts81c = %x",
+ hdmirx_rd_dwc(DWC_HDCP22_CONTROL));
+ }
+
+ rx_pr("ESM clock = %d\n",
+ rx_measure_clock(MEASURE_CLK_ESM));
+ rx_pr("HDCP debug value=0x%x\n",
+ hdmirx_rd_dwc(DWC_HDCP_DBG));
+ rx_pr("HDCP14 state:%d\n",
+ rx.cur.hdcp14_state);
+ rx_pr("HDCP22 state:%d\n",
+ rx.cur.hdcp22_state);
+
rx_pr("\n hdcp-seed = %d ",
rx.hdcp.seed);
/* KSV CONFIDENTIAL */
- rx_pr("hdcp-bksv = %x---%x",
+ rx_pr("hdcp-bksv = %x---%x\n",
hdmirx_rd_dwc(DWC_HDCP_BKSV1),
hdmirx_rd_dwc(DWC_HDCP_BKSV0));
- rx_pr("\n*************HDCP end**********\n");
}
-void dump_state(unsigned char enable)
+void dump_state(enum dumpinfo_e enable)
{
- /*int error = 0;*/
- /* int i = 0; */
- static struct aud_info_s a;
-
rx_get_video_info();
- if (enable & 1) {
- rx_pr("[HDMI info]");
- rx_pr("colorspace %d,", rx.cur.colorspace);
- rx_pr("dvi %d,", rx.cur.hw_dvi);
- rx_pr("sw_dvi:%d,", rx.cur.sw_dvi);
- rx_pr("interlace %d\n", rx.cur.interlaced);
- rx_pr("htotal %d", rx.cur.htotal);
- rx_pr("hactive %d", rx.cur.hactive);
- rx_pr("vtotal %d", rx.cur.vtotal);
- rx_pr("vactive %d", rx.cur.vactive);
- rx_pr("repetition %d\n", rx.cur.repeat);
- rx_pr("colordepth %d", rx.cur.colordepth);
- rx_pr("frame_rate %d\n", rx.cur.frame_rate);
- rx_pr("fmt=0x%x,", hdmirx_hw_get_fmt());
- rx_pr("rx.no_signal=%d,rx.state=%d,",
- rx.no_signal, rx.state);
- rx_pr("TMDS clock = %d\n,",
- rx_measure_clock(MEASURE_CLK_TMDS));
- rx_pr("Pixel clock = %d\n",
- rx_measure_clock(MEASURE_CLK_PIXEL));
- rx_pr("cable clock = %d\n",
- rx_measure_clock(MEASURE_CLK_CABLE));
- rx_pr("audio clock = %d\n",
- rx_measure_clock(MEASURE_CLK_AUD_PLL));
- rx_pr("aud div clock = %d\n",
- rx_measure_clock(MEASURE_CLK_AUD_DIV));
- rx_pr("mpll clock = %d\n",
- rx_measure_clock(MEASURE_CLK_MPLL));
- rx_pr("esm clock = %d\n",
- rx_measure_clock(MEASURE_CLK_ESM));
+ if (enable & RX_DUMP_VIDEO) /* video info */
+ dump_video_status();
+ else if (enable & RX_DUMP_AUDIO) /* audio info */
+ dump_audio_status();
+ else if (enable & RX_DUMP_HDCP) /* hdcp info */
+ dump_hdcp_status();
+ else if (enable & RX_DUMP_PHY) /* phy info */
+ dump_phy_status();
+ else if (enable & RX_DUMP_CLK) /* clk src info */
+ dump_clk_status();
+ else {
+ dump_clk_status();
+ dump_phy_status();
+ dump_video_status();
+ dump_audio_status();
+ dump_hdcp_status();
}
- if (enable & 2) {
- rx_get_audinfo(&a);
- rx_pr("AudioInfo:");
- rx_pr(" CT=%u CC=%u", a.coding_type,
- a.channel_count);
- rx_pr(" SF=%u SS=%u", a.sample_frequency,
- a.sample_size);
- rx_pr(" CA=%u", a.auds_ch_alloc);
- rx_pr(" CTS=%d, N=%d,", a.cts, a.n);
- rx_pr("recovery clock is %d\n", a.arc);
- }
- if (enable & 4) {
- /***************hdcp*****************/
- rx_pr("HDCP version:%d\n", rx.hdcp.hdcp_version);
- if (hdcp22_on) {
- rx_pr("HDCP22 sts = %x\n",
- rx_hdcp22_rd_reg(0x60));
- rx_pr("HDCP22_on = %d\n",
- hdcp22_on);
- rx_pr("HDCP22_auth_sts = %d\n",
- hdcp22_auth_sts);
- rx_pr("HDCP22_capable_sts = %d\n",
- hdcp22_capable_sts);
- rx_pr("video_stable_to_esm = %d\n",
- video_stable_to_esm);
- rx_pr("hpd_to_esm = %d\n",
- hpd_to_esm);
- rx_pr("sts8fc = %x",
- hdmirx_rd_dwc(DWC_HDCP22_STATUS));
- rx_pr("sts81c = %x",
- hdmirx_rd_dwc(DWC_HDCP22_CONTROL));
- }
- if (enable & 8) {
- rx_pr("hw_vic %d,", rx.cur.hw_vic);
- rx_pr("ESM clock = %d\n",
- rx_measure_clock(MEASURE_CLK_ESM));
- rx_pr("HDCP debug value=0x%x\n",
- hdmirx_rd_dwc(DWC_HDCP_DBG));
- rx_pr("HDCP14 state:%d\n",
- rx.cur.hdcp14_state);
- rx_pr("HDCP22 state:%d\n",
- rx.cur.hdcp22_state);
- rx_pr("audio receive data:%d\n",
- auds_rcv_sts);
- rx_pr("skip frame=%d\n", rx.skip);
- rx_pr("avmute_skip:0x%x\n", rx.avmute_skip);
- rx_pr("Audio PLL clock = %d\n",
- rx_measure_clock(MEASURE_CLK_AUD_PLL));
- }
+}
- dump_hdcp_data();
- /*--------------edid-------------------*/
- /* rx_pr("edid index: %d\n", edid_mode); */
- rx_pr("phy addr: %#x,%#x,port: %d, up phy addr:%#x\n",
- hdmirx_rd_top(TOP_EDID_RAM_OVR1_DATA),
- hdmirx_rd_top(TOP_EDID_RAM_OVR2_DATA),
- rx.port, up_phy_addr);
- /* rx_pr("downstream come: %d hpd:%d hdr lume:%d\n", */
- /* new_edid, repeat_plug, new_hdr_lum); */
- }
+void rx_debug_help(void)
+{
+ rx_pr("*****************\n");
+ rx_pr("reset0--hw_config\n");
+ rx_pr("reset1--8bit phy rst\n");
+ rx_pr("reset3--irq open\n");
+ rx_pr("reset4--edid_update\n");
+ rx_pr("reset5--esm rst\n");
+ rx_pr("database--esm data addr\n");
+ rx_pr("duk--dump duk\n");
+ rx_pr("v - driver version\n");
+ rx_pr("state0 -dump video\n");
+ rx_pr("state1 -dump audio\n");
+ rx_pr("state2 -dump hdcp\n");
+ rx_pr("state3 -dump phy\n");
+ rx_pr("state4 -dump clock\n");
+ rx_pr("statex -dump all\n");
+ rx_pr("port1/2/3 -port swich\n");
+ rx_pr("hpd0/1 -set hpd 0:low\n");
+ rx_pr("cable_status -5V sts\n");
+ rx_pr("pause -pause fsm\n");
+ rx_pr("reg -dump all dwc reg\n");
+ rx_pr("*****************\n");
}
int hdmirx_debug(const char *buf, int size)
}
if (strncmp(tmpbuf, "help", 4) == 0) {
- rx_pr("*****************\n");
- rx_pr("reset0--hw_config\n");
- rx_pr("reset1--8bit phy rst\n");
- rx_pr("reset3--irq open\n");
- rx_pr("reset4--edid_update\n");
- rx_pr("reset5--esm rst\n");
- rx_pr("database--esm data addr\n");
- rx_pr("duk--dump duk\n");
- rx_pr("*****************\n");
+ rx_debug_help();
} else if (strncmp(tmpbuf, "hpd", 3) == 0)
rx_set_cur_hpd(tmpbuf[3] == '0' ? 0 : 1);
else if (strncmp(tmpbuf, "cable_status", 12) == 0) {
hdmirx_hdcp22_esm_rst();
}
} else if (strncmp(tmpbuf, "state", 5) == 0) {
- if (tmpbuf[5] == '1')
- dump_state(0xff);
+ if (tmpbuf[5] == '0')
+ dump_state(RX_DUMP_VIDEO);
+ else if (tmpbuf[5] == '1')
+ dump_state(RX_DUMP_AUDIO);
+ else if (tmpbuf[5] == '2')
+ dump_state(RX_DUMP_HDCP);
+ else if (tmpbuf[5] == '3')
+ dump_state(RX_DUMP_PHY);
+ else if (tmpbuf[5] == '4')
+ dump_state(RX_DUMP_CLK);
else
- dump_state(1);
+ dump_state(RX_DUMP_ALL);
} else if (strncmp(tmpbuf, "pause", 5) == 0) {
if (kstrtol(tmpbuf + 5, 10, &value) < 0)
return -EINVAL;
rx_pr("Hdmirx version1: %s\n", RX_VER1);
rx_pr("Hdmirx version2: %s\n", RX_VER2);
rx_pr("------------------\n");
- } else if (strncmp(input[0], "port0", 5) == 0) {
+ } else if (strncmp(input[0], "port0", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI0);
+ signal_status_init();
rx.open_fg = 1;
} else if (strncmp(input[0], "port1", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI1);
+ signal_status_init();
rx.open_fg = 1;
} else if (strncmp(input[0], "port2", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI2);
+ signal_status_init();
rx.open_fg = 1;
} else if (strncmp(input[0], "port3", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI3);
+ signal_status_init();
rx.open_fg = 1;
} else if (strncmp(input[0], "empsts", 6) == 0) {
rx_emp_status();
- } else if (strncmp(input[0], "dumpemp", 7) == 0) {
+ } else if (strncmp(input[0], "empstart", 8) == 0) {
rx_emp_resource_allocate(hdmirx_dev);
- } else if (strncmp(input[0], "dumptmds", 8) == 0) {
+ } else if (strncmp(input[0], "tmdsstart", 9) == 0) {
rx_tmds_resource_allocate(hdmirx_dev);
- } else if (strncmp(input[0], "empbuff", 7) == 0) {
+ rx_tmds_to_ddr_init();
+ } else if (strncmp(input[0], "empcapture", 10) == 0) {
+ rx_emp_data_capture();
+ } else if (strncmp(input[0], "tmdcapture", 11) == 0) {
+ rx_tmds_data_capture();
+ } else if (strncmp(input[0], "phyinit", 7) == 0) {
+ aml_phy_bw_switch(rx_get_clock(TOP_HDMI_CABLECLK),
+ rx_get_scdc_clkrate_sts());
+ } else if (strncmp(input[0], "tmdscnt", 7) == 0) {
if (kstrtol(input[1], 16, &value) < 0)
rx_pr("error input Value\n");
rx_pr("set pkt cnt:0x%x\n", value);
E_AUDCLK_ERR,
};
+enum dumpinfo_e {
+ RX_DUMP_VIDEO = 0x01,
+ RX_DUMP_AUDIO = 0x02,
+ RX_DUMP_HDCP = 0x04,
+ RX_DUMP_PHY = 0x08,
+ RX_DUMP_CLK = 0x10,
+ RX_DUMP_ALL = 0x80,
+};
+
/* signal */
extern enum tvin_sig_fmt_e hdmirx_hw_get_fmt(void);
extern void rx_main_state_machine(void);
extern void hdmirx_timer_handler(unsigned long arg);
extern void rx_tmds_resource_allocate(struct device *dev);
extern void rx_emp_resource_allocate(struct device *dev);
-
+extern void rx_emp_data_capture(void);
+extern void rx_tmds_data_capture(void);
+extern void dump_state(enum dumpinfo_e enable);
#endif
projects / GitHub / LineageOS / G12 / android_kernel_amlogic_linux-4.9.git / commitdiff