ARM: dts: uniphier: add reference clock nodes

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index f847e6878011c18ad6bdb4f74b02723ffbe0f97a..61a0955982064eb8a5d216d1434ace0835631518 100644 (file)
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -45,6 +45,13 @@
 /include/ "skeleton.dtsi"
 
 / {
+       clocks {
+               refclk: ref {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+               };
+       };
+
        soc: soc {
                compatible = "simple-bus";
                #address-cells = <1>;

diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index 34f0d8dcd81470a2d60b4809a89598ac050f896e..dadd86070c98367c6bbe7c5d7892ef890f3fdb5d 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -173,6 +173,10 @@
 
 };
 
+&refclk {
+       clock-frequency = <24576000>;
+};
+
 &serial3 {
        interrupts = <0 29 4>;
 };

diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index d78142fb35c42f847024fcc6ba66dbdffe87166a..20f3f2ae7fa419b542c2a51593d7dc5a399fc547 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -195,6 +195,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <25000000>;
+};
+
 &pinctrl {
        compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };

diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 2f389ea75e0150b9a5127394027b277b8c99bf7d..24f6f664b2692b64acf6a19fe3d327233a759832 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -189,6 +189,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <20000000>;
+};
+
 &pinctrl {
        compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };

diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 4c746ea24ee19dfa3f5737a50cc2342cfa950877..03292f443305eb287826cc1ce202e0bcba224bc0 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -68,6 +68,12 @@
        };
 
        clocks {
+               refclk: ref {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24576000>;
+               };
+
                arm_timer_clk: arm_timer_clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";

diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index 7d06a1c487d8c8fa059983e4c97c605d15254ef4..6bfd29a05575909bb0e44f5ddcd295a054cd4032 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -172,6 +172,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <25000000>;
+};
+
 &serial3 {
        interrupts = <0 29 4>;
 };

diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 6bd353f2d77efceaeb1dd38a9991072190092f8d..4ac484c6ce4eb8208b6893b8f9bb408da7a7cdaf 100644 (file)
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -200,6 +200,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <25000000>;
+};
+
 &pinctrl {
        compatible = "socionext,proxstream2-pinctrl", "syscon";
 };