clk: mmp: add spin lock for clk-frac

The register used by clk-frac may be shared with
other clocks.
So it needs to use spin lock to protect the register
access.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 3fbc9cab53a6a901742f9d5d8dcc2b562fb5827a..e29d006ab85e9d39cfbda5cdc86bf7cf6e3ee9e1 100644 (file)
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -29,6 +29,7 @@ struct mmp_clk_factor {
        struct mmp_clk_factor_masks     *masks;
        struct mmp_clk_factor_tbl       *ftbl;
        unsigned int            ftbl_cnt;
+       spinlock_t *lock;
 };
 
 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
@@ -86,6 +87,7 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
        int i;
        unsigned long val;
        unsigned long prev_rate, rate = 0;
+       unsigned long flags = 0;
 
        for (i = 0; i < factor->ftbl_cnt; i++) {
                prev_rate = rate;
@@ -97,6 +99,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
        if (i > 0)
                i--;
 
+       if (factor->lock)
+               spin_lock_irqsave(factor->lock, flags);
+
        val = readl_relaxed(factor->base);
 
        val &= ~(masks->num_mask << masks->num_shift);
@@ -107,6 +112,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
 
        writel_relaxed(val, factor->base);
 
+       if (factor->lock)
+               spin_unlock_irqrestore(factor->lock, flags);
+
        return 0;
 }
 
@@ -120,7 +128,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
                unsigned long flags, void __iomem *base,
                struct mmp_clk_factor_masks *masks,
                struct mmp_clk_factor_tbl *ftbl,
-               unsigned int ftbl_cnt)
+               unsigned int ftbl_cnt, spinlock_t *lock)
 {
        struct mmp_clk_factor *factor;
        struct clk_init_data init;
@@ -143,6 +151,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
        factor->ftbl = ftbl;
        factor->ftbl_cnt = ftbl_cnt;
        factor->hw.init = &init;
+       factor->lock = lock;
 
        init.name = name;
        init.ops = &clk_factor_ops;

diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index 7083f12ef422b10062ce5c75994822a003cf1083..5c90a4230fa3d3f2718c7ed6452c32c51df70b24 100644 (file)
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
        clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(clk, 14745600);
        clk_register_clkdev(clk, "uart_pll", NULL);
 

diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 75266ac80829939e473053c32e555f206d2a7bd9..93e967c0f972f954ef1f7af9bb2f90e0c3241cae 100644 (file)
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
        uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 

diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index f81799987451eeb5cefe14e7d173b6f39a855597..993abcdb32cce825fdb1d2ea835cb69f3ecf94fc 100644 (file)
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -163,7 +163,7 @@ void __init pxa910_clk_init(void)
        uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
                                mpmu_base + MPMU_UART_PLL,
                                &uart_factor_masks, uart_factor_tbl,
-                               ARRAY_SIZE(uart_factor_tbl));
+                               ARRAY_SIZE(uart_factor_tbl), &clk_lock);
        clk_set_rate(uart_pll, 14745600);
        clk_register_clkdev(uart_pll, "uart_pll", NULL);
 

diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 3fe92be9e05493fa96b708ced266c11dd2906596..b71b717cdb24a51643fc8a424ca4bc471e8780ea 100644 (file)
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -31,5 +31,6 @@ extern struct clk *mmp_clk_register_apmu(const char *name,
 extern struct clk *mmp_clk_register_factor(const char *name,
                const char *parent_name, unsigned long flags,
                void __iomem *base, struct mmp_clk_factor_masks *masks,
-               struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+               struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+               spinlock_t *lock);
 #endif