ARM: tegra: reparent sclk to pll_c_out1

pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 22df10fb9972877069f92637ff5849ba990ad9f7..e9690041868223a71ad8dfd7e62f7c8f25b851e0 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
        { "pll_p_out2", "pll_p",        48000000,       true },
        { "pll_p_out3", "pll_p",        72000000,       true },
        { "pll_p_out4", "pll_p",        108000000,      true },
-       { "sclk",       "pll_p_out4",   108000000,      true },
-       { "hclk",       "sclk",         108000000,      true },
+       { "pll_c",      "clk_m",        600000000,      true },
+       { "pll_c_out1", "pll_c",        120000000,      true },
+       { "sclk",       "pll_c_out1",   120000000,      true },
+       { "hclk",       "sclk",         120000000,      true },
        { "pclk",       "hclk",         54000000,       true },
        { "csite",      NULL,           0,              true },
        { "emc",        NULL,           0,              true },