ARM: dts: r8a7743: Add APMU node and second CPU core

Add DT nodes for the Advanced Power Management Unit (APMU) and the
second CPU core.  Use the enable-method to point out that the APMU
should be used for SMP support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ce80a26c421a85726f7b9a510cf85d649c3ff34f..ec9db0fcffc694d82eaf71e93b187f4e2c79ec7a 100644 (file)
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -30,6 +30,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -41,6 +42,15 @@
                        next-level-cache = <&L2_CA15>;
                };
 
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+                       clock-frequency = <1500000000>;
+                       power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+                       next-level-cache = <&L2_CA15>;
+               };
+
                L2_CA15: cache-controller-0 {
                        compatible = "cache";
                        cache-unified;
@@ -57,6 +67,12 @@
                #size-cells = <2>;
                ranges;
 
+               apmu@e6152000 {
+                       compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+                       reg = <0 0xe6152000 0 0x188>;
+                       cpus = <&cpu0 &cpu1>;
+               };
+
                gic: interrupt-controller@f1001000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;