drm/i915: mask the video DIP frequency when changing it
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 4 May 2012 20:18:22 +0000 (17:18 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 8 May 2012 12:15:59 +0000 (14:15 +0200)
Better safe than sorry. Currently we never change the frequency and
use the same for every infoframe type, so the only way to reproduce a
bug would be with the BIOS doing something.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_hdmi.c

index 71e7af91f1b1b25a17ad04bf77e48250c5ee8cb0..ce6e64dd00ff79a5cef0b180a108243a7ece9b07 100644 (file)
 #define   VIDEO_DIP_FREQ_ONCE          (0 << 16)
 #define   VIDEO_DIP_FREQ_VSYNC         (1 << 16)
 #define   VIDEO_DIP_FREQ_2VSYNC                (2 << 16)
+#define   VIDEO_DIP_FREQ_MASK          (3 << 16)
 
 /* Panel power sequencing */
 #define PP_STATUS      0x61200
index 6c96bb54e967a8d376864fbbb7890333d74bf5fe..4a4ee8b25f2f655ab2e3757a04f651149473959b 100644 (file)
@@ -164,6 +164,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
        }
 
        val |= intel_infoframe_enable(frame);
+       val &= ~VIDEO_DIP_FREQ_MASK;
        val |= intel_infoframe_frequency(frame);
 
        I915_WRITE(VIDEO_DIP_CTL, val);
@@ -203,6 +204,7 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
        }
 
        val |= intel_infoframe_enable(frame);
+       val &= ~VIDEO_DIP_FREQ_MASK;
        val |= intel_infoframe_frequency(frame);
 
        I915_WRITE(reg, val);
@@ -236,6 +238,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
        }
 
        val |= intel_infoframe_enable(frame);
+       val &= ~VIDEO_DIP_FREQ_MASK;
        val |= intel_infoframe_frequency(frame);
 
        I915_WRITE(reg, val);