drm/i915: Apply OCD to VLV/CHV DPLL defines

Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c4d7894b429a880bffa5c9cea38c9600730ebbd..0650a3d8a40f8c95a61a563f2ae0217ab783ee09 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2150,7 +2150,7 @@ enum skl_disp_power_wells {
 #define   DPLL_DVO_2X_MODE             (1 << 30)
 #define   DPLL_EXT_BUFFER_ENABLE_VLV   (1 << 30)
 #define   DPLL_SYNCLOCK_ENABLE         (1 << 29)
-#define   DPLL_REFA_CLK_ENABLE_VLV     (1 << 29)
+#define   DPLL_REF_CLK_ENABLE_VLV      (1 << 29)
 #define   DPLL_VGA_MODE_DIS            (1 << 28)
 #define   DPLLB_MODE_DAC_SERIAL                (1 << 26) /* i915 */
 #define   DPLLB_MODE_LVDS              (2 << 26) /* i915 */
@@ -2164,8 +2164,8 @@ enum skl_disp_power_wells {
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
 #define   DPLL_LOCK_VLV                        (1<<15)
 #define   DPLL_INTEGRATED_CRI_CLK_VLV  (1<<14)
-#define   DPLL_INTEGRATED_CLOCK_VLV    (1<<13)
-#define   DPLL_SSC_REF_CLOCK_CHV       (1<<13)
+#define   DPLL_INTEGRATED_REF_CLK_VLV  (1<<13)
+#define   DPLL_SSC_REF_CLK_CHV         (1<<13)
 #define   DPLL_PORTC_READY_MASK                (0xf << 4)
 #define   DPLL_PORTB_READY_MASK                (0xf)
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 59986377ba8ac15dccbfb6ae09a9854a86d0e442..a7482ab140e1af5c3608ee317ff589c35c2a6021 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1807,7 +1807,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
         */
        val = DPLL_VGA_MODE_DIS;
        if (pipe == PIPE_B)
-               val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
+               val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
        I915_WRITE(DPLL(pipe), val);
        POSTING_READ(DPLL(pipe));
 
@@ -1822,8 +1822,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
        assert_pipe_disabled(dev_priv, pipe);
 
        /* Set PLL en = 0 */
-       val = DPLL_SSC_REF_CLOCK_CHV |
-               DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+       val = DPLL_SSC_REF_CLK_CHV |
+               DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
        if (pipe != PIPE_A)
                val |= DPLL_INTEGRATED_CRI_CLK_VLV;
        I915_WRITE(DPLL(pipe), val);
@@ -7224,8 +7224,8 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
         * clock for pipe B, since VGA hotplug / manual detection depends
         * on it.
         */
-       dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
-               DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+       dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
+               DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
        /* We should never disable this, set it here for state tracking */
        if (crtc->pipe == PIPE_B)
                dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
@@ -7331,8 +7331,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
 static void chv_compute_dpll(struct intel_crtc *crtc,
                             struct intel_crtc_state *pipe_config)
 {
-       pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
-               DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+       pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
+               DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
                DPLL_VCO_ENABLE;
        if (crtc->pipe != PIPE_A)
                pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5381ddcc2a796e7b68b6cab0906e0435db33857b..f4438eb5b4587d7ae0e3658392bf747d9681d044 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -413,12 +413,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
        /* Disable DPOunit clock gating, can stall pipe
         * and we need DPLL REFA always enabled */
        tmp = I915_READ(DPLL(pipe));
-       tmp |= DPLL_REFA_CLK_ENABLE_VLV;
+       tmp |= DPLL_REF_CLK_ENABLE_VLV;
        I915_WRITE(DPLL(pipe), tmp);
 
        /* update the hw state for DPLL */
-       intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
-               DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+       intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
+               DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 
        tmp = I915_READ(DSPCLK_GATE_D);
        tmp |= DPOUNIT_CLOCK_GATE_DISABLE;

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f0e6f49ee33a71259516025497bd51ae0ee88479..932d96332eca18cd91f3e1485e9ff9b8bd703c24 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -883,7 +883,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
         * hotplug / manual detection.
         */
        I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-                  DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+                  DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
        udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 
        vlv_set_power_well(dev_priv, power_well, true);
@@ -934,13 +934,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
        if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
                phy = DPIO_PHY0;
                I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-                          DPLL_REFA_CLK_ENABLE_VLV);
+                          DPLL_REF_CLK_ENABLE_VLV);
                I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-                          DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+                          DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
        } else {
                phy = DPIO_PHY1;
                I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
-                          DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+                          DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
        }
        udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
        vlv_set_power_well(dev_priv, power_well, true);