gpu: update gpu driver for t5 [1/1]

PD#SWPL-33677

Problem:
The mali poweron ack reg have been remove on T5
The read operation of AO_RTI_GEN_PWR_ACK0 will result in crash

Solution:
replace the gpu power on status with gpu internal reg value.

Verify:
ak326 socket board

Change-Id: If9ad2eac0ba5759dc91901b2e7e296caf04a25a5
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>

diff --git a/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/mpgpu.c b/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/mpgpu.c
index 6cbeb0cb2043dd4858cdbe2f09efd08e9ff8d9b1..ee7c1da89f43268235bfa0ad60661907861aa930 100644 (file)
--- a/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/mpgpu.c
+++ b/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/mpgpu.c
@@ -33,21 +33,27 @@
 #include <asm/io.h>
 #endif
 
-//#include <mali_kbase.h>
+#include <mali_kbase.h>
+#include <mali_kbase_defs.h>
+
 #include "meson_main2.h"
 
 int meson_gpu_data_invalid_count = 0;
 int meson_gpu_fault = 0;
 
+extern u64 kbase_pm_get_ready_cores(struct kbase_device *kbdev, enum kbase_pm_core_type type);
 static ssize_t domain_stat_read(struct class *class,
                struct class_attribute *attr, char *buf)
 {
        unsigned int val;
+       u64 core_ready;
        mali_plat_info_t* pmali_plat = get_mali_plat_data();
+       struct platform_device* ptr_plt_dev = pmali_plat->pdev;
+       struct kbase_device *kbdev = dev_get_drvdata(&ptr_plt_dev->dev);
 
-       val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
-       return sprintf(buf, "%x\n", val>>4);
-       return 0;
+       core_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_SHADER);
+       val = core_ready;
+       return sprintf(buf, "%x\n", val);
 }
 
 #define PREHEAT_CMD "preheat"

diff --git a/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c b/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
index ac49caa3b9453398a11053939b0211d6775b9b27..6e10d447c33e4a1ffcb97f31a5131c395efa17f3 100644 (file)
--- a/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
+++ b/bifrost/r16p0/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
@@ -163,20 +163,17 @@ quit:
     return ret;
 }
 #ifdef CONFIG_DEVFREQ_THERMAL
+/* note:
+ * why return the config_pp which come from dts [num_of_pp] dirrectly
+ * 1. the return value only used for thermal,
+ * and we have not dynamic adjust the core num.
+ * 2. avoid influent the IC before T5.
+ * TODO: need improve it, if we add dynamic adjust the core num.*/
 static u32 mali_get_online_pp(void)
 {
-    unsigned int val;
-    mali_plat_info_t* pmali_plat = get_mali_plat_data();
+    u32 fix_pp_num = mali_plat_data.cfg_pp;
 
-    val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
-    if (val == 0x07)    /* No pp is working */
-        return 0;
-
-#ifndef MESON_DRV_BRING
-    return 2;
-#else
-    return mali_executor_get_num_cores_enabled();
-#endif
+    return fix_pp_num;
 }
 #endif
 #endif