MIPS: RB532: Cleanup the headers again

This patch cleans up headers and regroups informations to
where they should reside. While moving, try to have a
consistant naming for defines.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index c0d0f950caf29d4bacd14b1bfb63f4dd50aa4262..549b46d2fcee3574ac823fd6425ae049c38329bc 100644 (file)
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -45,7 +45,7 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/irq.h>
 
 struct intr_group {
        u32 mask;       /* mask of valid bits in pending/mask registers */

diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 1a05b5ddee09718640baeefdd9fac439b20d5f88..3e0d7ec3a5795315830f8033a542de360fd1f1b5 100644 (file)
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -31,16 +31,16 @@
 #include <linux/serial_8250.h>
 
 #include <asm/serial.h>
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
 
 extern unsigned int idt_cpu_freq;
 
 static struct uart_port rb532_uart = {
        .type = PORT_16550A,
        .line = 0,
-       .irq = RC32434_UART0_IRQ,
+       .irq = UART0_IRQ,
        .iotype = UPIO_MEM,
-       .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
+       .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
        .regshift = 2
 };
 

diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
index 7aafa95ac20b830baead71239ca8d0f303c7188d..50f530f5b602a1cbeb5808c5428df3c637992dd1 100644 (file)
--- a/arch/mips/rb532/setup.c
+++ b/arch/mips/rb532/setup.c
@@ -9,7 +9,7 @@
 #include <asm/time.h>
 #include <linux/ioport.h>
 
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
 #include <asm/mach-rc32434/pci.h>
 
 struct pci_reg __iomem *pci_reg;
@@ -27,7 +27,7 @@ static struct resource pci0_res[] = {
 static void rb_machine_restart(char *command)
 {
        /* just jump to the reset vector */
-       writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
+       writel(0x80000001, IDT434_REG_BASE + RST);
        ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
 }
 

diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
index d68318b6b76d42f173f3496dcdaae236884687f3..56738d8ec4e2b46b7e9c864ff99c48529028f28a 100644 (file)
--- a/include/asm-mips/mach-rc32434/irq.h
+++ b/include/asm-mips/mach-rc32434/irq.h
@@ -4,6 +4,26 @@
 #define NR_IRQS        256
 
 #include <asm/mach-generic/irq.h>
+#include <asm/mach-rc32434/rb.h>
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND         (REGBASE + 0x38000)
+#define IC_GROUP0_MASK         (REGBASE + 0x38008)
+#define IC_GROUP_OFFSET                0x0C
+
+#define NUM_INTR_GROUPS                5
+
+/* 16550 UARTs */
+#define GROUP0_IRQ_BASE                8       /* GRP2 IRQ numbers start here */
+                                       /* GRP3 IRQ numbers start here */
+#define GROUP1_IRQ_BASE                (GROUP0_IRQ_BASE + 32)
+                                       /* GRP4 IRQ numbers start here */
+#define GROUP2_IRQ_BASE                (GROUP1_IRQ_BASE + 32)
+                                       /* GRP5 IRQ numbers start here */
+#define GROUP3_IRQ_BASE                (GROUP2_IRQ_BASE + 32)
+#define GROUP4_IRQ_BASE                (GROUP3_IRQ_BASE + 32)
+
+#define UART0_IRQ              (GROUP3_IRQ_BASE + 0)
 
 #define ETH0_DMA_RX_IRQ        (GROUP1_IRQ_BASE + 0)
 #define ETH0_DMA_TX_IRQ        (GROUP1_IRQ_BASE + 1)

diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
index 62ac73c999c4b47f94fbfbd67440617a335efff4..79e8ef67d0d397eb38ce223cd27160bec0a8a548 100644 (file)
--- a/include/asm-mips/mach-rc32434/rb.h
+++ b/include/asm-mips/mach-rc32434/rb.h
@@ -19,6 +19,8 @@
 
 #define REGBASE                0x18000000
 #define IDT434_REG_BASE        ((volatile void *) KSEG1ADDR(REGBASE))
+#define UART0BASE      0x58000
+#define RST            (1 << 15)
 #define DEV0BASE       0x010000
 #define DEV0MASK       0x010004
 #define DEV0C          0x010008

diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
index c4a02145104e7efb220ed3d38d39ff4febf59346..9df04b72744a195f0b25699e3b050664c0a1f301 100644 (file)
--- a/include/asm-mips/mach-rc32434/rc32434.h
+++ b/include/asm-mips/mach-rc32434/rc32434.h
@@ -8,37 +8,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#define RC32434_REG_BASE       0x18000000
-#define RC32434_RST            (1 << 15)
-
 #define IDT_CLOCK_MULT         2
-#define MIPS_CPU_TIMER_IRQ     7
-
-/* Interrupt Controller */
-#define IC_GROUP0_PEND         (RC32434_REG_BASE + 0x38000)
-#define IC_GROUP0_MASK         (RC32434_REG_BASE + 0x38008)
-#define IC_GROUP_OFFSET                0x0C
-
-#define NUM_INTR_GROUPS                5
-
-/* 16550 UARTs */
-#define GROUP0_IRQ_BASE                8       /* GRP2 IRQ numbers start here */
-                                       /* GRP3 IRQ numbers start here */
-#define GROUP1_IRQ_BASE                (GROUP0_IRQ_BASE + 32)
-                                       /* GRP4 IRQ numbers start here */
-#define GROUP2_IRQ_BASE                (GROUP1_IRQ_BASE + 32)
-                                       /* GRP5 IRQ numbers start here */
-#define GROUP3_IRQ_BASE                (GROUP2_IRQ_BASE + 32)
-#define GROUP4_IRQ_BASE                (GROUP3_IRQ_BASE + 32)
-
-
-#ifdef __MIPSEB__
-#define RC32434_UART0_BASE     (RC32434_REG_BASE + 0x58003)
-#else
-#define RC32434_UART0_BASE     (RC32434_REG_BASE + 0x58000)
-#endif
-
-#define RC32434_UART0_IRQ      (GROUP3_IRQ_BASE + 0)
 
 /* cpu pipeline flush */
 static inline void rc32434_sync(void)