drm/amdgpu: Fix 32bit x86 compilation warning

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:187:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:3: warning: right shift count >= width of type [enabled by default]

v2: Add a space between "&" and "0xff"

Reported by: kbuild-all@01.org

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index dd486377fb414ded38494633a2112932eaeddb6b..30ef3126c8a9682c883012d6c183f58074a8abb2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -172,7 +172,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
                (u32)(adev->dummy_page.addr >> 12));
        WREG32(SOC15_REG_OFFSET(GC, 0,
                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
-               (u32)(adev->dummy_page.addr >> 44));
+               (u32)((u64)adev->dummy_page.addr >> 44));
 
        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index c1dc8c4d6cc4ae93e245bc0ca2c1c74adab850ec..266a0f47a9086a714496c457bf6bd81167b3015d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -186,7 +186,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
                (u32)(adev->dummy_page.addr >> 12));
        WREG32(SOC15_REG_OFFSET(MMHUB, 0,
                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
-               (u32)(adev->dummy_page.addr >> 44));
+               (u32)((u64)adev->dummy_page.addr >> 44));
 
        tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
        tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 23371e1c09ef1cd896ea3e5e94d4e59e7dd3578f..071f56e439bb67e76dc054d36fc14b63f5b62e6a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -103,7 +103,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
        /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
        if (adev->irq.ih.use_bus_addr) {
                WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
-               WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.rb_dma_addr >> 40) &0xff);
+               WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
        } else {
                WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);