# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg
+ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \
+ -Idrivers/gpu/drm/amd/include
amdgpu-y := amdgpu_drv.o
#include <drm/drm_gem.h>
+#include "amd_shared.h"
#include "amdgpu_family.h"
#include "amdgpu_mode.h"
#include "amdgpu_ih.h"
AMDGPU_THERMAL_IRQ_LAST
};
-/*
- * IP block functions
- */
-enum amdgpu_ip_block_type {
- AMDGPU_IP_BLOCK_TYPE_COMMON,
- AMDGPU_IP_BLOCK_TYPE_GMC,
- AMDGPU_IP_BLOCK_TYPE_IH,
- AMDGPU_IP_BLOCK_TYPE_SMC,
- AMDGPU_IP_BLOCK_TYPE_DCE,
- AMDGPU_IP_BLOCK_TYPE_GFX,
- AMDGPU_IP_BLOCK_TYPE_SDMA,
- AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_IP_BLOCK_TYPE_VCE,
-};
-
-enum amdgpu_clockgating_state {
- AMDGPU_CG_STATE_GATE = 0,
- AMDGPU_CG_STATE_UNGATE,
-};
-
-enum amdgpu_powergating_state {
- AMDGPU_PG_STATE_GATE = 0,
- AMDGPU_PG_STATE_UNGATE,
-};
-
-struct amdgpu_ip_funcs {
- /* sets up early driver state (pre sw_init), does not configure hw - Optional */
- int (*early_init)(struct amdgpu_device *adev);
- /* sets up late driver/hw state (post hw_init) - Optional */
- int (*late_init)(struct amdgpu_device *adev);
- /* sets up driver state, does not configure hw */
- int (*sw_init)(struct amdgpu_device *adev);
- /* tears down driver state, does not configure hw */
- int (*sw_fini)(struct amdgpu_device *adev);
- /* sets up the hw state */
- int (*hw_init)(struct amdgpu_device *adev);
- /* tears down the hw state */
- int (*hw_fini)(struct amdgpu_device *adev);
- /* handles IP specific hw/sw changes for suspend */
- int (*suspend)(struct amdgpu_device *adev);
- /* handles IP specific hw/sw changes for resume */
- int (*resume)(struct amdgpu_device *adev);
- /* returns current IP block idle status */
- bool (*is_idle)(struct amdgpu_device *adev);
- /* poll for idle */
- int (*wait_for_idle)(struct amdgpu_device *adev);
- /* soft reset the IP block */
- int (*soft_reset)(struct amdgpu_device *adev);
- /* dump the IP block status registers */
- void (*print_status)(struct amdgpu_device *adev);
- /* enable/disable cg for the IP block */
- int (*set_clockgating_state)(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state);
- /* enable/disable pg for the IP block */
- int (*set_powergating_state)(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state);
-};
-
int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type block_type,
- enum amdgpu_clockgating_state state);
+ enum amd_ip_block_type block_type,
+ enum amd_clockgating_state state);
int amdgpu_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type block_type,
- enum amdgpu_powergating_state state);
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state);
struct amdgpu_ip_block_version {
- enum amdgpu_ip_block_type type;
+ enum amd_ip_block_type type;
u32 major;
u32 minor;
u32 rev;
- const struct amdgpu_ip_funcs *funcs;
+ const struct amd_ip_funcs *funcs;
};
int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type type,
+ enum amd_ip_block_type type,
u32 major, u32 minor);
const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
struct amdgpu_device *adev,
- enum amdgpu_ip_block_type type);
+ enum amd_ip_block_type type);
/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
struct amdgpu_buffer_funcs {
};
int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type block_type,
- enum amdgpu_clockgating_state state)
+ enum amd_ip_block_type block_type,
+ enum amd_clockgating_state state)
{
int i, r = 0;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (adev->ip_blocks[i].type == block_type) {
- r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
+ r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
state);
if (r)
return r;
}
int amdgpu_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type block_type,
- enum amdgpu_powergating_state state)
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state)
{
int i, r = 0;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (adev->ip_blocks[i].type == block_type) {
- r = adev->ip_blocks[i].funcs->set_powergating_state(adev,
+ r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
state);
if (r)
return r;
const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
struct amdgpu_device *adev,
- enum amdgpu_ip_block_type type)
+ enum amd_ip_block_type type)
{
int i;
* amdgpu_ip_block_version_cmp
*
* @adev: amdgpu_device pointer
- * @type: enum amdgpu_ip_block_type
+ * @type: enum amd_ip_block_type
* @major: major version
* @minor: minor version
*
* return 1 if smaller or the ip_block doesn't exist
*/
int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
- enum amdgpu_ip_block_type type,
+ enum amd_ip_block_type type,
u32 major, u32 minor)
{
const struct amdgpu_ip_block_version *ip_block;
adev->ip_block_enabled[i] = false;
} else {
if (adev->ip_blocks[i].funcs->early_init) {
- r = adev->ip_blocks[i].funcs->early_init(adev);
+ r = adev->ip_blocks[i].funcs->early_init((void *)adev);
if (r)
return r;
}
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_block_enabled[i])
continue;
- r = adev->ip_blocks[i].funcs->sw_init(adev);
+ r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
if (r)
return r;
/* need to do gmc hw init early so we can allocate gpu mem */
- if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {
+ if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
r = amdgpu_vram_scratch_init(adev);
if (r)
return r;
- r = adev->ip_blocks[i].funcs->hw_init(adev);
+ r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
if (r)
return r;
r = amdgpu_wb_init(adev);
if (!adev->ip_block_enabled[i])
continue;
/* gmc hw init is done early */
- if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC)
+ if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
continue;
- r = adev->ip_blocks[i].funcs->hw_init(adev);
+ r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
if (r)
return r;
}
if (!adev->ip_block_enabled[i])
continue;
/* enable clockgating to save power */
- r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
- AMDGPU_CG_STATE_GATE);
+ r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
+ AMD_CG_STATE_GATE);
if (r)
return r;
if (adev->ip_blocks[i].funcs->late_init) {
- r = adev->ip_blocks[i].funcs->late_init(adev);
+ r = adev->ip_blocks[i].funcs->late_init((void *)adev);
if (r)
return r;
}
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_block_enabled[i])
continue;
- if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {
+ if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
amdgpu_wb_fini(adev);
amdgpu_vram_scratch_fini(adev);
}
/* ungate blocks before hw fini so that we can shutdown the blocks safely */
- r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
- AMDGPU_CG_STATE_UNGATE);
+ r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
+ AMD_CG_STATE_UNGATE);
if (r)
return r;
- r = adev->ip_blocks[i].funcs->hw_fini(adev);
+ r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
/* XXX handle errors */
}
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_block_enabled[i])
continue;
- r = adev->ip_blocks[i].funcs->sw_fini(adev);
+ r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
/* XXX handle errors */
adev->ip_block_enabled[i] = false;
}
if (!adev->ip_block_enabled[i])
continue;
/* ungate blocks so that suspend can properly shut them down */
- r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
- AMDGPU_CG_STATE_UNGATE);
+ r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
+ AMD_CG_STATE_UNGATE);
/* XXX handle errors */
r = adev->ip_blocks[i].funcs->suspend(adev);
/* XXX handle errors */
return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
case AMDGPU_INFO_HW_IP_INFO: {
struct drm_amdgpu_info_hw_ip ip = {};
- enum amdgpu_ip_block_type type;
+ enum amd_ip_block_type type;
uint32_t ring_mask = 0;
if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
switch (info->query_hw_ip.type) {
case AMDGPU_HW_IP_GFX:
- type = AMDGPU_IP_BLOCK_TYPE_GFX;
+ type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
break;
case AMDGPU_HW_IP_COMPUTE:
- type = AMDGPU_IP_BLOCK_TYPE_GFX;
+ type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_compute_rings; i++)
ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
break;
case AMDGPU_HW_IP_DMA:
- type = AMDGPU_IP_BLOCK_TYPE_SDMA;
+ type = AMD_IP_BLOCK_TYPE_SDMA;
ring_mask = adev->sdma[0].ring.ready ? 1 : 0;
ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);
break;
case AMDGPU_HW_IP_UVD:
- type = AMDGPU_IP_BLOCK_TYPE_UVD;
+ type = AMD_IP_BLOCK_TYPE_UVD;
ring_mask = adev->uvd.ring.ready ? 1 : 0;
break;
case AMDGPU_HW_IP_VCE:
- type = AMDGPU_IP_BLOCK_TYPE_VCE;
+ type = AMD_IP_BLOCK_TYPE_VCE;
for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
break;
min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
}
case AMDGPU_INFO_HW_IP_COUNT: {
- enum amdgpu_ip_block_type type;
+ enum amd_ip_block_type type;
uint32_t count = 0;
switch (info->query_hw_ip.type) {
case AMDGPU_HW_IP_GFX:
- type = AMDGPU_IP_BLOCK_TYPE_GFX;
+ type = AMD_IP_BLOCK_TYPE_GFX;
break;
case AMDGPU_HW_IP_COMPUTE:
- type = AMDGPU_IP_BLOCK_TYPE_GFX;
+ type = AMD_IP_BLOCK_TYPE_GFX;
break;
case AMDGPU_HW_IP_DMA:
- type = AMDGPU_IP_BLOCK_TYPE_SDMA;
+ type = AMD_IP_BLOCK_TYPE_SDMA;
break;
case AMDGPU_HW_IP_UVD:
- type = AMDGPU_IP_BLOCK_TYPE_UVD;
+ type = AMD_IP_BLOCK_TYPE_UVD;
break;
case AMDGPU_HW_IP_VCE:
- type = AMDGPU_IP_BLOCK_TYPE_VCE;
+ type = AMD_IP_BLOCK_TYPE_VCE;
break;
default:
return -EINVAL;
}
/* from uvd v5.0 HW addressing capacity increased to 64 bits */
- if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0))
+ if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
adev->uvd.address_64_bit = true;
return 0;
if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
if (amdgpu_new_state->evclk) {
/* turn the clocks on when encoding */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_CG_STATE_UNGATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_UNGATE);
if (ret)
return ret;
ret = ci_enable_vce_dpm(adev, true);
} else {
/* turn the clocks off when not encoding */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_CG_STATE_GATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_GATE);
if (ret)
return ret;
return ret;
}
-static int ci_dpm_early_init(struct amdgpu_device *adev)
+static int ci_dpm_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
ci_dpm_set_dpm_funcs(adev);
ci_dpm_set_irq_funcs(adev);
return 0;
}
-static int ci_dpm_late_init(struct amdgpu_device *adev)
+static int ci_dpm_late_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (!amdgpu_dpm)
return 0;
return 0;
}
-static int ci_dpm_sw_init(struct amdgpu_device *adev)
+static int ci_dpm_sw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
if (ret)
return ret;
}
-static int ci_dpm_sw_fini(struct amdgpu_device *adev)
+static int ci_dpm_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
mutex_lock(&adev->pm.mutex);
amdgpu_pm_sysfs_fini(adev);
ci_dpm_fini(adev);
return 0;
}
-static int ci_dpm_hw_init(struct amdgpu_device *adev)
+static int ci_dpm_hw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (!amdgpu_dpm)
return 0;
return ret;
}
-static int ci_dpm_hw_fini(struct amdgpu_device *adev)
+static int ci_dpm_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
ci_dpm_disable(adev);
return 0;
}
-static int ci_dpm_suspend(struct amdgpu_device *adev)
+static int ci_dpm_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
/* disable dpm */
return 0;
}
-static int ci_dpm_resume(struct amdgpu_device *adev)
+static int ci_dpm_resume(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->pm.dpm_enabled) {
/* asic init will reset to the boot state */
return 0;
}
-static bool ci_dpm_is_idle(struct amdgpu_device *adev)
+static bool ci_dpm_is_idle(void *handle)
{
/* XXX */
return true;
}
-static int ci_dpm_wait_for_idle(struct amdgpu_device *adev)
+static int ci_dpm_wait_for_idle(void *handle)
{
/* XXX */
return 0;
}
-static void ci_dpm_print_status(struct amdgpu_device *adev)
+static void ci_dpm_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "CIK DPM registers\n");
dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
RREG32(mmBIOS_SCRATCH_4));
RREG32_SMC(ixSMC_PC_C));
}
-static int ci_dpm_soft_reset(struct amdgpu_device *adev)
+static int ci_dpm_soft_reset(void *handle)
{
return 0;
}
return 0;
}
-static int ci_dpm_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int ci_dpm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int ci_dpm_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int ci_dpm_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs ci_dpm_ip_funcs = {
+const struct amd_ip_funcs ci_dpm_ip_funcs = {
.early_init = ci_dpm_early_init,
.late_init = ci_dpm_late_init,
.sw_init = ci_dpm_sw_init,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &cik_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &gmc_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &ci_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 8,
.minor = 2,
.rev = 0,
.funcs = &dce_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 7,
.minor = 2,
.rev = 0,
.funcs = &gfx_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_sdma_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 4,
.minor = 2,
.rev = 0,
.funcs = &uvd_v4_2_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 2,
.minor = 0,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &cik_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &gmc_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &ci_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 8,
.minor = 5,
.rev = 0,
.funcs = &dce_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 7,
.minor = 3,
.rev = 0,
.funcs = &gfx_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_sdma_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 4,
.minor = 2,
.rev = 0,
.funcs = &uvd_v4_2_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 2,
.minor = 0,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &cik_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &gmc_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &kv_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 8,
.minor = 3,
.rev = 0,
.funcs = &dce_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 7,
.minor = 2,
.rev = 0,
.funcs = &gfx_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_sdma_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 4,
.minor = 2,
.rev = 0,
.funcs = &uvd_v4_2_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 2,
.minor = 0,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &cik_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &gmc_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &kv_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 8,
.minor = 3,
.rev = 0,
.funcs = &dce_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 7,
.minor = 2,
.rev = 0,
.funcs = &gfx_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_sdma_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 4,
.minor = 2,
.rev = 0,
.funcs = &uvd_v4_2_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 2,
.minor = 0,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &cik_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &gmc_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 0,
.rev = 0,
.funcs = &kv_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 8,
.minor = 1,
.rev = 0,
.funcs = &dce_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 7,
.minor = 1,
.rev = 0,
.funcs = &gfx_v7_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &cik_sdma_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 4,
.minor = 2,
.rev = 0,
.funcs = &uvd_v4_2_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 2,
.minor = 0,
.rev = 0,
.wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
};
-static int cik_common_early_init(struct amdgpu_device *adev)
+static int cik_common_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
adev->smc_rreg = &cik_smc_rreg;
adev->smc_wreg = &cik_smc_wreg;
adev->pcie_rreg = &cik_pcie_rreg;
return 0;
}
-static int cik_common_sw_init(struct amdgpu_device *adev)
+static int cik_common_sw_init(void *handle)
{
return 0;
}
-static int cik_common_sw_fini(struct amdgpu_device *adev)
+static int cik_common_sw_fini(void *handle)
{
return 0;
}
-static int cik_common_hw_init(struct amdgpu_device *adev)
+static int cik_common_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
/* move the golden regs per IP block */
cik_init_golden_registers(adev);
/* enable pcie gen2/3 link */
return 0;
}
-static int cik_common_hw_fini(struct amdgpu_device *adev)
+static int cik_common_hw_fini(void *handle)
{
return 0;
}
-static int cik_common_suspend(struct amdgpu_device *adev)
+static int cik_common_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cik_common_hw_fini(adev);
}
-static int cik_common_resume(struct amdgpu_device *adev)
+static int cik_common_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cik_common_hw_init(adev);
}
-static bool cik_common_is_idle(struct amdgpu_device *adev)
+static bool cik_common_is_idle(void *handle)
{
return true;
}
-static int cik_common_wait_for_idle(struct amdgpu_device *adev)
+static int cik_common_wait_for_idle(void *handle)
{
return 0;
}
-static void cik_common_print_status(struct amdgpu_device *adev)
+static void cik_common_print_status(void *handle)
{
}
-static int cik_common_soft_reset(struct amdgpu_device *adev)
+static int cik_common_soft_reset(void *handle)
{
/* XXX hard reset?? */
return 0;
}
-static int cik_common_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cik_common_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int cik_common_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cik_common_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs cik_common_ip_funcs = {
+const struct amd_ip_funcs cik_common_ip_funcs = {
.early_init = cik_common_early_init,
.late_init = NULL,
.sw_init = cik_common_sw_init,
#ifndef __CIK_H__
#define __CIK_H__
-extern const struct amdgpu_ip_funcs cik_common_ip_funcs;
+extern const struct amd_ip_funcs cik_common_ip_funcs;
void cik_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
#ifndef __CIK_DPM_H__
#define __CIK_DPM_H__
-extern const struct amdgpu_ip_funcs ci_dpm_ip_funcs;
-extern const struct amdgpu_ip_funcs kv_dpm_ip_funcs;
+extern const struct amd_ip_funcs ci_dpm_ip_funcs;
+extern const struct amd_ip_funcs kv_dpm_ip_funcs;
#endif
WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}
-static int cik_ih_early_init(struct amdgpu_device *adev)
+static int cik_ih_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cik_ih_set_interrupt_funcs(adev);
return 0;
}
-static int cik_ih_sw_init(struct amdgpu_device *adev)
+static int cik_ih_sw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
if (r)
return r;
}
-static int cik_ih_sw_fini(struct amdgpu_device *adev)
+static int cik_ih_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
return 0;
}
-static int cik_ih_hw_init(struct amdgpu_device *adev)
+static int cik_ih_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = cik_ih_irq_init(adev);
if (r)
return 0;
}
-static int cik_ih_hw_fini(struct amdgpu_device *adev)
+static int cik_ih_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cik_ih_irq_disable(adev);
return 0;
}
-static int cik_ih_suspend(struct amdgpu_device *adev)
+static int cik_ih_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cik_ih_hw_fini(adev);
}
-static int cik_ih_resume(struct amdgpu_device *adev)
+static int cik_ih_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cik_ih_hw_init(adev);
}
-static bool cik_ih_is_idle(struct amdgpu_device *adev)
+static bool cik_ih_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
return true;
}
-static int cik_ih_wait_for_idle(struct amdgpu_device *adev)
+static int cik_ih_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void cik_ih_print_status(struct amdgpu_device *adev)
+static void cik_ih_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "CIK IH registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmSRBM_STATUS));
RREG32(mmIH_RB_WPTR));
}
-static int cik_ih_soft_reset(struct amdgpu_device *adev)
+static int cik_ih_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
u32 srbm_soft_reset = 0;
u32 tmp = RREG32(mmSRBM_STATUS);
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
if (srbm_soft_reset) {
- cik_ih_print_status(adev);
+ cik_ih_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- cik_ih_print_status(adev);
+ cik_ih_print_status((void *)adev);
}
return 0;
}
-static int cik_ih_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cik_ih_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int cik_ih_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cik_ih_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs cik_ih_ip_funcs = {
+const struct amd_ip_funcs cik_ih_ip_funcs = {
.early_init = cik_ih_early_init,
.late_init = NULL,
.sw_init = cik_ih_sw_init,
#ifndef __CIK_IH_H__
#define __CIK_IH_H__
-extern const struct amdgpu_ip_funcs cik_ih_ip_funcs;
+extern const struct amd_ip_funcs cik_ih_ip_funcs;
#endif
}
}
-static int cik_sdma_early_init(struct amdgpu_device *adev)
+static int cik_sdma_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cik_sdma_set_ring_funcs(adev);
cik_sdma_set_irq_funcs(adev);
cik_sdma_set_buffer_funcs(adev);
return 0;
}
-static int cik_sdma_sw_init(struct amdgpu_device *adev)
+static int cik_sdma_sw_init(void *handle)
{
struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
r = cik_sdma_init_microcode(adev);
return r;
}
-static int cik_sdma_sw_fini(struct amdgpu_device *adev)
+static int cik_sdma_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_ring_fini(&adev->sdma[0].ring);
amdgpu_ring_fini(&adev->sdma[1].ring);
return 0;
}
-static int cik_sdma_hw_init(struct amdgpu_device *adev)
+static int cik_sdma_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = cik_sdma_start(adev);
if (r)
return r;
}
-static int cik_sdma_hw_fini(struct amdgpu_device *adev)
+static int cik_sdma_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cik_sdma_enable(adev, false);
return 0;
}
-static int cik_sdma_suspend(struct amdgpu_device *adev)
+static int cik_sdma_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return cik_sdma_hw_fini(adev);
}
-static int cik_sdma_resume(struct amdgpu_device *adev)
+static int cik_sdma_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return cik_sdma_hw_init(adev);
}
-static bool cik_sdma_is_idle(struct amdgpu_device *adev)
+static bool cik_sdma_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
return true;
}
-static int cik_sdma_wait_for_idle(struct amdgpu_device *adev)
+static int cik_sdma_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
return -ETIMEDOUT;
}
-static void cik_sdma_print_status(struct amdgpu_device *adev)
+static void cik_sdma_print_status(void *handle)
{
int i, j;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "CIK SDMA registers\n");
dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
}
}
-static int cik_sdma_soft_reset(struct amdgpu_device *adev)
+static int cik_sdma_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
}
if (srbm_soft_reset) {
- cik_sdma_print_status(adev);
+ cik_sdma_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- cik_sdma_print_status(adev);
+ cik_sdma_print_status((void *)adev);
}
return 0;
return 0;
}
-static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cik_sdma_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_CG_STATE_GATE)
+ if (state == AMD_CG_STATE_GATE)
gate = true;
cik_enable_sdma_mgcg(adev, gate);
return 0;
}
-static int cik_sdma_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cik_sdma_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs cik_sdma_ip_funcs = {
+const struct amd_ip_funcs cik_sdma_ip_funcs = {
.early_init = cik_sdma_early_init,
.late_init = NULL,
.sw_init = cik_sdma_sw_init,
#ifndef __CIK_SDMA_H__
#define __CIK_SDMA_H__
-extern const struct amdgpu_ip_funcs cik_sdma_ip_funcs;
+extern const struct amd_ip_funcs cik_sdma_ip_funcs;
#endif
static void cz_dpm_set_funcs(struct amdgpu_device *adev);
-static int cz_dpm_early_init(struct amdgpu_device *adev)
+static int cz_dpm_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cz_dpm_set_funcs(adev);
return 0;
}
-static int cz_dpm_late_init(struct amdgpu_device *adev)
+static int cz_dpm_late_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
/* powerdown unused blocks for now */
cz_dpm_powergate_uvd(adev, true);
return 0;
}
-static int cz_dpm_sw_init(struct amdgpu_device *adev)
+static int cz_dpm_sw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret = 0;
/* fix me to add thermal support TODO */
return ret;
}
-static int cz_dpm_sw_fini(struct amdgpu_device *adev)
+static int cz_dpm_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
mutex_lock(&adev->pm.mutex);
amdgpu_pm_sysfs_fini(adev);
cz_dpm_fini(adev);
return 0;
}
-static int cz_dpm_hw_init(struct amdgpu_device *adev)
+static int cz_dpm_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret = 0;
mutex_lock(&adev->pm.mutex);
return 0;
}
-static int cz_dpm_hw_fini(struct amdgpu_device *adev)
+static int cz_dpm_hw_fini(void *handle)
{
int ret = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
mutex_lock(&adev->pm.mutex);
return ret;
}
-static int cz_dpm_suspend(struct amdgpu_device *adev)
+static int cz_dpm_suspend(void *handle)
{
int ret = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
return ret;
}
-static int cz_dpm_resume(struct amdgpu_device *adev)
+static int cz_dpm_resume(void *handle)
{
int ret = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
mutex_lock(&adev->pm.mutex);
ret = cz_smu_init(adev);
return 0;
}
-static int cz_dpm_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cz_dpm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int cz_dpm_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cz_dpm_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
if (gate) {
if (pi->caps_uvd_pg) {
/* disable clockgating so we can properly shut down the block */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_CG_STATE_UNGATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_UNGATE);
/* shutdown the UVD block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_PG_STATE_GATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
/* XXX: check for errors */
}
cz_update_uvd_dpm(adev, gate);
else
cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
/* re-init the UVD block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_PG_STATE_UNGATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_CG_STATE_GATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
/* XXX: check for errors */
}
cz_update_uvd_dpm(adev, gate);
}
}
-const struct amdgpu_ip_funcs cz_dpm_ip_funcs = {
+const struct amd_ip_funcs cz_dpm_ip_funcs = {
.early_init = cz_dpm_early_init,
.late_init = cz_dpm_late_init,
.sw_init = cz_dpm_sw_init,
WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}
-static int cz_ih_early_init(struct amdgpu_device *adev)
+static int cz_ih_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cz_ih_set_interrupt_funcs(adev);
return 0;
}
-static int cz_ih_sw_init(struct amdgpu_device *adev)
+static int cz_ih_sw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
if (r)
return r;
}
-static int cz_ih_sw_fini(struct amdgpu_device *adev)
+static int cz_ih_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
return 0;
}
-static int cz_ih_hw_init(struct amdgpu_device *adev)
+static int cz_ih_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = cz_ih_irq_init(adev);
if (r)
return 0;
}
-static int cz_ih_hw_fini(struct amdgpu_device *adev)
+static int cz_ih_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cz_ih_irq_disable(adev);
return 0;
}
-static int cz_ih_suspend(struct amdgpu_device *adev)
+static int cz_ih_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cz_ih_hw_fini(adev);
}
-static int cz_ih_resume(struct amdgpu_device *adev)
+static int cz_ih_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cz_ih_hw_init(adev);
}
-static bool cz_ih_is_idle(struct amdgpu_device *adev)
+static bool cz_ih_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return true;
}
-static int cz_ih_wait_for_idle(struct amdgpu_device *adev)
+static int cz_ih_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void cz_ih_print_status(struct amdgpu_device *adev)
+static void cz_ih_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "CZ IH registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmSRBM_STATUS));
RREG32(mmIH_RB_WPTR));
}
-static int cz_ih_soft_reset(struct amdgpu_device *adev)
+static int cz_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- cz_ih_print_status(adev);
+ cz_ih_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- cz_ih_print_status(adev);
+ cz_ih_print_status((void *)adev);
}
return 0;
}
-static int cz_ih_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cz_ih_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
// TODO
return 0;
}
-static int cz_ih_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cz_ih_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
// TODO
return 0;
}
-const struct amdgpu_ip_funcs cz_ih_ip_funcs = {
+const struct amd_ip_funcs cz_ih_ip_funcs = {
.early_init = cz_ih_early_init,
.late_init = NULL,
.sw_init = cz_ih_sw_init,
#ifndef __CZ_IH_H__
#define __CZ_IH_H__
-extern const struct amdgpu_ip_funcs cz_ih_ip_funcs;
+extern const struct amd_ip_funcs cz_ih_ip_funcs;
#endif /* __CZ_IH_H__ */
return 0;
}
-static int dce_v10_0_early_init(struct amdgpu_device *adev)
+static int dce_v10_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
return 0;
}
-static int dce_v10_0_sw_init(struct amdgpu_device *adev)
+static int dce_v10_0_sw_init(void *handle)
{
int r, i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
return r;
}
-static int dce_v10_0_sw_fini(struct amdgpu_device *adev)
+static int dce_v10_0_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
kfree(adev->mode_info.bios_hardcoded_edid);
drm_kms_helper_poll_fini(adev->ddev);
return 0;
}
-static int dce_v10_0_hw_init(struct amdgpu_device *adev)
+static int dce_v10_0_hw_init(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v10_0_init_golden_registers(adev);
return 0;
}
-static int dce_v10_0_hw_fini(struct amdgpu_device *adev)
+static int dce_v10_0_hw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v10_0_hpd_fini(adev);
return 0;
}
-static int dce_v10_0_suspend(struct amdgpu_device *adev)
+static int dce_v10_0_suspend(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
drm_kms_helper_poll_disable(adev->ddev);
return 0;
}
-static int dce_v10_0_resume(struct amdgpu_device *adev)
+static int dce_v10_0_resume(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v10_0_init_golden_registers(adev);
return 0;
}
-static bool dce_v10_0_is_idle(struct amdgpu_device *adev)
+static bool dce_v10_0_is_idle(void *handle)
{
- /* XXX todo */
return true;
}
-static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev)
+static int dce_v10_0_wait_for_idle(void *handle)
{
- /* XXX todo */
return 0;
}
-static void dce_v10_0_print_status(struct amdgpu_device *adev)
+static void dce_v10_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "DCE 10.x registers\n");
/* XXX todo */
}
-static int dce_v10_0_soft_reset(struct amdgpu_device *adev)
+static int dce_v10_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (dce_v10_0_is_display_hung(adev))
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v10_0_print_status(adev);
+ dce_v10_0_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- dce_v10_0_print_status(adev);
+ dce_v10_0_print_status((void *)adev);
}
return 0;
}
return 0;
}
-static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int dce_v10_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int dce_v10_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = {
+const struct amd_ip_funcs dce_v10_0_ip_funcs = {
.early_init = dce_v10_0_early_init,
.late_init = NULL,
.sw_init = dce_v10_0_sw_init,
#ifndef __DCE_V10_0_H__
#define __DCE_V10_0_H__
-extern const struct amdgpu_ip_funcs dce_v10_0_ip_funcs;
+extern const struct amd_ip_funcs dce_v10_0_ip_funcs;
#endif
return 0;
}
-static int dce_v11_0_early_init(struct amdgpu_device *adev)
+static int dce_v11_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
return 0;
}
-static int dce_v11_0_sw_init(struct amdgpu_device *adev)
+static int dce_v11_0_sw_init(void *handle)
{
int r, i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
return r;
}
-static int dce_v11_0_sw_fini(struct amdgpu_device *adev)
+static int dce_v11_0_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
kfree(adev->mode_info.bios_hardcoded_edid);
drm_kms_helper_poll_fini(adev->ddev);
return 0;
}
-static int dce_v11_0_hw_init(struct amdgpu_device *adev)
+static int dce_v11_0_hw_init(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v11_0_init_golden_registers(adev);
return 0;
}
-static int dce_v11_0_hw_fini(struct amdgpu_device *adev)
+static int dce_v11_0_hw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v11_0_hpd_fini(adev);
return 0;
}
-static int dce_v11_0_suspend(struct amdgpu_device *adev)
+static int dce_v11_0_suspend(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
drm_kms_helper_poll_disable(adev->ddev);
return 0;
}
-static int dce_v11_0_resume(struct amdgpu_device *adev)
+static int dce_v11_0_resume(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v11_0_init_golden_registers(adev);
return 0;
}
-static bool dce_v11_0_is_idle(struct amdgpu_device *adev)
+static bool dce_v11_0_is_idle(void *handle)
{
- /* XXX todo */
return true;
}
-static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev)
+static int dce_v11_0_wait_for_idle(void *handle)
{
- /* XXX todo */
return 0;
}
-static void dce_v11_0_print_status(struct amdgpu_device *adev)
+static void dce_v11_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "DCE 10.x registers\n");
/* XXX todo */
}
-static int dce_v11_0_soft_reset(struct amdgpu_device *adev)
+static int dce_v11_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (dce_v11_0_is_display_hung(adev))
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v11_0_print_status(adev);
+ dce_v11_0_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- dce_v11_0_print_status(adev);
+ dce_v11_0_print_status((void *)adev);
}
return 0;
}
return 0;
}
-static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int dce_v11_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int dce_v11_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = {
+const struct amd_ip_funcs dce_v11_0_ip_funcs = {
.early_init = dce_v11_0_early_init,
.late_init = NULL,
.sw_init = dce_v11_0_sw_init,
#ifndef __DCE_V11_0_H__
#define __DCE_V11_0_H__
-extern const struct amdgpu_ip_funcs dce_v11_0_ip_funcs;
+extern const struct amd_ip_funcs dce_v11_0_ip_funcs;
#endif
return 0;
}
-static int dce_v8_0_early_init(struct amdgpu_device *adev)
+static int dce_v8_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
return 0;
}
-static int dce_v8_0_sw_init(struct amdgpu_device *adev)
+static int dce_v8_0_sw_init(void *handle)
{
int r, i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
return r;
}
-static int dce_v8_0_sw_fini(struct amdgpu_device *adev)
+static int dce_v8_0_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
kfree(adev->mode_info.bios_hardcoded_edid);
drm_kms_helper_poll_fini(adev->ddev);
return 0;
}
-static int dce_v8_0_hw_init(struct amdgpu_device *adev)
+static int dce_v8_0_hw_init(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* init dig PHYs, disp eng pll */
amdgpu_atombios_encoder_init_dig(adev);
return 0;
}
-static int dce_v8_0_hw_fini(struct amdgpu_device *adev)
+static int dce_v8_0_hw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dce_v8_0_hpd_fini(adev);
return 0;
}
-static int dce_v8_0_suspend(struct amdgpu_device *adev)
+static int dce_v8_0_suspend(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
drm_kms_helper_poll_disable(adev->ddev);
return 0;
}
-static int dce_v8_0_resume(struct amdgpu_device *adev)
+static int dce_v8_0_resume(void *handle)
{
struct drm_connector *connector;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_atombios_scratch_regs_restore(adev);
return 0;
}
-static bool dce_v8_0_is_idle(struct amdgpu_device *adev)
+static bool dce_v8_0_is_idle(void *handle)
{
- /* XXX todo */
return true;
}
-static int dce_v8_0_wait_for_idle(struct amdgpu_device *adev)
+static int dce_v8_0_wait_for_idle(void *handle)
{
- /* XXX todo */
return 0;
}
-static void dce_v8_0_print_status(struct amdgpu_device *adev)
+static void dce_v8_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "DCE 8.x registers\n");
/* XXX todo */
}
-static int dce_v8_0_soft_reset(struct amdgpu_device *adev)
+static int dce_v8_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (dce_v8_0_is_display_hung(adev))
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v8_0_print_status(adev);
+ dce_v8_0_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- dce_v8_0_print_status(adev);
+ dce_v8_0_print_status((void *)adev);
}
return 0;
}
}
-static int dce_v8_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int dce_v8_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int dce_v8_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int dce_v8_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs dce_v8_0_ip_funcs = {
+const struct amd_ip_funcs dce_v8_0_ip_funcs = {
.early_init = dce_v8_0_early_init,
.late_init = NULL,
.sw_init = dce_v8_0_sw_init,
#ifndef __DCE_V8_0_H__
#define __DCE_V8_0_H__
-extern const struct amdgpu_ip_funcs dce_v8_0_ip_funcs;
+extern const struct amd_ip_funcs dce_v8_0_ip_funcs;
#endif
amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
}
-static int gfx_v7_0_early_init(struct amdgpu_device *adev)
+static int gfx_v7_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
return 0;
}
-static int gfx_v7_0_sw_init(struct amdgpu_device *adev)
+static int gfx_v7_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i, r;
/* EOP Event */
return r;
}
-static int gfx_v7_0_sw_fini(struct amdgpu_device *adev)
+static int gfx_v7_0_sw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
return 0;
}
-static int gfx_v7_0_hw_init(struct amdgpu_device *adev)
+static int gfx_v7_0_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfx_v7_0_gpu_init(adev);
return r;
}
-static int gfx_v7_0_hw_fini(struct amdgpu_device *adev)
+static int gfx_v7_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gfx_v7_0_cp_enable(adev, false);
gfx_v7_0_rlc_stop(adev);
gfx_v7_0_fini_pg(adev);
return 0;
}
-static int gfx_v7_0_suspend(struct amdgpu_device *adev)
+static int gfx_v7_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return gfx_v7_0_hw_fini(adev);
}
-static int gfx_v7_0_resume(struct amdgpu_device *adev)
+static int gfx_v7_0_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return gfx_v7_0_hw_init(adev);
}
-static bool gfx_v7_0_is_idle(struct amdgpu_device *adev)
+static bool gfx_v7_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
return false;
else
return true;
}
-static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev)
+static int gfx_v7_0_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void gfx_v7_0_print_status(struct amdgpu_device *adev)
+static void gfx_v7_0_print_status(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "GFX 7.x registers\n");
dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
mutex_unlock(&adev->srbm_mutex);
}
-static int gfx_v7_0_soft_reset(struct amdgpu_device *adev)
+static int gfx_v7_0_soft_reset(void *handle)
{
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* GRBM_STATUS */
tmp = RREG32(mmGRBM_STATUS);
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
if (grbm_soft_reset || srbm_soft_reset) {
- gfx_v7_0_print_status(adev);
+ gfx_v7_0_print_status((void *)adev);
/* disable CG/PG */
gfx_v7_0_fini_pg(adev);
gfx_v7_0_update_cg(adev, false);
}
/* Wait a little for things to settle down */
udelay(50);
- gfx_v7_0_print_status(adev);
+ gfx_v7_0_print_status((void *)adev);
}
return 0;
}
return 0;
}
-static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int gfx_v7_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_CG_STATE_GATE)
+ if (state == AMD_CG_STATE_GATE)
gate = true;
gfx_v7_0_enable_gui_idle_interrupt(adev, false);
return 0;
}
-static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int gfx_v7_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_PG_STATE_GATE)
+ if (state == AMD_PG_STATE_GATE)
gate = true;
if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
return 0;
}
-const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = {
+const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.early_init = gfx_v7_0_early_init,
.late_init = NULL,
.sw_init = gfx_v7_0_sw_init,
#ifndef __GFX_V7_0_H__
#define __GFX_V7_0_H__
-extern const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs;
+extern const struct amd_ip_funcs gfx_v7_0_ip_funcs;
/* XXX these shouldn't be exported */
void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev);
return 0;
}
-static int gfx_v8_0_sw_init(struct amdgpu_device *adev)
+static int gfx_v8_0_sw_init(void *handle)
{
int i, r;
struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* EOP Event */
r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
return 0;
}
-static int gfx_v8_0_sw_fini(struct amdgpu_device *adev)
+static int gfx_v8_0_sw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
gfx_v8_0_cp_compute_enable(adev, enable);
}
-static int gfx_v8_0_hw_init(struct amdgpu_device *adev)
+static int gfx_v8_0_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfx_v8_0_init_golden_registers(adev);
return r;
}
-static int gfx_v8_0_hw_fini(struct amdgpu_device *adev)
+static int gfx_v8_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gfx_v8_0_cp_enable(adev, false);
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_cp_compute_fini(adev);
return 0;
}
-static int gfx_v8_0_suspend(struct amdgpu_device *adev)
+static int gfx_v8_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return gfx_v8_0_hw_fini(adev);
}
-static int gfx_v8_0_resume(struct amdgpu_device *adev)
+static int gfx_v8_0_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return gfx_v8_0_hw_init(adev);
}
-static bool gfx_v8_0_is_idle(struct amdgpu_device *adev)
+static bool gfx_v8_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
return false;
else
return true;
}
-static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev)
+static int gfx_v8_0_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void gfx_v8_0_print_status(struct amdgpu_device *adev)
+static void gfx_v8_0_print_status(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "GFX 8.x registers\n");
dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
mutex_unlock(&adev->srbm_mutex);
}
-static int gfx_v8_0_soft_reset(struct amdgpu_device *adev)
+static int gfx_v8_0_soft_reset(void *handle)
{
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* GRBM_STATUS */
tmp = RREG32(mmGRBM_STATUS);
SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
if (grbm_soft_reset || srbm_soft_reset) {
- gfx_v8_0_print_status(adev);
+ gfx_v8_0_print_status((void *)adev);
/* stop the rlc */
gfx_v8_0_rlc_stop(adev);
}
/* Wait a little for things to settle down */
udelay(50);
- gfx_v8_0_print_status(adev);
+ gfx_v8_0_print_status((void *)adev);
}
return 0;
}
amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
}
-static int gfx_v8_0_early_init(struct amdgpu_device *adev)
+static int gfx_v8_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
return 0;
}
-static int gfx_v8_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int gfx_v8_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-static int gfx_v8_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int gfx_v8_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
return 0;
}
-const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs = {
+const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.early_init = gfx_v8_0_early_init,
.late_init = NULL,
.sw_init = gfx_v8_0_sw_init,
#ifndef __GFX_V8_0_H__
#define __GFX_V8_0_H__
-extern const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs;
+extern const struct amd_ip_funcs gfx_v8_0_ip_funcs;
uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev);
void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
WREG32(mmHDP_MEM_POWER_LS, data);
}
-static int gmc_v7_0_early_init(struct amdgpu_device *adev)
+static int gmc_v7_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gmc_v7_0_set_gart_funcs(adev);
gmc_v7_0_set_irq_funcs(adev);
return 0;
}
-static int gmc_v7_0_sw_init(struct amdgpu_device *adev)
+static int gmc_v7_0_sw_init(void *handle)
{
int r;
int dma_bits;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_gem_init(adev);
if (r)
return r;
}
-static int gmc_v7_0_sw_fini(struct amdgpu_device *adev)
+static int gmc_v7_0_sw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->vm_manager.enabled) {
for (i = 0; i < AMDGPU_NUM_VM; ++i)
return 0;
}
-static int gmc_v7_0_hw_init(struct amdgpu_device *adev)
+static int gmc_v7_0_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v7_0_mc_program(adev);
return r;
}
-static int gmc_v7_0_hw_fini(struct amdgpu_device *adev)
+static int gmc_v7_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gmc_v7_0_gart_disable(adev);
return 0;
}
-static int gmc_v7_0_suspend(struct amdgpu_device *adev)
+static int gmc_v7_0_suspend(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->vm_manager.enabled) {
for (i = 0; i < AMDGPU_NUM_VM; ++i)
return 0;
}
-static int gmc_v7_0_resume(struct amdgpu_device *adev)
+static int gmc_v7_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = gmc_v7_0_hw_init(adev);
if (r)
return r;
}
-static bool gmc_v7_0_is_idle(struct amdgpu_device *adev)
+static bool gmc_v7_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
return true;
}
-static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev)
+static int gmc_v7_0_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
}
-static void gmc_v7_0_print_status(struct amdgpu_device *adev)
+static void gmc_v7_0_print_status(void *handle)
{
int i, j;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "GMC 8.x registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmBIF_FB_EN));
}
-static int gmc_v7_0_soft_reset(struct amdgpu_device *adev)
+static int gmc_v7_0_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_mode_mc_save save;
u32 srbm_soft_reset = 0;
u32 tmp = RREG32(mmSRBM_STATUS);
}
if (srbm_soft_reset) {
- gmc_v7_0_print_status(adev);
+ gmc_v7_0_print_status((void *)adev);
gmc_v7_0_mc_stop(adev, &save);
if (gmc_v7_0_wait_for_idle(adev)) {
gmc_v7_0_mc_resume(adev, &save);
udelay(50);
- gmc_v7_0_print_status(adev);
+ gmc_v7_0_print_status((void *)adev);
}
return 0;
return 0;
}
-static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int gmc_v7_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_CG_STATE_GATE)
+ if (state == AMD_CG_STATE_GATE)
gate = true;
if (!(adev->flags & AMDGPU_IS_APU)) {
return 0;
}
-static int gmc_v7_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int gmc_v7_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs = {
+const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
.early_init = gmc_v7_0_early_init,
.late_init = NULL,
.sw_init = gmc_v7_0_sw_init,
#ifndef __GMC_V7_0_H__
#define __GMC_V7_0_H__
-extern const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs;
+extern const struct amd_ip_funcs gmc_v7_0_ip_funcs;
/* XXX these shouldn't be exported */
void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
"write" : "read", block, mc_client, mc_id);
}
-static int gmc_v8_0_early_init(struct amdgpu_device *adev)
+static int gmc_v8_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gmc_v8_0_set_gart_funcs(adev);
gmc_v8_0_set_irq_funcs(adev);
return 0;
}
-static int gmc_v8_0_sw_init(struct amdgpu_device *adev)
+static int gmc_v8_0_sw_init(void *handle)
{
int r;
int dma_bits;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_gem_init(adev);
if (r)
return r;
}
-static int gmc_v8_0_sw_fini(struct amdgpu_device *adev)
+static int gmc_v8_0_sw_fini(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->vm_manager.enabled) {
for (i = 0; i < AMDGPU_NUM_VM; ++i)
return 0;
}
-static int gmc_v8_0_hw_init(struct amdgpu_device *adev)
+static int gmc_v8_0_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v8_0_init_golden_registers(adev);
return r;
}
-static int gmc_v8_0_hw_fini(struct amdgpu_device *adev)
+static int gmc_v8_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
gmc_v8_0_gart_disable(adev);
return 0;
}
-static int gmc_v8_0_suspend(struct amdgpu_device *adev)
+static int gmc_v8_0_suspend(void *handle)
{
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->vm_manager.enabled) {
for (i = 0; i < AMDGPU_NUM_VM; ++i)
return 0;
}
-static int gmc_v8_0_resume(struct amdgpu_device *adev)
+static int gmc_v8_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = gmc_v8_0_hw_init(adev);
if (r)
return r;
}
-static bool gmc_v8_0_is_idle(struct amdgpu_device *adev)
+static bool gmc_v8_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
return true;
}
-static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev)
+static int gmc_v8_0_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
}
-static void gmc_v8_0_print_status(struct amdgpu_device *adev)
+static void gmc_v8_0_print_status(void *handle)
{
int i, j;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "GMC 8.x registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmBIF_FB_EN));
}
-static int gmc_v8_0_soft_reset(struct amdgpu_device *adev)
+static int gmc_v8_0_soft_reset(void *handle)
{
struct amdgpu_mode_mc_save save;
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
}
if (srbm_soft_reset) {
- gmc_v8_0_print_status(adev);
+ gmc_v8_0_print_status((void *)adev);
gmc_v8_0_mc_stop(adev, &save);
if (gmc_v8_0_wait_for_idle(adev)) {
gmc_v8_0_mc_resume(adev, &save);
udelay(50);
- gmc_v8_0_print_status(adev);
+ gmc_v8_0_print_status((void *)adev);
}
return 0;
return 0;
}
-static int gmc_v8_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int gmc_v8_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- /* XXX handled via the smc on VI */
-
return 0;
}
-static int gmc_v8_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int gmc_v8_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs = {
+const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
.early_init = gmc_v8_0_early_init,
.late_init = NULL,
.sw_init = gmc_v8_0_sw_init,
#ifndef __GMC_V8_0_H__
#define __GMC_V8_0_H__
-extern const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs;
+extern const struct amd_ip_funcs gmc_v8_0_ip_funcs;
/* XXX these shouldn't be exported */
void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
static void iceland_dpm_set_funcs(struct amdgpu_device *adev);
-static int iceland_dpm_early_init(struct amdgpu_device *adev)
+static int iceland_dpm_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
iceland_dpm_set_funcs(adev);
return 0;
return err;
}
-static int iceland_dpm_sw_init(struct amdgpu_device *adev)
+static int iceland_dpm_sw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
ret = iceland_dpm_init_microcode(adev);
if (ret)
return 0;
}
-static int iceland_dpm_sw_fini(struct amdgpu_device *adev)
+static int iceland_dpm_sw_fini(void *handle)
{
return 0;
}
-static int iceland_dpm_hw_init(struct amdgpu_device *adev)
+static int iceland_dpm_hw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
mutex_lock(&adev->pm.mutex);
return -EINVAL;
}
-static int iceland_dpm_hw_fini(struct amdgpu_device *adev)
+static int iceland_dpm_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
mutex_lock(&adev->pm.mutex);
iceland_smu_fini(adev);
mutex_unlock(&adev->pm.mutex);
return 0;
}
-static int iceland_dpm_suspend(struct amdgpu_device *adev)
+static int iceland_dpm_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
iceland_dpm_hw_fini(adev);
return 0;
}
-static int iceland_dpm_resume(struct amdgpu_device *adev)
+static int iceland_dpm_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
iceland_dpm_hw_init(adev);
return 0;
}
-static int iceland_dpm_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int iceland_dpm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int iceland_dpm_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int iceland_dpm_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs iceland_dpm_ip_funcs = {
+const struct amd_ip_funcs iceland_dpm_ip_funcs = {
.early_init = iceland_dpm_early_init,
.late_init = NULL,
.sw_init = iceland_dpm_sw_init,
WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}
-static int iceland_ih_early_init(struct amdgpu_device *adev)
+static int iceland_ih_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
iceland_ih_set_interrupt_funcs(adev);
return 0;
}
-static int iceland_ih_sw_init(struct amdgpu_device *adev)
+static int iceland_ih_sw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
if (r)
return r;
}
-static int iceland_ih_sw_fini(struct amdgpu_device *adev)
+static int iceland_ih_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
return 0;
}
-static int iceland_ih_hw_init(struct amdgpu_device *adev)
+static int iceland_ih_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = iceland_ih_irq_init(adev);
if (r)
return 0;
}
-static int iceland_ih_hw_fini(struct amdgpu_device *adev)
+static int iceland_ih_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
iceland_ih_irq_disable(adev);
return 0;
}
-static int iceland_ih_suspend(struct amdgpu_device *adev)
+static int iceland_ih_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return iceland_ih_hw_fini(adev);
}
-static int iceland_ih_resume(struct amdgpu_device *adev)
+static int iceland_ih_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return iceland_ih_hw_init(adev);
}
-static bool iceland_ih_is_idle(struct amdgpu_device *adev)
+static bool iceland_ih_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return true;
}
-static int iceland_ih_wait_for_idle(struct amdgpu_device *adev)
+static int iceland_ih_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void iceland_ih_print_status(struct amdgpu_device *adev)
+static void iceland_ih_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "ICELAND IH registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmSRBM_STATUS));
RREG32(mmIH_RB_WPTR));
}
-static int iceland_ih_soft_reset(struct amdgpu_device *adev)
+static int iceland_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- iceland_ih_print_status(adev);
+ iceland_ih_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- iceland_ih_print_status(adev);
+ iceland_ih_print_status((void *)adev);
}
return 0;
}
-static int iceland_ih_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int iceland_ih_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- // TODO
return 0;
}
-static int iceland_ih_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int iceland_ih_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
- // TODO
return 0;
}
-const struct amdgpu_ip_funcs iceland_ih_ip_funcs = {
+const struct amd_ip_funcs iceland_ih_ip_funcs = {
.early_init = iceland_ih_early_init,
.late_init = NULL,
.sw_init = iceland_ih_sw_init,
#ifndef __ICELAND_IH_H__
#define __ICELAND_IH_H__
-extern const struct amdgpu_ip_funcs iceland_ih_ip_funcs;
+extern const struct amd_ip_funcs iceland_ih_ip_funcs;
#endif /* __ICELAND_IH_H__ */
if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
kv_dpm_powergate_vce(adev, false);
/* turn the clocks on when encoding */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_CG_STATE_UNGATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_UNGATE);
if (ret)
return ret;
if (pi->caps_stable_p_state)
} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
kv_enable_vce_dpm(adev, false);
/* turn the clocks off when not encoding */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_CG_STATE_GATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_CG_STATE_GATE);
if (ret)
return ret;
kv_dpm_powergate_vce(adev, true);
if (gate) {
if (pi->caps_uvd_pg) {
/* disable clockgating so we can properly shut down the block */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_CG_STATE_UNGATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_UNGATE);
/* shutdown the UVD block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_PG_STATE_GATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_GATE);
/* XXX: check for errors */
}
kv_update_uvd_dpm(adev, gate);
/* power on the UVD block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
/* re-init the UVD block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_PG_STATE_UNGATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
- ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
- AMDGPU_CG_STATE_GATE);
+ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
/* XXX: check for errors */
}
kv_update_uvd_dpm(adev, gate);
if (gate) {
if (pi->caps_vce_pg) {
/* shutdown the VCE block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_PG_STATE_GATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_GATE);
/* XXX: check for errors */
/* power off the VCE block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
/* power on the VCE block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
/* re-init the VCE block */
- ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
- AMDGPU_PG_STATE_UNGATE);
+ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+ AMD_PG_STATE_UNGATE);
/* XXX: check for errors */
}
}
return actual_temp;
}
-static int kv_dpm_early_init(struct amdgpu_device *adev)
+static int kv_dpm_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
kv_dpm_set_dpm_funcs(adev);
kv_dpm_set_irq_funcs(adev);
return 0;
}
-static int kv_dpm_late_init(struct amdgpu_device *adev)
+static int kv_dpm_late_init(void *handle)
{
- if (!amdgpu_dpm)
- return 0;
-
/* powerdown unused blocks for now */
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
kv_dpm_powergate_acp(adev, true);
kv_dpm_powergate_samu(adev, true);
kv_dpm_powergate_vce(adev, true);
return 0;
}
-static int kv_dpm_sw_init(struct amdgpu_device *adev)
+static int kv_dpm_sw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
if (ret)
return ret;
}
-static int kv_dpm_sw_fini(struct amdgpu_device *adev)
+static int kv_dpm_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
mutex_lock(&adev->pm.mutex);
amdgpu_pm_sysfs_fini(adev);
kv_dpm_fini(adev);
return 0;
}
-static int kv_dpm_hw_init(struct amdgpu_device *adev)
+static int kv_dpm_hw_init(void *handle)
{
int ret;
-
- if (!amdgpu_dpm)
- return 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
mutex_lock(&adev->pm.mutex);
kv_dpm_setup_asic(adev);
return ret;
}
-static int kv_dpm_hw_fini(struct amdgpu_device *adev)
+static int kv_dpm_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
kv_dpm_disable(adev);
return 0;
}
-static int kv_dpm_suspend(struct amdgpu_device *adev)
+static int kv_dpm_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
/* disable dpm */
return 0;
}
-static int kv_dpm_resume(struct amdgpu_device *adev)
+static int kv_dpm_resume(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->pm.dpm_enabled) {
/* asic init will reset to the boot state */
return 0;
}
-static bool kv_dpm_is_idle(struct amdgpu_device *adev)
+static bool kv_dpm_is_idle(void *handle)
{
- /* XXX */
return true;
}
-static int kv_dpm_wait_for_idle(struct amdgpu_device *adev)
+static int kv_dpm_wait_for_idle(void *handle)
{
- /* XXX */
return 0;
}
-static void kv_dpm_print_status(struct amdgpu_device *adev)
+static void kv_dpm_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "KV/KB DPM registers\n");
dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
RREG32_DIDT(ixDIDT_SQ_CTRL0));
RREG32(mmSMC_IND_ACCESS_CNTL));
}
-static int kv_dpm_soft_reset(struct amdgpu_device *adev)
+static int kv_dpm_soft_reset(void *handle)
{
return 0;
}
return 0;
}
-static int kv_dpm_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int kv_dpm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int kv_dpm_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int kv_dpm_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs kv_dpm_ip_funcs = {
+const struct amd_ip_funcs kv_dpm_ip_funcs = {
.early_init = kv_dpm_early_init,
.late_init = kv_dpm_late_init,
.sw_init = kv_dpm_sw_init,
SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
}
-static int sdma_v2_4_early_init(struct amdgpu_device *adev)
+static int sdma_v2_4_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
sdma_v2_4_set_ring_funcs(adev);
sdma_v2_4_set_buffer_funcs(adev);
sdma_v2_4_set_vm_pte_funcs(adev);
return 0;
}
-static int sdma_v2_4_sw_init(struct amdgpu_device *adev)
+static int sdma_v2_4_sw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* SDMA trap event */
r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
return r;
}
-static int sdma_v2_4_sw_fini(struct amdgpu_device *adev)
+static int sdma_v2_4_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_ring_fini(&adev->sdma[0].ring);
amdgpu_ring_fini(&adev->sdma[1].ring);
return 0;
}
-static int sdma_v2_4_hw_init(struct amdgpu_device *adev)
+static int sdma_v2_4_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
sdma_v2_4_init_golden_registers(adev);
return r;
}
-static int sdma_v2_4_hw_fini(struct amdgpu_device *adev)
+static int sdma_v2_4_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
sdma_v2_4_enable(adev, false);
return 0;
}
-static int sdma_v2_4_suspend(struct amdgpu_device *adev)
+static int sdma_v2_4_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return sdma_v2_4_hw_fini(adev);
}
-static int sdma_v2_4_resume(struct amdgpu_device *adev)
+static int sdma_v2_4_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return sdma_v2_4_hw_init(adev);
}
-static bool sdma_v2_4_is_idle(struct amdgpu_device *adev)
+static bool sdma_v2_4_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
return true;
}
-static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev)
+static int sdma_v2_4_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
return -ETIMEDOUT;
}
-static void sdma_v2_4_print_status(struct amdgpu_device *adev)
+static void sdma_v2_4_print_status(void *handle)
{
int i, j;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "VI SDMA registers\n");
dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
}
}
-static int sdma_v2_4_soft_reset(struct amdgpu_device *adev)
+static int sdma_v2_4_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
}
if (srbm_soft_reset) {
- sdma_v2_4_print_status(adev);
+ sdma_v2_4_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- sdma_v2_4_print_status(adev);
+ sdma_v2_4_print_status((void *)adev);
}
return 0;
return 0;
}
-static int sdma_v2_4_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int sdma_v2_4_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
/* XXX handled via the smc on VI */
-
return 0;
}
-static int sdma_v2_4_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int sdma_v2_4_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs = {
+const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
.early_init = sdma_v2_4_early_init,
.late_init = NULL,
.sw_init = sdma_v2_4_sw_init,
#ifndef __SDMA_V2_4_H__
#define __SDMA_V2_4_H__
-extern const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs;
+extern const struct amd_ip_funcs sdma_v2_4_ip_funcs;
#endif
SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
}
-static int sdma_v3_0_early_init(struct amdgpu_device *adev)
+static int sdma_v3_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
sdma_v3_0_set_ring_funcs(adev);
sdma_v3_0_set_buffer_funcs(adev);
sdma_v3_0_set_vm_pte_funcs(adev);
return 0;
}
-static int sdma_v3_0_sw_init(struct amdgpu_device *adev)
+static int sdma_v3_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* SDMA trap event */
r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
return r;
}
-static int sdma_v3_0_sw_fini(struct amdgpu_device *adev)
+static int sdma_v3_0_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_ring_fini(&adev->sdma[0].ring);
amdgpu_ring_fini(&adev->sdma[1].ring);
return 0;
}
-static int sdma_v3_0_hw_init(struct amdgpu_device *adev)
+static int sdma_v3_0_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
sdma_v3_0_init_golden_registers(adev);
return r;
}
-static int sdma_v3_0_hw_fini(struct amdgpu_device *adev)
+static int sdma_v3_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
sdma_v3_0_enable(adev, false);
return 0;
}
-static int sdma_v3_0_suspend(struct amdgpu_device *adev)
+static int sdma_v3_0_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return sdma_v3_0_hw_fini(adev);
}
-static int sdma_v3_0_resume(struct amdgpu_device *adev)
+static int sdma_v3_0_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return sdma_v3_0_hw_init(adev);
}
-static bool sdma_v3_0_is_idle(struct amdgpu_device *adev)
+static bool sdma_v3_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
return true;
}
-static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev)
+static int sdma_v3_0_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
return -ETIMEDOUT;
}
-static void sdma_v3_0_print_status(struct amdgpu_device *adev)
+static void sdma_v3_0_print_status(void *handle)
{
int i, j;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "VI SDMA registers\n");
dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
}
}
-static int sdma_v3_0_soft_reset(struct amdgpu_device *adev)
+static int sdma_v3_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
}
if (srbm_soft_reset) {
- sdma_v3_0_print_status(adev);
+ sdma_v3_0_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
/* Wait a little for things to settle down */
udelay(50);
- sdma_v3_0_print_status(adev);
+ sdma_v3_0_print_status((void *)adev);
}
return 0;
return 0;
}
-static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int sdma_v3_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- /* XXX handled via the smc on VI */
-
return 0;
}
-static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int sdma_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = {
+const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.early_init = sdma_v3_0_early_init,
.late_init = NULL,
.sw_init = sdma_v3_0_sw_init,
#ifndef __SDMA_V3_0_H__
#define __SDMA_V3_0_H__
-extern const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs;
+extern const struct amd_ip_funcs sdma_v3_0_ip_funcs;
#endif
static void tonga_dpm_set_funcs(struct amdgpu_device *adev);
-static int tonga_dpm_early_init(struct amdgpu_device *adev)
+static int tonga_dpm_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
tonga_dpm_set_funcs(adev);
return 0;
{
char fw_name[30] = "amdgpu/tonga_smc.bin";
int err;
-
err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
if (err)
goto out;
return err;
}
-static int tonga_dpm_sw_init(struct amdgpu_device *adev)
+static int tonga_dpm_sw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
ret = tonga_dpm_init_microcode(adev);
if (ret)
return 0;
}
-static int tonga_dpm_sw_fini(struct amdgpu_device *adev)
+static int tonga_dpm_sw_fini(void *handle)
{
return 0;
}
-static int tonga_dpm_hw_init(struct amdgpu_device *adev)
+static int tonga_dpm_hw_init(void *handle)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
mutex_lock(&adev->pm.mutex);
return -EINVAL;
}
-static int tonga_dpm_hw_fini(struct amdgpu_device *adev)
+static int tonga_dpm_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
mutex_lock(&adev->pm.mutex);
tonga_smu_fini(adev);
mutex_unlock(&adev->pm.mutex);
return 0;
}
-static int tonga_dpm_suspend(struct amdgpu_device *adev)
+static int tonga_dpm_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
tonga_dpm_hw_fini(adev);
return 0;
}
-static int tonga_dpm_resume(struct amdgpu_device *adev)
+static int tonga_dpm_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
tonga_dpm_hw_init(adev);
return 0;
}
-static int tonga_dpm_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int tonga_dpm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int tonga_dpm_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int tonga_dpm_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs tonga_dpm_ip_funcs = {
+const struct amd_ip_funcs tonga_dpm_ip_funcs = {
.early_init = tonga_dpm_early_init,
.late_init = NULL,
.sw_init = tonga_dpm_sw_init,
}
}
-static int tonga_ih_early_init(struct amdgpu_device *adev)
+static int tonga_ih_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
tonga_ih_set_interrupt_funcs(adev);
return 0;
}
-static int tonga_ih_sw_init(struct amdgpu_device *adev)
+static int tonga_ih_sw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_ih_ring_init(adev, 4 * 1024, true);
if (r)
return r;
}
-static int tonga_ih_sw_fini(struct amdgpu_device *adev)
+static int tonga_ih_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
return 0;
}
-static int tonga_ih_hw_init(struct amdgpu_device *adev)
+static int tonga_ih_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = tonga_ih_irq_init(adev);
if (r)
return 0;
}
-static int tonga_ih_hw_fini(struct amdgpu_device *adev)
+static int tonga_ih_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
tonga_ih_irq_disable(adev);
return 0;
}
-static int tonga_ih_suspend(struct amdgpu_device *adev)
+static int tonga_ih_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return tonga_ih_hw_fini(adev);
}
-static int tonga_ih_resume(struct amdgpu_device *adev)
+static int tonga_ih_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return tonga_ih_hw_init(adev);
}
-static bool tonga_ih_is_idle(struct amdgpu_device *adev)
+static bool tonga_ih_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return true;
}
-static int tonga_ih_wait_for_idle(struct amdgpu_device *adev)
+static int tonga_ih_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
return -ETIMEDOUT;
}
-static void tonga_ih_print_status(struct amdgpu_device *adev)
+static void tonga_ih_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "TONGA IH registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmSRBM_STATUS));
RREG32(mmIH_RB_WPTR));
}
-static int tonga_ih_soft_reset(struct amdgpu_device *adev)
+static int tonga_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
return 0;
}
-static int tonga_ih_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int tonga_ih_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- // TODO
return 0;
}
-static int tonga_ih_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int tonga_ih_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
- // TODO
return 0;
}
-const struct amdgpu_ip_funcs tonga_ih_ip_funcs = {
+const struct amd_ip_funcs tonga_ih_ip_funcs = {
.early_init = tonga_ih_early_init,
.late_init = NULL,
.sw_init = tonga_ih_sw_init,
#ifndef __TONGA_IH_H__
#define __TONGA_IH_H__
-extern const struct amdgpu_ip_funcs tonga_ih_ip_funcs;
+extern const struct amd_ip_funcs tonga_ih_ip_funcs;
#endif /* __CZ_IH_H__ */
WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
}
-static int uvd_v4_2_early_init(struct amdgpu_device *adev)
+static int uvd_v4_2_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v4_2_set_ring_funcs(adev);
uvd_v4_2_set_irq_funcs(adev);
return 0;
}
-static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
+static int uvd_v4_2_sw_init(void *handle)
{
struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
/* UVD TRAP */
return r;
}
-static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
+static int uvd_v4_2_sw_fini(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_suspend(adev);
if (r)
*
* Initialize the hardware, boot up the VCPU and do some testing
*/
-static int uvd_v4_2_hw_init(struct amdgpu_device *adev)
+static int uvd_v4_2_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uint32_t tmp;
int r;
*
* Stop the UVD block, mark ring as not ready any more
*/
-static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
+static int uvd_v4_2_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uvd_v4_2_stop(adev);
return 0;
}
-static int uvd_v4_2_suspend(struct amdgpu_device *adev)
+static int uvd_v4_2_suspend(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = uvd_v4_2_hw_fini(adev);
if (r)
return r;
}
-static int uvd_v4_2_resume(struct amdgpu_device *adev)
+static int uvd_v4_2_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_resume(adev);
if (r)
}
}
-static bool uvd_v4_2_is_idle(struct amdgpu_device *adev)
+static bool uvd_v4_2_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
-static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
+static int uvd_v4_2_wait_for_idle(void *handle)
{
unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
return -ETIMEDOUT;
}
-static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
+static int uvd_v4_2_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v4_2_stop(adev);
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
return uvd_v4_2_start(adev);
}
-static void uvd_v4_2_print_status(struct amdgpu_device *adev)
+static void uvd_v4_2_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "UVD 4.2 registers\n");
dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
RREG32(mmUVD_SEMA_ADDR_LOW));
return 0;
}
-static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int uvd_v4_2_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_CG_STATE_GATE)
+ if (state == AMD_CG_STATE_GATE)
gate = true;
uvd_v4_2_enable_mgcg(adev, gate);
return 0;
}
-static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int uvd_v4_2_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
* That's done in the dpm code via the SMC. This
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- if (state == AMDGPU_PG_STATE_GATE) {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE) {
uvd_v4_2_stop(adev);
return 0;
} else {
}
}
-const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = {
+const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
.early_init = uvd_v4_2_early_init,
.late_init = NULL,
.sw_init = uvd_v4_2_sw_init,
#ifndef __UVD_V4_2_H__
#define __UVD_V4_2_H__
-extern const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs;
+extern const struct amd_ip_funcs uvd_v4_2_ip_funcs;
#endif
WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
}
-static int uvd_v5_0_early_init(struct amdgpu_device *adev)
+static int uvd_v5_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v5_0_set_ring_funcs(adev);
uvd_v5_0_set_irq_funcs(adev);
return 0;
}
-static int uvd_v5_0_sw_init(struct amdgpu_device *adev)
+static int uvd_v5_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
/* UVD TRAP */
return r;
}
-static int uvd_v5_0_sw_fini(struct amdgpu_device *adev)
+static int uvd_v5_0_sw_fini(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_suspend(adev);
if (r)
*
* Initialize the hardware, boot up the VCPU and do some testing
*/
-static int uvd_v5_0_hw_init(struct amdgpu_device *adev)
+static int uvd_v5_0_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uint32_t tmp;
int r;
*
* Stop the UVD block, mark ring as not ready any more
*/
-static int uvd_v5_0_hw_fini(struct amdgpu_device *adev)
+static int uvd_v5_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uvd_v5_0_stop(adev);
return 0;
}
-static int uvd_v5_0_suspend(struct amdgpu_device *adev)
+static int uvd_v5_0_suspend(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = uvd_v5_0_hw_fini(adev);
if (r)
return r;
}
-static int uvd_v5_0_resume(struct amdgpu_device *adev)
+static int uvd_v5_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_resume(adev);
if (r)
return r;
}
-static bool uvd_v5_0_is_idle(struct amdgpu_device *adev)
+static bool uvd_v5_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
-static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev)
+static int uvd_v5_0_wait_for_idle(void *handle)
{
unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
return -ETIMEDOUT;
}
-static int uvd_v5_0_soft_reset(struct amdgpu_device *adev)
+static int uvd_v5_0_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v5_0_stop(adev);
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
return uvd_v5_0_start(adev);
}
-static void uvd_v5_0_print_status(struct amdgpu_device *adev)
+static void uvd_v5_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "UVD 5.0 registers\n");
dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
RREG32(mmUVD_SEMA_ADDR_LOW));
return 0;
}
-static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int uvd_v5_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- //TODO
-
return 0;
}
-static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int uvd_v5_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
* That's done in the dpm code via the SMC. This
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- if (state == AMDGPU_PG_STATE_GATE) {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE) {
uvd_v5_0_stop(adev);
return 0;
} else {
}
}
-const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = {
+const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.early_init = uvd_v5_0_early_init,
.late_init = NULL,
.sw_init = uvd_v5_0_sw_init,
#ifndef __UVD_V5_0_H__
#define __UVD_V5_0_H__
-extern const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs;
+extern const struct amd_ip_funcs uvd_v5_0_ip_funcs;
#endif
WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
}
-static int uvd_v6_0_early_init(struct amdgpu_device *adev)
+static int uvd_v6_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v6_0_set_ring_funcs(adev);
uvd_v6_0_set_irq_funcs(adev);
return 0;
}
-static int uvd_v6_0_sw_init(struct amdgpu_device *adev)
+static int uvd_v6_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* UVD TRAP */
r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
return r;
}
-static int uvd_v6_0_sw_fini(struct amdgpu_device *adev)
+static int uvd_v6_0_sw_fini(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_suspend(adev);
if (r)
*
* Initialize the hardware, boot up the VCPU and do some testing
*/
-static int uvd_v6_0_hw_init(struct amdgpu_device *adev)
+static int uvd_v6_0_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uint32_t tmp;
int r;
*
* Stop the UVD block, mark ring as not ready any more
*/
-static int uvd_v6_0_hw_fini(struct amdgpu_device *adev)
+static int uvd_v6_0_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uvd_v6_0_stop(adev);
return 0;
}
-static int uvd_v6_0_suspend(struct amdgpu_device *adev)
+static int uvd_v6_0_suspend(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = uvd_v6_0_hw_fini(adev);
if (r)
return r;
}
-static int uvd_v6_0_resume(struct amdgpu_device *adev)
+static int uvd_v6_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_resume(adev);
if (r)
return r;
}
-static bool uvd_v6_0_is_idle(struct amdgpu_device *adev)
+static bool uvd_v6_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
-static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev)
+static int uvd_v6_0_wait_for_idle(void *handle)
{
unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
return -ETIMEDOUT;
}
-static int uvd_v6_0_soft_reset(struct amdgpu_device *adev)
+static int uvd_v6_0_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
uvd_v6_0_stop(adev);
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
return uvd_v6_0_start(adev);
}
-static void uvd_v6_0_print_status(struct amdgpu_device *adev)
+static void uvd_v6_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
dev_info(adev->dev, "UVD 6.0 registers\n");
dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
RREG32(mmUVD_SEMA_ADDR_LOW));
return 0;
}
-static int uvd_v6_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int uvd_v6_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- //TODO
-
return 0;
}
-static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int uvd_v6_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
* That's done in the dpm code via the SMC. This
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- if (state == AMDGPU_PG_STATE_GATE) {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE) {
uvd_v6_0_stop(adev);
return 0;
} else {
}
}
-const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs = {
+const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.early_init = uvd_v6_0_early_init,
.late_init = NULL,
.sw_init = uvd_v6_0_sw_init,
#ifndef __UVD_V6_0_H__
#define __UVD_V6_0_H__
-extern const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs;
+extern const struct amd_ip_funcs uvd_v6_0_ip_funcs;
#endif
return 0;
}
-static int vce_v2_0_early_init(struct amdgpu_device *adev)
+static int vce_v2_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
vce_v2_0_set_ring_funcs(adev);
vce_v2_0_set_irq_funcs(adev);
return 0;
}
-static int vce_v2_0_sw_init(struct amdgpu_device *adev)
+static int vce_v2_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* VCE */
r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
return r;
}
-static int vce_v2_0_sw_fini(struct amdgpu_device *adev)
+static int vce_v2_0_sw_fini(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_suspend(adev);
if (r)
return r;
}
-static int vce_v2_0_hw_init(struct amdgpu_device *adev)
+static int vce_v2_0_hw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v2_0_start(adev);
if (r)
return 0;
}
-static int vce_v2_0_hw_fini(struct amdgpu_device *adev)
+static int vce_v2_0_hw_fini(void *handle)
{
- // TODO
return 0;
}
-static int vce_v2_0_suspend(struct amdgpu_device *adev)
+static int vce_v2_0_suspend(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v2_0_hw_fini(adev);
if (r)
return r;
}
-static int vce_v2_0_resume(struct amdgpu_device *adev)
+static int vce_v2_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_resume(adev);
if (r)
vce_v2_0_init_cg(adev);
}
-static bool vce_v2_0_is_idle(struct amdgpu_device *adev)
+static bool vce_v2_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}
-static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev)
+static int vce_v2_0_wait_for_idle(void *handle)
{
unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
return -ETIMEDOUT;
}
-static int vce_v2_0_soft_reset(struct amdgpu_device *adev)
+static int vce_v2_0_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
mdelay(5);
return vce_v2_0_start(adev);
}
-static void vce_v2_0_print_status(struct amdgpu_device *adev)
+static void vce_v2_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "VCE 2.0 registers\n");
dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
RREG32(mmVCE_STATUS));
return 0;
}
-static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int vce_v2_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
bool gate = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == AMDGPU_CG_STATE_GATE)
+ if (state == AMD_CG_STATE_GATE)
gate = true;
vce_v2_0_enable_mgcg(adev, gate);
return 0;
}
-static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int vce_v2_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
* That's done in the dpm code via the SMC. This
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- if (state == AMDGPU_PG_STATE_GATE)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE)
/* XXX do we need a vce_v2_0_stop()? */
return 0;
else
return vce_v2_0_start(adev);
}
-const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = {
+const struct amd_ip_funcs vce_v2_0_ip_funcs = {
.early_init = vce_v2_0_early_init,
.late_init = NULL,
.sw_init = vce_v2_0_sw_init,
#ifndef __VCE_V2_0_H__
#define __VCE_V2_0_H__
-extern const struct amdgpu_ip_funcs vce_v2_0_ip_funcs;
+extern const struct amd_ip_funcs vce_v2_0_ip_funcs;
#endif
return 0;
}
-static int vce_v3_0_early_init(struct amdgpu_device *adev)
+static int vce_v3_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
vce_v3_0_set_ring_funcs(adev);
vce_v3_0_set_irq_funcs(adev);
return 0;
}
-static int vce_v3_0_sw_init(struct amdgpu_device *adev)
+static int vce_v3_0_sw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring;
int r;
return r;
}
-static int vce_v3_0_sw_fini(struct amdgpu_device *adev)
+static int vce_v3_0_sw_fini(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_suspend(adev);
if (r)
return r;
}
-static int vce_v3_0_hw_init(struct amdgpu_device *adev)
+static int vce_v3_0_hw_init(void *handle)
{
struct amdgpu_ring *ring;
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v3_0_start(adev);
if (r)
return 0;
}
-static int vce_v3_0_hw_fini(struct amdgpu_device *adev)
+static int vce_v3_0_hw_fini(void *handle)
{
- // TODO
return 0;
}
-static int vce_v3_0_suspend(struct amdgpu_device *adev)
+static int vce_v3_0_suspend(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = vce_v3_0_hw_fini(adev);
if (r)
return r;
}
-static int vce_v3_0_resume(struct amdgpu_device *adev)
+static int vce_v3_0_resume(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_vce_resume(adev);
if (r)
~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
}
-static bool vce_v3_0_is_idle(struct amdgpu_device *adev)
+static bool vce_v3_0_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}
-static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev)
+static int vce_v3_0_wait_for_idle(void *handle)
{
unsigned i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
return -ETIMEDOUT;
}
-static int vce_v3_0_soft_reset(struct amdgpu_device *adev)
+static int vce_v3_0_soft_reset(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
mdelay(5);
return vce_v3_0_start(adev);
}
-static void vce_v3_0_print_status(struct amdgpu_device *adev)
+static void vce_v3_0_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "VCE 3.0 registers\n");
dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
RREG32(mmVCE_STATUS));
return 0;
}
-static int vce_v3_0_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int vce_v3_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
- //TODO
return 0;
}
-static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int vce_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
* That's done in the dpm code via the SMC. This
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- if (state == AMDGPU_PG_STATE_GATE)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (state == AMD_PG_STATE_GATE)
/* XXX do we need a vce_v3_0_stop()? */
return 0;
else
return vce_v3_0_start(adev);
}
-const struct amdgpu_ip_funcs vce_v3_0_ip_funcs = {
+const struct amd_ip_funcs vce_v3_0_ip_funcs = {
.early_init = vce_v3_0_early_init,
.late_init = NULL,
.sw_init = vce_v3_0_sw_init,
#ifndef __VCE_V3_0_H__
#define __VCE_V3_0_H__
-extern const struct amdgpu_ip_funcs vce_v3_0_ip_funcs;
+extern const struct amd_ip_funcs vce_v3_0_ip_funcs;
#endif
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &vi_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gmc_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 2,
.minor = 4,
.rev = 0,
.funcs = &iceland_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 1,
.rev = 0,
.funcs = &iceland_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gfx_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 2,
.minor = 4,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &vi_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gmc_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &tonga_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 7,
.minor = 1,
.rev = 0,
.funcs = &tonga_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 10,
.minor = 0,
.rev = 0,
.funcs = &dce_v10_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gfx_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &sdma_v3_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 5,
.minor = 0,
.rev = 0,
.funcs = &uvd_v5_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 3,
.minor = 0,
.rev = 0,
{
/* ORDER MATTERS! */
{
- .type = AMDGPU_IP_BLOCK_TYPE_COMMON,
+ .type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 2,
.minor = 0,
.rev = 0,
.funcs = &vi_common_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GMC,
+ .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gmc_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_IH,
+ .type = AMD_IP_BLOCK_TYPE_IH,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &cz_ih_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SMC,
+ .type = AMD_IP_BLOCK_TYPE_SMC,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &cz_dpm_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_DCE,
+ .type = AMD_IP_BLOCK_TYPE_DCE,
.major = 11,
.minor = 0,
.rev = 0,
.funcs = &dce_v11_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_GFX,
+ .type = AMD_IP_BLOCK_TYPE_GFX,
.major = 8,
.minor = 0,
.rev = 0,
.funcs = &gfx_v8_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_SDMA,
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 3,
.minor = 0,
.rev = 0,
.funcs = &sdma_v3_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_UVD,
+ .type = AMD_IP_BLOCK_TYPE_UVD,
.major = 6,
.minor = 0,
.rev = 0,
.funcs = &uvd_v6_0_ip_funcs,
},
{
- .type = AMDGPU_IP_BLOCK_TYPE_VCE,
+ .type = AMD_IP_BLOCK_TYPE_VCE,
.major = 3,
.minor = 0,
.rev = 0,
.wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
};
-static int vi_common_early_init(struct amdgpu_device *adev)
+static int vi_common_early_init(void *handle)
{
bool smc_enabled = false;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->smc_rreg = &vi_smc_rreg;
adev->smc_wreg = &vi_smc_wreg;
adev->asic_funcs = &vi_asic_funcs;
- if (amdgpu_get_ip_block(adev, AMDGPU_IP_BLOCK_TYPE_SMC) &&
- (amdgpu_ip_block_mask & (1 << AMDGPU_IP_BLOCK_TYPE_SMC)))
+ if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
+ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
smc_enabled = true;
adev->rev_id = vi_get_rev_id(adev);
return 0;
}
-static int vi_common_sw_init(struct amdgpu_device *adev)
+static int vi_common_sw_init(void *handle)
{
return 0;
}
-static int vi_common_sw_fini(struct amdgpu_device *adev)
+static int vi_common_sw_fini(void *handle)
{
return 0;
}
-static int vi_common_hw_init(struct amdgpu_device *adev)
+static int vi_common_hw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
/* move the golden regs per IP block */
vi_init_golden_registers(adev);
/* enable pcie gen2/3 link */
return 0;
}
-static int vi_common_hw_fini(struct amdgpu_device *adev)
+static int vi_common_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
/* enable the doorbell aperture */
vi_enable_doorbell_aperture(adev, false);
return 0;
}
-static int vi_common_suspend(struct amdgpu_device *adev)
+static int vi_common_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return vi_common_hw_fini(adev);
}
-static int vi_common_resume(struct amdgpu_device *adev)
+static int vi_common_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return vi_common_hw_init(adev);
}
-static bool vi_common_is_idle(struct amdgpu_device *adev)
+static bool vi_common_is_idle(void *handle)
{
return true;
}
-static int vi_common_wait_for_idle(struct amdgpu_device *adev)
+static int vi_common_wait_for_idle(void *handle)
{
return 0;
}
-static void vi_common_print_status(struct amdgpu_device *adev)
+static void vi_common_print_status(void *handle)
{
-
+ return;
}
-static int vi_common_soft_reset(struct amdgpu_device *adev)
+static int vi_common_soft_reset(void *handle)
{
- /* XXX hard reset?? */
return 0;
}
-static int vi_common_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int vi_common_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
return 0;
}
-static int vi_common_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int vi_common_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
return 0;
}
-const struct amdgpu_ip_funcs vi_common_ip_funcs = {
+const struct amd_ip_funcs vi_common_ip_funcs = {
.early_init = vi_common_early_init,
.late_init = NULL,
.sw_init = vi_common_sw_init,
#ifndef __VI_H__
#define __VI_H__
-extern const struct amdgpu_ip_funcs vi_common_ip_funcs;
+extern const struct amd_ip_funcs vi_common_ip_funcs;
void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
#ifndef __VI_DPM_H__
#define __VI_DPM_H__
-extern const struct amdgpu_ip_funcs cz_dpm_ip_funcs;
+extern const struct amd_ip_funcs cz_dpm_ip_funcs;
int cz_smu_init(struct amdgpu_device *adev);
int cz_smu_start(struct amdgpu_device *adev);
int cz_smu_fini(struct amdgpu_device *adev);
-extern const struct amdgpu_ip_funcs tonga_dpm_ip_funcs;
+extern const struct amd_ip_funcs tonga_dpm_ip_funcs;
-extern const struct amdgpu_ip_funcs iceland_dpm_ip_funcs;
+extern const struct amd_ip_funcs iceland_dpm_ip_funcs;
#endif
--- /dev/null
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_SHARED_H__
+#define __AMD_SHARED_H__
+
+enum amd_ip_block_type {
+ AMD_IP_BLOCK_TYPE_COMMON,
+ AMD_IP_BLOCK_TYPE_GMC,
+ AMD_IP_BLOCK_TYPE_IH,
+ AMD_IP_BLOCK_TYPE_SMC,
+ AMD_IP_BLOCK_TYPE_DCE,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_IP_BLOCK_TYPE_SDMA,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_IP_BLOCK_TYPE_VCE,
+};
+
+enum amd_clockgating_state {
+ AMD_CG_STATE_GATE = 0,
+ AMD_CG_STATE_UNGATE,
+};
+
+enum amd_powergating_state {
+ AMD_PG_STATE_GATE = 0,
+ AMD_PG_STATE_UNGATE,
+};
+
+struct amd_ip_funcs {
+ /* sets up early driver state (pre sw_init), does not configure hw - Optional */
+ int (*early_init)(void *handle);
+ /* sets up late driver/hw state (post hw_init) - Optional */
+ int (*late_init)(void *handle);
+ /* sets up driver state, does not configure hw */
+ int (*sw_init)(void *handle);
+ /* tears down driver state, does not configure hw */
+ int (*sw_fini)(void *handle);
+ /* sets up the hw state */
+ int (*hw_init)(void *handle);
+ /* tears down the hw state */
+ int (*hw_fini)(void *handle);
+ /* handles IP specific hw/sw changes for suspend */
+ int (*suspend)(void *handle);
+ /* handles IP specific hw/sw changes for resume */
+ int (*resume)(void *handle);
+ /* returns current IP block idle status */
+ bool (*is_idle)(void *handle);
+ /* poll for idle */
+ int (*wait_for_idle)(void *handle);
+ /* soft reset the IP block */
+ int (*soft_reset)(void *handle);
+ /* dump the IP block status registers */
+ void (*print_status)(void *handle);
+ /* enable/disable cg for the IP block */
+ int (*set_clockgating_state)(void *handle,
+ enum amd_clockgating_state state);
+ /* enable/disable pg for the IP block */
+ int (*set_powergating_state)(void *handle,
+ enum amd_powergating_state state);
+};
+
+#endif /* __AMD_SHARED_H__ */
projects / GitHub / LineageOS / G12 / android_kernel_amlogic_linux-4.9.git / commitdiff