ARM: dts: vfxxx: Include support for dspi[23] functionality.

Extend the existing Vybrid DSPI devicetree implementation to also
describe the dspi2 and dspi3 functional blocks.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 3cd1b27f269780b99d1dbc4af64644bcaa45cce5..a9ceb5bac40ef244dc6ca18602eef4072b87a57d 100644 (file)
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -455,6 +455,30 @@
                                status = "disabled";
                        };
 
+                       dspi2: dspi2@400ac000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,vf610-dspi";
+                               reg = <0x400ac000 0x1000>;
+                               interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks VF610_CLK_DSPI2>;
+                               clock-names = "dspi";
+                               spi-num-chipselects = <2>;
+                               status = "disabled";
+                       };
+
+                       dspi3: dspi3@400ad000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,vf610-dspi";
+                               reg = <0x400ad000 0x1000>;
+                               interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks VF610_CLK_DSPI3>;
+                               clock-names = "dspi";
+                               spi-num-chipselects = <2>;
+                               status = "disabled";
+                       };
+
                        adc1: adc@400bb000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x400bb000 0x1000>;