drm/i915: Nuke crtc->wm.cxsr_allowed

Remove crtc->wm.cxsr_allowed and just rely on crtc_state->disable_cxsr
instead. This was used only by vlv/chv to indicate whether to enable
cxsr in the wm computation. That doesn't really work anymore, and as far
as the optimal watermarks go we'll just consider the number of planes
and the current pipe, and for the intermediate watermarks we'll also
start to consider disable_cxsr which is set appropriately when planes
are being enabled/disabled.

We'll also flip over the crtc_state->wm.need_postvbl_update setup so
that it's the wm code that will set it. Previously the generic code set
it up, and then the wm code cleared it again if it thought it's not
needed after all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302171508.1666-11-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 45a7c7e18e3d0796d35df76dfb43f67ed07e9585..83f30560217d6683a91c3e158c9d86607c8f5aa4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4997,8 +4997,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 
        intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
 
-       crtc->wm.cxsr_allowed = true;
-
        if (pipe_config->update_wm_post && pipe_config->base.active)
                intel_update_watermarks(crtc);
 
@@ -5045,22 +5043,18 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
                        intel_pre_disable_primary(&crtc->base);
        }
 
-       if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
-               crtc->wm.cxsr_allowed = false;
-
-               /*
-                * Vblank time updates from the shadow to live plane control register
-                * are blocked if the memory self-refresh mode is active at that
-                * moment. So to make sure the plane gets truly disabled, disable
-                * first the self-refresh mode. The self-refresh enable bit in turn
-                * will be checked/applied by the HW only at the next frame start
-                * event which is after the vblank start event, so we need to have a
-                * wait-for-vblank between disabling the plane and the pipe.
-                */
-               if (old_crtc_state->base.active &&
-                   intel_set_memory_cxsr(dev_priv, false))
-                       intel_wait_for_vblank(dev_priv, crtc->pipe);
-       }
+       /*
+        * Vblank time updates from the shadow to live plane control register
+        * are blocked if the memory self-refresh mode is active at that
+        * moment. So to make sure the plane gets truly disabled, disable
+        * first the self-refresh mode. The self-refresh enable bit in turn
+        * will be checked/applied by the HW only at the next frame start
+        * event which is after the vblank start event, so we need to have a
+        * wait-for-vblank between disabling the plane and the pipe.
+        */
+       if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
+           pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
+               intel_wait_for_vblank(dev_priv, crtc->pipe);
 
        /*
         * IVB workaround: must disable low power watermarks for at least
@@ -10868,11 +10862,6 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
                pipe_config->update_wm_post = true;
        }
 
-       /* Pre-gen9 platforms need two-step watermark updates */
-       if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
-           INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
-               to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
-
        if (visible || was_visible)
                pipe_config->fb_bits |= plane->frontbuffer_bit;
 
@@ -12616,12 +12605,7 @@ static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
        if (crtc_state->update_wm_post)
                return true;
 
-       /*
-        * cxsr is re-enabled after vblank.
-        * This is already handled by crtc_state->update_wm_post,
-        * but added for clarity.
-        */
-       if (crtc_state->disable_cxsr)
+       if (crtc_state->wm.need_postvbl_update)
                return true;
 
        return false;
@@ -13890,8 +13874,6 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
        intel_crtc->cursor_cntl = ~0;
        intel_crtc->cursor_size = ~0;
 
-       intel_crtc->wm.cxsr_allowed = true;
-
        /* initialize shared scalers */
        intel_crtc_init_scalers(intel_crtc, crtc_state);
 

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9bab6124cde81762e77b24543cd712c78a6399c3..f503313f6e6528b61f4fce90240dbaa62389d8b8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -777,9 +777,6 @@ struct intel_crtc {
                        struct intel_pipe_wm ilk;
                        struct vlv_wm_state vlv;
                } active;
-
-               /* allow CxSR on this pipe */
-               bool cxsr_allowed;
        } wm;
 
        int scanline_offset;

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 824d5b0806b920eb76e96255e1289f9df670be4b..af7fb532d806e34061986b766c213a794e0385e6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1274,8 +1274,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
         * enabled can wedge the pipe. Hence we only allow cxsr
         * with exactly one enabled primary/sprite plane.
         */
-       wm_state->cxsr = crtc->pipe != PIPE_C &&
-               crtc->wm.cxsr_allowed && num_active_planes == 1;
+       wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
 
        for (level = 0; level < wm_state->num_levels; level++) {
                const struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
@@ -1411,7 +1410,8 @@ static int vlv_compute_intermediate_wm(struct drm_device *dev,
        int level;
 
        intermediate->num_levels = min(optimal->num_levels, active->num_levels);
-       intermediate->cxsr = optimal->cxsr & active->cxsr;
+       intermediate->cxsr = optimal->cxsr && active->cxsr &&
+               !crtc_state->disable_cxsr;
 
        for (level = 0; level < intermediate->num_levels; level++) {
                enum plane_id plane_id;
@@ -1434,8 +1434,8 @@ static int vlv_compute_intermediate_wm(struct drm_device *dev,
         * If our intermediate WM are identical to the final WM, then we can
         * omit the post-vblank programming; only update if it's different.
         */
-       if (memcmp(intermediate, optimal, sizeof(*intermediate)) == 0)
-               crtc_state->wm.need_postvbl_update = false;
+       if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
+               crtc_state->wm.need_postvbl_update = true;
 
        return 0;
 }
@@ -2628,8 +2628,8 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
         * If our intermediate WM are identical to the final WM, then we can
         * omit the post-vblank programming; only update if it's different.
         */
-       if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
-               newstate->wm.need_postvbl_update = false;
+       if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
+               newstate->wm.need_postvbl_update = true;
 
        return 0;
 }