drm/nouveau/gr/gf100-: rename magic_not_rop_nr to screen_tile_row_offset
authorBen Skeggs <bskeggs@redhat.com>
Thu, 14 Apr 2016 04:08:25 +0000 (14:08 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 20 May 2016 04:43:04 +0000 (14:43 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

index a54b5537677ebeb9870a11596eabc6ed7821bd04..b02d8f50ea6aff4549a27b3e3917da5b4731b883 100644 (file)
@@ -1181,20 +1181,20 @@ gf100_grctx_generate_r418bb8(struct gf100_gr *gr)
 
        /* GPC_BROADCAST */
        nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr);
+                                    gr->screen_tile_row_offset);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
 
        /* GPC_BROADCAST.TP_BROADCAST */
        nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr | data2[0]);
+                                    gr->screen_tile_row_offset | data2[0]);
        nvkm_wr32(device, 0x419be4, data2[1]);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x419b00 + (i * 4), data[i]);
 
        /* UNK78xx */
        nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr);
+                                    gr->screen_tile_row_offset);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
 }
index 2be27179a2613819ffd28e2138cac5ad94ab4f9f..0c99f3c3a376bb8fb0682fd4b404228fc32d7656 100644 (file)
@@ -924,20 +924,20 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
 
        /* GPC_BROADCAST */
        nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr);
+                                    gr->screen_tile_row_offset);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
 
        /* GPC_BROADCAST.TP_BROADCAST */
        nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr | data2[0]);
+                                    gr->screen_tile_row_offset | data2[0]);
        nvkm_wr32(device, 0x41bfe4, data2[1]);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]);
 
        /* UNK78xx */
        nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
-                                gr->magic_not_rop_nr);
+                                    gr->screen_tile_row_offset);
        for (i = 0; i < 6; i++)
                nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
 }
index 8206aecefc7dccf41b1e5db43a8e0098b09871a2..086f56529d6dc8291fe8740d7bb0c7d5b49578ce 100644 (file)
@@ -1651,38 +1651,38 @@ gf100_gr_oneinit(struct nvkm_gr *base)
        switch (device->chipset) {
        case 0xc0:
                if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
-                       gr->magic_not_rop_nr = 0x07;
+                       gr->screen_tile_row_offset = 0x07;
                } else
                if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
-                       gr->magic_not_rop_nr = 0x05;
+                       gr->screen_tile_row_offset = 0x05;
                } else
                if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
-                       gr->magic_not_rop_nr = 0x06;
+                       gr->screen_tile_row_offset = 0x06;
                }
                break;
        case 0xc3: /* 450, 4/0/0/0, 2 */
-               gr->magic_not_rop_nr = 0x03;
+               gr->screen_tile_row_offset = 0x03;
                break;
        case 0xc4: /* 460, 3/4/0/0, 4 */
-               gr->magic_not_rop_nr = 0x01;
+               gr->screen_tile_row_offset = 0x01;
                break;
        case 0xc1: /* 2/0/0/0, 1 */
-               gr->magic_not_rop_nr = 0x01;
+               gr->screen_tile_row_offset = 0x01;
                break;
        case 0xc8: /* 4/4/3/4, 5 */
-               gr->magic_not_rop_nr = 0x06;
+               gr->screen_tile_row_offset = 0x06;
                break;
        case 0xce: /* 4/4/0/0, 4 */
-               gr->magic_not_rop_nr = 0x03;
+               gr->screen_tile_row_offset = 0x03;
                break;
        case 0xcf: /* 4/0/0/0, 3 */
-               gr->magic_not_rop_nr = 0x03;
+               gr->screen_tile_row_offset = 0x03;
                break;
        case 0xd7:
        case 0xd9: /* 1/0/0/0, 1 */
        case 0xea: /* gk20a */
        case 0x12b: /* gm20b */
-               gr->magic_not_rop_nr = 0x01;
+               gr->screen_tile_row_offset = 0x01;
                break;
        }
 
@@ -1851,9 +1851,9 @@ gf100_gr_init(struct gf100_gr *gr)
 
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
-                       gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+                         gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-                       gr->tpc_total);
+                                                        gr->tpc_total);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
        }
 
index f0c6acb0f8fd56f32903bf627562fc08b6e87625..0c49193740f05ee1ce46e1ce86e971b6d4774e65 100644 (file)
@@ -108,7 +108,7 @@ struct gf100_gr {
        u32  size;
        u32 *data;
 
-       u8 magic_not_rop_nr;
+       u8 screen_tile_row_offset;
 };
 
 int gf100_gr_ctor(const struct gf100_gr_func *, struct nvkm_device *,
index abf54928a1a44afefac30138392f6743cc21a583..1be324ac26581a2850f9b9697bb990c354cc2fa7 100644 (file)
@@ -218,9 +218,9 @@ gk104_gr_init(struct gf100_gr *gr)
 
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
-                       gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+                         gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-                       gr->tpc_total);
+                                                        gr->tpc_total);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
        }
 
index 7ffb8a626196c82975bbf423e74ac6a9abf0c18f..8a43baf2d9ab9f233d388a354dd9ea1186e428b9 100644 (file)
@@ -267,7 +267,7 @@ gk20a_gr_init(struct gf100_gr *gr)
 
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
-                         gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+                         gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
                          gr->tpc_total);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
index 56e960212e5df280cd6c6a7b1e13cb6f0473852a..b410221628de1524497cdd8e38711fd9c7cc2629 100644 (file)
@@ -347,9 +347,9 @@ gm107_gr_init(struct gf100_gr *gr)
 
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
-                       gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+                         gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-                       gr->tpc_total);
+                                                        gr->tpc_total);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
        }
 
index 058fc1d22c0992126ad15b5eb96f440e0bc6ce83..ccc644605643720101184975e872f9413f940d61 100644 (file)
@@ -79,9 +79,9 @@ gm200_gr_init(struct gf100_gr *gr)
 
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
-                       gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+                         gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
-                       gr->tpc_total);
+                                                        gr->tpc_total);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
        }