drm/i915: reindent Haswell register definitions
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 8 Aug 2012 17:15:31 +0000 (14:15 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 9 Aug 2012 16:41:47 +0000 (18:41 +0200)
It's the only part of the i915_reg.h file that looks totally wrongly
indented, so I assume my editor config is the correct one.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h

index f3fafb8653655383f78ccf78d23d7058790ad137..af41d03bff822a51c88b5c450c4704fe74cc9532 100644 (file)
 #define   AUD_CONFIG_DISABLE_NCTS              (1 << 3)
 
 /* HSW Power Wells */
-#define HSW_PWR_WELL_CTL1              0x45400         /* BIOS */
-#define HSW_PWR_WELL_CTL2              0x45404         /* Driver */
-#define HSW_PWR_WELL_CTL3              0x45408         /* KVMR */
-#define HSW_PWR_WELL_CTL4              0x4540C         /* Debug */
-#define   HSW_PWR_WELL_ENABLE                          (1<<31)
-#define   HSW_PWR_WELL_STATE                           (1<<30)
-#define HSW_PWR_WELL_CTL5              0x45410
+#define HSW_PWR_WELL_CTL1                      0x45400 /* BIOS */
+#define HSW_PWR_WELL_CTL2                      0x45404 /* Driver */
+#define HSW_PWR_WELL_CTL3                      0x45408 /* KVMR */
+#define HSW_PWR_WELL_CTL4                      0x4540C /* Debug */
+#define   HSW_PWR_WELL_ENABLE                  (1<<31)
+#define   HSW_PWR_WELL_STATE                   (1<<30)
+#define HSW_PWR_WELL_CTL5                      0x45410
 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP      (1<<31)
 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE       (1<<20)
-#define   HSW_PWR_WELL_FORCE_ON                                (1<<19)
-#define HSW_PWR_WELL_CTL6              0x45414
+#define   HSW_PWR_WELL_FORCE_ON                        (1<<19)
+#define HSW_PWR_WELL_CTL6                      0x45414
 
 /* Per-pipe DDI Function Control */
-#define PIPE_DDI_FUNC_CTL_A                    0x60400
-#define PIPE_DDI_FUNC_CTL_B                    0x61400
-#define PIPE_DDI_FUNC_CTL_C                    0x62400
+#define PIPE_DDI_FUNC_CTL_A            0x60400
+#define PIPE_DDI_FUNC_CTL_B            0x61400
+#define PIPE_DDI_FUNC_CTL_C            0x62400
 #define PIPE_DDI_FUNC_CTL_EDP          0x6F400
-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
-                                       PIPE_DDI_FUNC_CTL_A, \
-                                       PIPE_DDI_FUNC_CTL_B)
+#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
+                                      PIPE_DDI_FUNC_CTL_B)
 #define  PIPE_DDI_FUNC_ENABLE          (1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define  PIPE_DDI_PORT_MASK                    (7<<28)
-#define  PIPE_DDI_SELECT_PORT(x)               ((x)<<28)
-#define  PIPE_DDI_MODE_SELECT_MASK             (7<<24)
-#define  PIPE_DDI_MODE_SELECT_HDMI             (0<<24)
-#define  PIPE_DDI_MODE_SELECT_DVI              (1<<24)
+#define  PIPE_DDI_PORT_MASK            (7<<28)
+#define  PIPE_DDI_SELECT_PORT(x)       ((x)<<28)
+#define  PIPE_DDI_MODE_SELECT_MASK     (7<<24)
+#define  PIPE_DDI_MODE_SELECT_HDMI     (0<<24)
+#define  PIPE_DDI_MODE_SELECT_DVI      (1<<24)
 #define  PIPE_DDI_MODE_SELECT_DP_SST   (2<<24)
 #define  PIPE_DDI_MODE_SELECT_DP_MST   (3<<24)
-#define  PIPE_DDI_MODE_SELECT_FDI              (4<<24)
-#define  PIPE_DDI_BPC_MASK                     (7<<20)
-#define  PIPE_DDI_BPC_8                                        (0<<20)
-#define  PIPE_DDI_BPC_10                               (1<<20)
-#define  PIPE_DDI_BPC_6                                        (2<<20)
-#define  PIPE_DDI_BPC_12                               (3<<20)
-#define  PIPE_DDI_PVSYNC                       (1<<17)
-#define  PIPE_DDI_PHSYNC                       (1<<16)
-#define  PIPE_DDI_BFI_ENABLE                   (1<<4)
-#define  PIPE_DDI_PORT_WIDTH_X1                        (0<<1)
-#define  PIPE_DDI_PORT_WIDTH_X2                        (1<<1)
-#define  PIPE_DDI_PORT_WIDTH_X4                        (3<<1)
+#define  PIPE_DDI_MODE_SELECT_FDI      (4<<24)
+#define  PIPE_DDI_BPC_MASK             (7<<20)
+#define  PIPE_DDI_BPC_8                        (0<<20)
+#define  PIPE_DDI_BPC_10               (1<<20)
+#define  PIPE_DDI_BPC_6                        (2<<20)
+#define  PIPE_DDI_BPC_12               (3<<20)
+#define  PIPE_DDI_PVSYNC               (1<<17)
+#define  PIPE_DDI_PHSYNC               (1<<16)
+#define  PIPE_DDI_BFI_ENABLE           (1<<4)
+#define  PIPE_DDI_PORT_WIDTH_X1                (0<<1)
+#define  PIPE_DDI_PORT_WIDTH_X2                (1<<1)
+#define  PIPE_DDI_PORT_WIDTH_X4                (3<<1)
 
 /* DisplayPort Transport Control */
 #define DP_TP_CTL_A                    0x64040
 #define DP_TP_CTL_B                    0x64140
-#define DP_TP_CTL(port) _PORT(port, \
-                                       DP_TP_CTL_A, \
-                                       DP_TP_CTL_B)
-#define  DP_TP_CTL_ENABLE              (1<<31)
-#define  DP_TP_CTL_MODE_SST    (0<<27)
-#define  DP_TP_CTL_MODE_MST    (1<<27)
+#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
+#define  DP_TP_CTL_ENABLE                      (1<<31)
+#define  DP_TP_CTL_MODE_SST                    (0<<27)
+#define  DP_TP_CTL_MODE_MST                    (1<<27)
 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE       (1<<18)
-#define  DP_TP_CTL_FDI_AUTOTRAIN       (1<<15)
+#define  DP_TP_CTL_FDI_AUTOTRAIN               (1<<15)
 #define  DP_TP_CTL_LINK_TRAIN_MASK             (7<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT1             (0<<8)
 #define  DP_TP_CTL_LINK_TRAIN_PAT2             (1<<8)
-#define  DP_TP_CTL_LINK_TRAIN_NORMAL   (3<<8)
+#define  DP_TP_CTL_LINK_TRAIN_NORMAL           (3<<8)
 
 /* DisplayPort Transport Status */
 #define DP_TP_STATUS_A                 0x64044
 #define DP_TP_STATUS_B                 0x64144
-#define DP_TP_STATUS(port) _PORT(port, \
-                                       DP_TP_STATUS_A, \
-                                       DP_TP_STATUS_B)
+#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
 #define  DP_TP_STATUS_AUTOTRAIN_DONE   (1<<12)
 
 /* DDI Buffer Control */
 #define DDI_BUF_CTL_A                          0x64000
 #define DDI_BUF_CTL_B                          0x64100
-#define DDI_BUF_CTL(port) _PORT(port, \
-                                       DDI_BUF_CTL_A, \
-                                       DDI_BUF_CTL_B)
-#define  DDI_BUF_CTL_ENABLE                            (1<<31)
+#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
+#define  DDI_BUF_CTL_ENABLE                    (1<<31)
 #define  DDI_BUF_EMP_400MV_0DB_HSW             (0<<24)   /* Sel0 */
-#define  DDI_BUF_EMP_400MV_3_5DB_HSW   (1<<24)   /* Sel1 */
+#define  DDI_BUF_EMP_400MV_3_5DB_HSW           (1<<24)   /* Sel1 */
 #define  DDI_BUF_EMP_400MV_6DB_HSW             (2<<24)   /* Sel2 */
-#define  DDI_BUF_EMP_400MV_9_5DB_HSW   (3<<24)   /* Sel3 */
+#define  DDI_BUF_EMP_400MV_9_5DB_HSW           (3<<24)   /* Sel3 */
 #define  DDI_BUF_EMP_600MV_0DB_HSW             (4<<24)   /* Sel4 */
-#define  DDI_BUF_EMP_600MV_3_5DB_HSW   (5<<24)   /* Sel5 */
+#define  DDI_BUF_EMP_600MV_3_5DB_HSW           (5<<24)   /* Sel5 */
 #define  DDI_BUF_EMP_600MV_6DB_HSW             (6<<24)   /* Sel6 */
 #define  DDI_BUF_EMP_800MV_0DB_HSW             (7<<24)   /* Sel7 */
-#define  DDI_BUF_EMP_800MV_3_5DB_HSW   (8<<24)   /* Sel8 */
-#define  DDI_BUF_EMP_MASK                              (0xf<<24)
-#define  DDI_BUF_IS_IDLE                               (1<<7)
-#define  DDI_PORT_WIDTH_X1                             (0<<1)
-#define  DDI_PORT_WIDTH_X2                             (1<<1)
-#define  DDI_PORT_WIDTH_X4                             (3<<1)
+#define  DDI_BUF_EMP_800MV_3_5DB_HSW           (8<<24)   /* Sel8 */
+#define  DDI_BUF_EMP_MASK                      (0xf<<24)
+#define  DDI_BUF_IS_IDLE                       (1<<7)
+#define  DDI_PORT_WIDTH_X1                     (0<<1)
+#define  DDI_PORT_WIDTH_X2                     (1<<1)
+#define  DDI_PORT_WIDTH_X4                     (3<<1)
 #define  DDI_INIT_DISPLAY_DETECTED             (1<<0)
 
 /* DDI Buffer Translations */
 #define DDI_BUF_TRANS_A                                0x64E00
 #define DDI_BUF_TRANS_B                                0x64E60
-#define DDI_BUF_TRANS(port) _PORT(port, \
-                                       DDI_BUF_TRANS_A, \
-                                       DDI_BUF_TRANS_B)
+#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
 
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  * which contains the payload */
-#define SBI_ADDR                               0xC6000
-#define SBI_DATA                               0xC6004
+#define SBI_ADDR                       0xC6000
+#define SBI_DATA                       0xC6004
 #define SBI_CTL_STAT                   0xC6008
 #define  SBI_CTL_OP_CRRD               (0x6<<8)
 #define  SBI_CTL_OP_CRWR               (0x7<<8)
 #define  SBI_RESPONSE_FAIL             (0x1<<1)
-#define  SBI_RESPONSE_SUCCESS  (0x0<<1)
-#define  SBI_BUSY                              (0x1<<0)
-#define  SBI_READY                             (0x0<<0)
+#define  SBI_RESPONSE_SUCCESS          (0x0<<1)
+#define  SBI_BUSY                      (0x1<<0)
+#define  SBI_READY                     (0x0<<0)
 
 /* SBI offsets */
-#define  SBI_SSCDIVINTPHASE6           0x0600
+#define  SBI_SSCDIVINTPHASE6                   0x0600
 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK       ((0x7f)<<1)
 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)         ((x)<<1)
 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK       ((0x7f)<<8)
 #define   SBI_SSCDIVINTPHASE_INCVAL(x)         ((x)<<8)
-#define   SBI_SSCDIVINTPHASE_DIR(x)                    ((x)<<15)
+#define   SBI_SSCDIVINTPHASE_DIR(x)            ((x)<<15)
 #define   SBI_SSCDIVINTPHASE_PROPAGATE         (1<<0)
-#define  SBI_SSCCTL                                    0x020c
+#define  SBI_SSCCTL                            0x020c
 #define  SBI_SSCCTL6                           0x060C
-#define   SBI_SSCCTL_DISABLE           (1<<0)
+#define   SBI_SSCCTL_DISABLE                   (1<<0)
 #define  SBI_SSCAUXDIV6                                0x0610
 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)                ((x)<<4)
-#define  SBI_DBUFF0                                    0x2a00
+#define  SBI_DBUFF0                            0x2a00
 
 /* LPT PIXCLK_GATE */
-#define PIXCLK_GATE                            0xC6020
+#define PIXCLK_GATE                    0xC6020
 #define  PIXCLK_GATE_UNGATE            1<<0
 #define  PIXCLK_GATE_GATE              0<<0
 
 /* SPLL */
-#define SPLL_CTL                               0x46020
+#define SPLL_CTL                       0x46020
 #define  SPLL_PLL_ENABLE               (1<<31)
 #define  SPLL_PLL_SCC                  (1<<28)
 #define  SPLL_PLL_NON_SCC              (2<<28)
-#define  SPLL_PLL_FREQ_810MHz  (0<<26)
-#define  SPLL_PLL_FREQ_1350MHz (1<<26)
+#define  SPLL_PLL_FREQ_810MHz          (0<<26)
+#define  SPLL_PLL_FREQ_1350MHz         (1<<26)
 
 /* WRPLL */
-#define WRPLL_CTL1                             0x46040
-#define WRPLL_CTL2                             0x46060
-#define  WRPLL_PLL_ENABLE                              (1<<31)
-#define  WRPLL_PLL_SELECT_SSC                  (0x01<<28)
-#define  WRPLL_PLL_SELECT_NON_SCC              (0x02<<28)
+#define WRPLL_CTL1                     0x46040
+#define WRPLL_CTL2                     0x46060
+#define  WRPLL_PLL_ENABLE              (1<<31)
+#define  WRPLL_PLL_SELECT_SSC          (0x01<<28)
+#define  WRPLL_PLL_SELECT_NON_SCC      (0x02<<28)
 #define  WRPLL_PLL_SELECT_LCPLL_2700   (0x03<<28)
 /* WRPLL divider programming */
-#define  WRPLL_DIVIDER_REFERENCE(x)            ((x)<<0)
-#define  WRPLL_DIVIDER_POST(x)                 ((x)<<8)
-#define  WRPLL_DIVIDER_FEEDBACK(x)             ((x)<<16)
+#define  WRPLL_DIVIDER_REFERENCE(x)    ((x)<<0)
+#define  WRPLL_DIVIDER_POST(x)         ((x)<<8)
+#define  WRPLL_DIVIDER_FEEDBACK(x)     ((x)<<16)
 
 /* Port clock selection */
 #define PORT_CLK_SEL_A                 0x46100
 #define PORT_CLK_SEL_B                 0x46104
-#define PORT_CLK_SEL(port) _PORT(port, \
-                                       PORT_CLK_SEL_A, \
-                                       PORT_CLK_SEL_B)
+#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
 #define  PORT_CLK_SEL_LCPLL_2700       (0<<29)
 #define  PORT_CLK_SEL_LCPLL_1350       (1<<29)
 #define  PORT_CLK_SEL_LCPLL_810                (2<<29)
-#define  PORT_CLK_SEL_SPLL                     (3<<29)
+#define  PORT_CLK_SEL_SPLL             (3<<29)
 #define  PORT_CLK_SEL_WRPLL1           (4<<29)
 #define  PORT_CLK_SEL_WRPLL2           (5<<29)
 
 /* Pipe clock selection */
 #define PIPE_CLK_SEL_A                 0x46140
 #define PIPE_CLK_SEL_B                 0x46144
-#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \
-                                       PIPE_CLK_SEL_A, \
-                                       PIPE_CLK_SEL_B)
+#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
 /* For each pipe, we need to select the corresponding port clock */
-#define  PIPE_CLK_SEL_DISABLED (0x0<<29)
-#define  PIPE_CLK_SEL_PORT(x)  ((x+1)<<29)
+#define  PIPE_CLK_SEL_DISABLED         (0x0<<29)
+#define  PIPE_CLK_SEL_PORT(x)          ((x+1)<<29)
 
 /* LCPLL Control */
-#define LCPLL_CTL                              0x130040
+#define LCPLL_CTL                      0x130040
 #define  LCPLL_PLL_DISABLE             (1<<31)
 #define  LCPLL_PLL_LOCK                        (1<<30)
-#define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
+#define  LCPLL_CD_CLOCK_DISABLE                (1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
 
 /* Pipe WM_LINETIME - watermark line time */
 #define PIPE_WM_LINETIME_A             0x45270
 #define PIPE_WM_LINETIME_B             0x45274
-#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
-                                       PIPE_WM_LINETIME_A, \
-                                       PIPE_WM_LINETIME_B)
-#define   PIPE_WM_LINETIME_MASK                (0x1ff)
-#define   PIPE_WM_LINETIME_TIME(x)                     ((x))
+#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
+                                          PIPE_WM_LINETIME_B)
+#define   PIPE_WM_LINETIME_MASK                        (0x1ff)
+#define   PIPE_WM_LINETIME_TIME(x)             ((x))
 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK   (0x1ff<<16)
-#define   PIPE_WM_LINETIME_IPS_LINETIME(x)             ((x)<<16)
+#define   PIPE_WM_LINETIME_IPS_LINETIME(x)     ((x)<<16)
 
 /* SFUSE_STRAP */
-#define SFUSE_STRAP                            0xc2014
+#define SFUSE_STRAP                    0xc2014
 #define  SFUSE_STRAP_DDIB_DETECTED     (1<<2)
 #define  SFUSE_STRAP_DDIC_DETECTED     (1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED     (1<<0)