Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding

Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1470153381-20517-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index ee66df082a42db125d1201f19e2262ca24ad1f38..4a1714f96babb4c3c2b51c1a1556cd17c9608e23 100644 (file)
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -122,6 +122,15 @@ Required Properties:
 - interrupts      : Should be single bit error interrupt, then double bit error
        interrupt, in this order.
 
+SDMMC FIFO ECC
+Required Properties:
+- compatible      : Should be "altr,socfpga-sdmmc-ecc"
+- reg             : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent SD/MMC node.
+- interrupts      : Should be single bit error interrupt, then double bit error
+       interrupt, in this order for port A, and then single bit error interrupt,
+       then double bit error interrupt in this order for port B.
+
 Example:
 
        eccmgr: eccmgr@ffd06000 {
@@ -211,4 +220,14 @@ Example:
                        interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
                                     <46 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               sdmmc-ecc@ff8c2c00 {
+                       compatible = "altr,socfpga-sdmmc-ecc";
+                       reg = <0xff8c2c00 0x400>;
+                       altr,ecc-parent = <&mmc>;
+                       interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+                                    <47 IRQ_TYPE_LEVEL_HIGH>,
+                                    <16 IRQ_TYPE_LEVEL_HIGH>,
+                                    <48 IRQ_TYPE_LEVEL_HIGH>;
+               };
        };