u32 dbck_enable_mask;
struct device *dev;
bool dbck_flag;
+ int stride;
};
#ifdef CONFIG_ARCH_OMAP3
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_IO_CNTL;
+ reg += OMAP_MPUIO_IO_CNTL / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT;
+ reg += OMAP_MPUIO_OUTPUT / bank->stride;
l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_INPUT_LATCH;
+ reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT;
+ reg += OMAP_MPUIO_OUTPUT / bank->stride;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
break;
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
l = __raw_readl(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_MASKIT;
+ reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
mask = 0xffff;
inv = 1;
break;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_MASKIT;
+ reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
l = __raw_readl(reg);
if (enable)
l &= ~(gpio_mask);
bank = get_irq_data(irq);
#ifdef CONFIG_ARCH_OMAP1
if (bank->method == METHOD_MPUIO)
- isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
+ isr_reg = bank->base +
+ OMAP_MPUIO_GPIO_INT / bank->stride;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (bank->method == METHOD_GPIO_1510)
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
- void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ void __iomem *mask_reg = bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
- void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ void __iomem *mask_reg = bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_IO_CNTL;
+ reg += OMAP_MPUIO_IO_CNTL / bank->stride;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
}
} else if (cpu_class_is_omap1()) {
if (bank_is_mpuio(bank))
- __raw_writew(0xffff, bank->base
- + OMAP_MPUIO_GPIO_MASKIT);
+ __raw_writew(0xffff, bank->base +
+ OMAP_MPUIO_GPIO_MASKIT / bank->stride);
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
__raw_writew(0xffff, bank->base
+ OMAP1510_GPIO_INT_MASK);
bank->method = pdata->bank_type;
bank->dev = &pdev->dev;
bank->dbck_flag = pdata->dbck_flag;
+ bank->stride = pdata->bank_stride;
bank_width = pdata->bank_width;
spin_lock_init(&bank->lock);
#define OMAP1_MPUIO_BASE 0xfffb5000
-#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
-
-#define OMAP_MPUIO_INPUT_LATCH 0x00
-#define OMAP_MPUIO_OUTPUT 0x02
-#define OMAP_MPUIO_IO_CNTL 0x04
-#define OMAP_MPUIO_KBR_LATCH 0x08
-#define OMAP_MPUIO_KBC 0x0a
-#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
-#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
-#define OMAP_MPUIO_KBD_INT 0x10
-#define OMAP_MPUIO_GPIO_INT 0x12
-#define OMAP_MPUIO_KBD_MASKIT 0x14
-#define OMAP_MPUIO_GPIO_MASKIT 0x16
-#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
-#define OMAP_MPUIO_LATCH 0x1a
-#else
+/*
+ * These are the omap15xx/16xx offsets. The omap7xx offset are
+ * OMAP_MPUIO_ / 2 offsets below.
+ */
#define OMAP_MPUIO_INPUT_LATCH 0x00
#define OMAP_MPUIO_OUTPUT 0x04
#define OMAP_MPUIO_IO_CNTL 0x08
#define OMAP_MPUIO_GPIO_MASKIT 0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
#define OMAP_MPUIO_LATCH 0x34
-#endif
#define OMAP34XX_NR_GPIOS 6
u16 virtual_irq_start;
int bank_type;
int bank_width; /* GPIO bank width */
+ int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
};