drm/i915: s/pm_intr_keep/pm_intrmsk_mbz

"pm_intr_keep" is not conveying the intent that it is bitmask
of interrupts that must be zero(mbz) in GEN6_PMINTRMSK.
Name it "pm_intrmsk_mbz".

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489199821-6707-2-git-send-email-sagar.a.kamble@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 56674df31275103ed9278a9b93fc3ef1039d0c74..82fb005a5e221ac948f2b7e39987a9e484f6ba6d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1189,7 +1189,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                }
                seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
                           pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
-               seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
+               seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
+                          dev_priv->rps.pm_intrmsk_mbz);
                seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
                seq_printf(m, "Render p-state ratio: %d\n",
                           (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4d1fb620de8f3cd064da1b22576c33bb6a8265d2..f4d87d33f51386a6502fdf6bc61a988e2b7ef92f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1337,7 +1337,7 @@ struct intel_gen6_power_mgmt {
        u32 pm_iir;
 
        /* PM interrupt bits that should never be masked */
-       u32 pm_intr_keep;
+       u32 pm_intrmsk_mbz;
 
        /* Frequencies are stored in potentially platform dependent multiples.
         * In other words, *_freq needs to be multiplied by X to be interesting.

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ce445bccf0cacc93fc99e661d71112e617e5a563..a6bf6199aeda06bd510f74142849ab502db533cb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -391,7 +391,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 
 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 {
-       return (mask & ~dev_priv->rps.pm_intr_keep);
+       return (mask & ~dev_priv->rps.pm_intrmsk_mbz);
 }
 
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
@@ -4270,7 +4270,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
        else
                dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
 
-       dev_priv->rps.pm_intr_keep = 0;
+       dev_priv->rps.pm_intrmsk_mbz = 0;
 
        /*
         * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
@@ -4279,33 +4279,33 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
         * TODO: verify if this can be reproduced on VLV,CHV.
         */
        if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
-               dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
+               dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
        if (INTEL_INFO(dev_priv)->gen >= 8)
-               dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
+               dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;
 
        /*
         * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
         * (unmasked) PM interrupts to the GuC. All other bits of this
         * register *disable* generation of a specific interrupt.
         *
-        * 'pm_intr_keep' indicates bits that are NOT to be set when
+        * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
         * writing to the PM interrupt mask register, i.e. interrupts
         * that must not be disabled.
         *
         * If the GuC is handling these interrupts, then we must not let
         * the PM code disable ANY interrupt that the GuC is expecting.
         * So for each ENABLED (0) bit in this register, we must SET the
-        * bit in pm_intr_keep so that it's left enabled for the GuC.
+        * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
         * GuC needs ARAT expired interrupt unmasked hence it is set in
-        * pm_intr_keep.
+        * pm_intrmsk_mbz.
         *
-        * Here we CLEAR REDIRECT_TO_GUC bit in pm_intr_keep, which will
+        * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
         * result in the register bit being left SET!
         */
        if (HAS_GUC_SCHED(dev_priv)) {
-               dev_priv->rps.pm_intr_keep |= ARAT_EXPIRED_INTRMSK;
-               dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
+               dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+               dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
        }
 
        if (IS_GEN2(dev_priv)) {