ctx->config.parm.dec.cfg.canvas_mem_mode);
pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
ctx->config.parm.dec.cfg.canvas_mem_endian);
+ pbuf += sprintf(pbuf, "parm_v4l_low_latency_mode:%d;",
+ ctx->config.parm.dec.cfg.low_latency_mode);
ctx->config.length = pbuf - ctx->config.buf;
} else {
ctx->config.parm.dec.cfg.double_write_mode = 16;
ctx->config.parm.dec.cfg.canvas_mem_mode);
pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
ctx->config.parm.dec.cfg.canvas_mem_endian);
+ pbuf += sprintf(pbuf, "parm_v4l_low_latency_mode:%d;",
+ ctx->config.parm.dec.cfg.low_latency_mode);
ctx->config.length = pbuf - ctx->config.buf;
} else {
ctx->config.parm.dec.cfg.double_write_mode = 16;
ctx->config.parm.dec.cfg.canvas_mem_mode);
pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;",
ctx->config.parm.dec.cfg.canvas_mem_endian);
+ pbuf += sprintf(pbuf, "parm_v4l_low_latency_mode:%d;",
+ ctx->config.parm.dec.cfg.low_latency_mode);
ctx->config.length = pbuf - ctx->config.buf;
} else {
ctx->config.parm.dec.cfg.double_write_mode = 16;
if (get_config_int(pdata->config,
"parm_v4l_low_latency_mode",
&config_val) == 0)
- hw->low_latency_mode = config_val;
+ hw->low_latency_mode = config_val ? 0x8:0;
if (get_config_int(pdata->config, "sidebind_type",
&config_val) == 0)
hw->sidebind_type = config_val;
bool discard_dv_data;
bool enable_fence;
int fence_usage;
+ int low_latency_flag;
} /*hevc_stru_t */;
#ifdef AGAIN_HAS_THRESHOLD
new_pic->num_reorder_pic = rpm_param->p.sps_num_reorder_pics_0;
new_pic->ip_mode = (!new_pic->num_reorder_pic &&
!(vdec->slave || vdec->master) &&
- !disable_ip_mode) ? true : false;
+ !disable_ip_mode &&
+ hevc->low_latency_flag) ? true : false;
new_pic->losless_comp_body_size = hevc->losless_comp_body_size;
new_pic->POC = hevc->curr_POC;
new_pic->pic_struct = hevc->curr_pic_struct;
hevc->param.p.sps_num_reorder_pics_0;
hevc->ip_mode = (!hevc->sps_num_reorder_pics_0 &&
!(vdec->slave || vdec->master) &&
- !disable_ip_mode) ? true : false;
+ !disable_ip_mode &&
+ hevc->low_latency_flag) ? true : false;
hevc->pic_list_init_flag = 1;
if ((!IS_4K_SIZE(hevc->pic_w, hevc->pic_h)) &&
((hevc->param.p.profile_etc & 0xc) == 0x4)
"parm_fence_usage",
&config_val) == 0)
hevc->fence_usage = config_val;
+
+ if (get_config_int(pdata->config,
+ "parm_v4l_low_latency_mode",
+ &config_val) == 0)
+ hevc->low_latency_flag = config_val;
+
#endif
} else {
if (pdata->sys_info)
"parm_v4l_canvas_mem_mode",
&config_val) == 0)
hw->mem_map_mode = config_val;
+
+ if (get_config_int(pdata->config,
+ "parm_v4l_low_latency_mode",
+ &config_val) == 0)
+ hw->low_latency_flag = config_val;
+
#endif
if (get_config_int(pdata->config, "HDRStaticInfo",
&vf_dp.present_flag) == 0
"parm_fence_usage",
&config_val) == 0)
pbi->fence_usage = config_val;
+
+ if (get_config_int(pdata->config,
+ "parm_v4l_low_latency_mode",
+ &config_val) == 0)
+ pbi->low_latency_flag = config_val;
#endif
if (get_config_int(pdata->config, "HDRStaticInfo",
&vf_dp.present_flag) == 0
pbi->vvp9_amstream_dec_info.height = 0;
pbi->vvp9_amstream_dec_info.rate = 30;
}
- pbi->low_latency_flag = 1;
+ pbi->low_latency_flag = 1;
vp9_print(pbi, 0,
"no_head %d low_latency %d\n",
pbi->no_head, pbi->low_latency_flag);