i40e: trigger SW INT with no ITR wait

Since we want the SW INT to go off as soon as possible, write the
extra bits that will turn off the ITR wait for the interrupt.

Change-ID: I6d5382ba60840fa32abb7dea17c839eb4b5f68f7
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
index bb1698a7b3d125a5e8bc7839d3aa4cfb3c79318c..b2402851a9bd669ad5710833d8a4e5226aa41480 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
@@ -1400,7 +1400,10 @@ static int i40e_intr_test(struct net_device *netdev, u64 *data)
        netif_info(pf, hw, netdev, "interrupt test\n");
        wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
             (I40E_PFINT_DYN_CTL0_INTENA_MASK |
-             I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
+             I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
+             I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
+             I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
+             I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
        usleep_range(1000, 2000);
        *data = (swc_old == pf->sw_int_count);
 

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 3ebab039fbb3c4842a8998c0fc987fb6a7d0f3a1..3913329998bffbcd6acfedbb422106e8643ceb94 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -5565,11 +5565,17 @@ static void i40e_check_hang_subtask(struct i40e_pf *pf)
                        if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
                                wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
                                     (I40E_PFINT_DYN_CTL0_INTENA_MASK |
-                                     I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
+                                     I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
+                                     I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
+                                     I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
+                                     I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
                        } else {
                                u16 vec = vsi->base_vector - 1;
                                u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
-                                          I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
+                                     I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
+                                     I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
+                                     I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
+                                     I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
                                for (i = 0; i < vsi->num_q_vectors; i++, vec++)
                                        wr32(&vsi->back->hw,
                                             I40E_PFINT_DYN_CTLN(vec), val);