powerpc/mpc85xx: Update clock nodes in device tree

The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 5a6615d0ade24717ed73a21fe8456bc420380a77..60566f9927be576de6797accfc578f6b1e5fd7ad 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -86,6 +86,42 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+               ranges = <0x0 0xe1000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-2.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-2.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                               <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                       clock-names = "pll0", "pll0-div2", "pll0-div4",
+                               "pll1", "pll1-div2", "pll1-div4";
+                       clock-output-names = "cmux0";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index c6e451affb055958b3943378878d6dc4c4a59284..2419731c2c5443b35c1f6edde0f89808fc7bbef6 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -64,11 +64,13 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
        };

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 981397518fc6243919e78118944d8dda2f763f6b..cbc354b05117344342bab0d839749e19a0f2b832 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -130,6 +130,42 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
+               ranges = <0x0 0xe1000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-2.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-2.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                               <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                       clock-names = "pll0", "pll0-div2", "pll0-div4",
+                               "pll1", "pll1-div2", "pll1-div4";
+                       clock-output-names = "cmux0";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 9bc26b14790061ea3793f7b3f4afa7c06efd09d3..142ac862cacfd2b1362ebf508ca9e11f9237fb3e 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -64,21 +64,25 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
        };

diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index dc6cc5afd189b6f1e66c200e994e75760229d2a3..e2987a33083cbbeb51b5d66984f2508e740759d7 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -306,8 +306,68 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-1.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux1";
+               };
+
+               mux2: mux2@40 {
+                       #clock-cells = <0>;
+                       reg = <0x40 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+               };
+
+               mux3: mux3@60 {
+                       #clock-cells = <0>;
+                       reg = <0x60 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux3";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 7a2697d04549535e74d5b78924c90e2bf193cef5..22f3b14517de83fc5f4c891d06eed37fb762cb68 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                       clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;

diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 3fa1e22d544a51c76848c9113cdc5726b575c7e3..7af6d45fd998b6470a94e198855772e9d5313d5d 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -333,8 +333,69 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-1.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux1";
+               };
+
+               mux2: mux2@40 {
+                       #clock-cells = <0>;
+                       reg = <0x40 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux2";
+               };
+
+               mux3: mux3@60 {
+                       #clock-cells = <0>;
+                       reg = <0x60 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux3";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index c9ca2c305cfecff64052e084d44b35af7ff02ce1..468e8be8ac6f82cc40c149fb50edab9baf5260d5 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -82,6 +82,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -90,6 +91,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -98,6 +100,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -106,6 +109,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                       clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;

diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7eafea17cec138f0885feb8a476adf6d94..2415e1f1d3fafe6801020bbbf62d200bf8e47581 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -353,8 +353,121 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-1.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2";
+               };
+
+               pll2: pll2@840 {
+                       #clock-cells = <1>;
+                       reg = <0x840 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll2", "pll2-div2";
+               };
+
+               pll3: pll3@860 {
+                       #clock-cells = <1>;
+                       reg = <0x860 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll3", "pll3-div2";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux1";
+               };
+
+               mux2: mux2@40 {
+                       #clock-cells = <0>;
+                       reg = <0x40 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux2";
+               };
+
+               mux3: mux3@60 {
+                       #clock-cells = <0>;
+                       reg = <0x60 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux3";
+               };
+
+               mux4: mux4@80 {
+                       #clock-cells = <0>;
+                       reg = <0x80 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                       clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                       clock-output-names = "cmux4";
+               };
+
+               mux5: mux5@a0 {
+                       #clock-cells = <0>;
+                       reg = <0xa0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                       clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                       clock-output-names = "cmux5";
+               };
+
+               mux6: mux6@c0 {
+                       #clock-cells = <0>;
+                       reg = <0xc0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                       clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                       clock-output-names = "cmux6";
+               };
+
+               mux7: mux7@e0 {
+                       #clock-cells = <0>;
+                       reg = <0xe0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                       clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                       clock-output-names = "cmux7";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 493d9a056b5caceffbc58c80baf38a2fec8c2f25..0040b5a5379e2de22819988902e26b5e5f94dde2 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                       clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
@@ -113,6 +117,7 @@
                cpu4: PowerPC,e500mc@4 {
                        device_type = "cpu";
                        reg = <4>;
+                       clocks = <&mux4>;
                        next-level-cache = <&L2_4>;
                        L2_4: l2-cache {
                                next-level-cache = <&cpc>;
@@ -121,6 +126,7 @@
                cpu5: PowerPC,e500mc@5 {
                        device_type = "cpu";
                        reg = <5>;
+                       clocks = <&mux5>;
                        next-level-cache = <&L2_5>;
                        L2_5: l2-cache {
                                next-level-cache = <&cpc>;
@@ -129,6 +135,7 @@
                cpu6: PowerPC,e500mc@6 {
                        device_type = "cpu";
                        reg = <6>;
+                       clocks = <&mux6>;
                        next-level-cache = <&L2_6>;
                        L2_6: l2-cache {
                                next-level-cache = <&cpc>;
@@ -137,6 +144,7 @@
                cpu7: PowerPC,e500mc@7 {
                        device_type = "cpu";
                        reg = <7>;
+                       clocks = <&mux7>;
                        next-level-cache = <&L2_7>;
                        L2_7: l2-cache {
                                next-level-cache = <&cpc>;

diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index bc3ae5a2252f451a4bdcc76ead0dff12fd5b553f..2985de4ad6bec72d0d28331e88558bf1c5cbd58d 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -338,8 +338,51 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-1.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux1";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 8df47fc45ab530c2523c3ae0968f61d5aa09c685..fe1a2e6613b49b8c116d65763e79f160e023b9e3 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -88,6 +88,7 @@
                cpu0: PowerPC,e5500@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -96,6 +97,7 @@
                cpu1: PowerPC,e5500@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;

diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index a91897f6af0989b92f8f8ed717b554c13514a044..546a899efe20eca6ec44bade2d2df2831e95d7f3 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -298,8 +298,69 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-1.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-1.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux1";
+               };
+
+               mux2: mux2@40 {
+                       #clock-cells = <0>;
+                       reg = <0x40 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux2";
+               };
+
+               mux3: mux3@60 {
+                       #clock-cells = <0>;
+                       reg = <0x60 0x4>;
+                       compatible = "fsl,qoriq-core-mux-1.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                       clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                       clock-output-names = "cmux3";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 40ca943f5d1cac4e34a01413633dc640382edaec..3674686687cbfd24066b53debf34111ab63125c7 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e5500@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e5500@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e5500@2 {
                        device_type = "cpu";
                        reg = <2>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e5500@3 {
                        device_type = "cpu";
                        reg = <3>;
+                       clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;

diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 4143a9733cd01e0ad62d9d3d98902e7f414dd8f3..f99d74ff11b4f95cf3a312b1aa7645c6df6c24a9 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -369,7 +369,93 @@
 
        clockgen: global-utilities@e1000 {
                compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
+               ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               sysclk: sysclk {
+                       #clock-cells = <0>;
+                       compatible = "fsl,qoriq-sysclk-2.0";
+                       clock-output-names = "sysclk";
+               };
+
+               pll0: pll0@800 {
+                       #clock-cells = <1>;
+                       reg = <0x800 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+               };
+
+               pll1: pll1@820 {
+                       #clock-cells = <1>;
+                       reg = <0x820 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+               };
+
+               pll2: pll2@840 {
+                       #clock-cells = <1>;
+                       reg = <0x840 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll2", "pll2-div2", "pll2-div4";
+               };
+
+               pll3: pll3@860 {
+                       #clock-cells = <1>;
+                       reg = <0x860 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll3", "pll3-div2", "pll3-div4";
+               };
+
+               pll4: pll4@880 {
+                       #clock-cells = <1>;
+                       reg = <0x880 0x4>;
+                       compatible = "fsl,qoriq-core-pll-2.0";
+                       clocks = <&sysclk>;
+                       clock-output-names = "pll4", "pll4-div2", "pll4-div4";
+               };
+
+               mux0: mux0@0 {
+                       #clock-cells = <0>;
+                       reg = <0x0 0x4>;
+                       compatible = "fsl,qoriq-core-mux-2.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                               <&pll1 0>, <&pll1 1>, <&pll1 2>,
+                               <&pll2 0>, <&pll2 1>, <&pll2 2>;
+                       clock-names = "pll0", "pll0-div2", "pll0-div4",
+                               "pll1", "pll1-div2", "pll1-div4",
+                               "pll2", "pll2-div2", "pll2-div4";
+                       clock-output-names = "cmux0";
+               };
+
+               mux1: mux1@20 {
+                       #clock-cells = <0>;
+                       reg = <0x20 0x4>;
+                       compatible = "fsl,qoriq-core-mux-2.0";
+                       clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                               <&pll1 0>, <&pll1 1>, <&pll1 2>,
+                               <&pll2 0>, <&pll2 1>, <&pll2 2>;
+                       clock-names = "pll0", "pll0-div2", "pll0-div4",
+                               "pll1", "pll1-div2", "pll1-div4",
+                               "pll2", "pll2-div2", "pll2-div4";
+                       clock-output-names = "cmux1";
+               };
+
+               mux2: mux2@40 {
+                       #clock-cells = <0>;
+                       reg = <0x40 0x4>;
+                       compatible = "fsl,qoriq-core-mux-2.0";
+                       clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
+                               <&pll4 0>, <&pll4 1>, <&pll4 2>;
+                       clock-names = "pll3", "pll3-div2", "pll3-div4",
+                               "pll4", "pll4-div2", "pll4-div4";
+                       clock-output-names = "cmux2";
+               };
        };
 
        rcpm: global-utilities@e2000 {

diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index a93c55a885601a098abc4187ac2b38d3f3d7bc8e..0b8ccc5b4a46575088acd599a01fd0aef3909d98 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -67,61 +67,73 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
+                       clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu4: PowerPC,e6500@8 {
                        device_type = "cpu";
                        reg = <8 9>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu5: PowerPC,e6500@10 {
                        device_type = "cpu";
                        reg = <10 11>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu6: PowerPC,e6500@12 {
                        device_type = "cpu";
                        reg = <12 13>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu7: PowerPC,e6500@14 {
                        device_type = "cpu";
                        reg = <14 15>;
+                       clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu8: PowerPC,e6500@16 {
                        device_type = "cpu";
                        reg = <16 17>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu9: PowerPC,e6500@18 {
                        device_type = "cpu";
                        reg = <18 19>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu10: PowerPC,e6500@20 {
                        device_type = "cpu";
                        reg = <20 21>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu11: PowerPC,e6500@22 {
                        device_type = "cpu";
                        reg = <22 23>;
+                       clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
        };