arm: mach-orion5x: convert to use mvebu-mbus driver
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 21 Mar 2013 16:59:18 +0000 (17:59 +0100)
committerJason Cooper <jason@lakedaemon.net>
Mon, 15 Apr 2013 14:06:34 +0000 (14:06 +0000)
This commit migrates the mach-orion5x platforms to use the mvebu-mbus
driver and therefore removes the Orion5x-specific addr-map code.

The dove_init_early() function now initializes the mvebu-mbus driver
by calling mvebu_mbus_init().

We also convert a number of orion5x_setup_xyz_win() calls to the
appropriate mvebu_mbus_add_window() calls, as each board was doing its
own setup for the NOR window or other devices. Ultimately, those
devices will be probed from the DT.

The common address decoding windows are now registered in the
orion5x_setup_wins() function. It is worth noting that the four PCIe
address decoding windows will ultimately no longer have to be
registered here: it will be done automatically by the PCIe driver once
Dove has been migrated to use the upcoming mvebu PCIe driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
28 files changed:
arch/arm/Kconfig
arch/arm/mach-orion5x/Makefile
arch/arm/mach-orion5x/addr-map.c [deleted file]
arch/arm/mach-orion5x/board-dt.c
arch/arm/mach-orion5x/common.c
arch/arm/mach-orion5x/common.h
arch/arm/mach-orion5x/d2net-setup.c
arch/arm/mach-orion5x/db88f5281-setup.c
arch/arm/mach-orion5x/dns323-setup.c
arch/arm/mach-orion5x/edmini_v2-setup.c
arch/arm/mach-orion5x/include/mach/orion5x.h
arch/arm/mach-orion5x/kurobox_pro-setup.c
arch/arm/mach-orion5x/ls-chl-setup.c
arch/arm/mach-orion5x/ls_hgl-setup.c
arch/arm/mach-orion5x/lsmini-setup.c
arch/arm/mach-orion5x/mss2-setup.c
arch/arm/mach-orion5x/mv2120-setup.c
arch/arm/mach-orion5x/net2big-setup.c
arch/arm/mach-orion5x/pci.c
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
arch/arm/mach-orion5x/rd88f5182-setup.c
arch/arm/mach-orion5x/terastation_pro2-setup.c
arch/arm/mach-orion5x/ts209-setup.c
arch/arm/mach-orion5x/ts409-setup.c
arch/arm/mach-orion5x/wnr854t-setup.c
arch/arm/mach-orion5x/wrt350n-v2-setup.c
arch/arm/plat-orion/Makefile

index 6ee09663e929824809fb7647a9488ffb8166ead0..b6f5f28ef007f09f694123af3e2a3fc5784c6c63 100644 (file)
@@ -600,6 +600,7 @@ config ARCH_ORION5X
        select GENERIC_CLOCKEVENTS
        select PCI
        select PLAT_ORION_LEGACY
+       select MVEBU_MBUS
        help
          Support for the following Marvell Orion 5x series SoCs:
          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
index 9e809a7c05c0c607b00433fc6a95047ac1365e7c..45da805fb23692d07703310e8076a0cd8e4070f5 100644 (file)
@@ -1,4 +1,4 @@
-obj-y                          += common.o addr-map.o pci.o irq.o mpp.o
+obj-y                          += common.o pci.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)   += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)   += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
deleted file mode 100644 (file)
index b5efc0f..0000000
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-orion5x/addr-map.c
- *
- * Address map functions for Marvell Orion 5x SoCs
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <plat/addr-map.h>
-#include "common.h"
-
-/*
- * The Orion has fully programmable address map. There's a separate address
- * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
- * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
- * address decode windows that allow it to access any of the Orion resources.
- *
- * CPU address decoding --
- * Linux assumes that it is the boot loader that already setup the access to
- * DDR and internal registers.
- * Setup access to PCI and PCIe IO/MEM space is issued by this file.
- * Setup access to various devices located on the device bus interface (e.g.
- * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion5x_setup_*_win()).
- *
- * Non-CPU Masters address decoding --
- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
- * banks only (the typical use case).
- * Setup access for each master to DDR is issued by platform device setup.
- */
-
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DEV_BUS         1
-#define TARGET_PCI             3
-#define TARGET_PCIE            4
-#define TARGET_SRAM            9
-#define ATTR_PCIE_MEM          0x59
-#define ATTR_PCIE_IO           0x51
-#define ATTR_PCIE_WA           0x79
-#define ATTR_PCI_MEM           0x59
-#define ATTR_PCI_IO            0x51
-#define ATTR_DEV_CS0           0x1e
-#define ATTR_DEV_CS1           0x1d
-#define ATTR_DEV_CS2           0x1b
-#define ATTR_DEV_BOOT          0xf
-#define ATTR_SRAM              0x0
-
-static int __initdata win_alloc_count;
-
-static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
-                 const int win)
-{
-       u32 dev, rev;
-
-       orion5x_pcie_id(&dev, &rev);
-       if ((dev == MV88F5281_DEV_ID && win < 4)
-           || (dev == MV88F5182_DEV_ID && win < 2)
-           || (dev == MV88F5181_DEV_ID && win < 2)
-           || (dev == MV88F6183_DEV_ID && win < 4))
-               return 1;
-
-       return 0;
-}
-
-/*
- * Description of the windows needed by the platform code
- */
-static struct orion_addr_map_cfg addr_map_cfg __initdata = {
-       .num_wins = 8,
-       .cpu_win_can_remap = cpu_win_can_remap,
-       .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
-};
-
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
-       /*
-        * Setup windows for PCI+PCIe IO+MEM space.
-        */
-       { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
-         TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
-       },
-       { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-         TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
-       },
-       { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-         TARGET_PCIE, ATTR_PCIE_MEM, -1
-       },
-       { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
-         TARGET_PCI, ATTR_PCI_MEM, -1
-       },
-       /* End marker */
-       { -1, 0, 0, 0, 0, 0 }
-};
-
-void __init orion5x_setup_cpu_mbus_bridge(void)
-{
-       /*
-        * Disable, clear and configure windows.
-        */
-       orion_config_wins(&addr_map_cfg, addr_map_info);
-       win_alloc_count = 4;
-
-       /*
-        * Setup MBUS dram target info.
-        */
-       orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                   (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
-}
-
-void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                           TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
-}
-
-void __init orion5x_setup_dev0_win(u32 base, u32 size)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                           TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
-}
-
-void __init orion5x_setup_dev1_win(u32 base, u32 size)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                           TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
-}
-
-void __init orion5x_setup_dev2_win(u32 base, u32 size)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                           TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
-}
-
-void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                           TARGET_PCIE, ATTR_PCIE_WA, -1);
-}
-
-void __init orion5x_setup_sram_win(void)
-{
-       orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
-                           ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
-                           TARGET_SRAM, ATTR_SRAM, -1);
-}
index 35a8014529ca7b45b68a769a59e8a8d11d3e0782..6bbc8786c1e3f0e1ed3021c70148676e3f7301eb 100644 (file)
@@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void)
        /*
         * Setup Orion address map
         */
-       orion5x_setup_cpu_mbus_bridge();
+       orion5x_setup_wins();
 
        /* Setup root of clk tree */
        clk_init();
index d068f1431c402965004105c3ddb1018ec3b6d8ec..8e468e3a60153a483d02a07219fa31ac1055a218 100644 (file)
@@ -34,7 +34,6 @@
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
-#include <plat/addr-map.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -174,7 +173,8 @@ void __init orion5x_xor_init(void)
  ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-       orion5x_setup_sram_win();
+       mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
+                             ORION5X_SRAM_SIZE);
        orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                          SZ_8K, IRQ_ORION5X_CESA);
 }
@@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void)
  ****************************************************************************/
 void __init orion5x_init_early(void)
 {
+       u32 rev, dev;
+       const char *mbus_soc_name;
+
        orion_time_set_base(TIMER_VIRT_BASE);
 
        /*
@@ -201,6 +204,46 @@ void __init orion5x_init_early(void)
         * the allocations won't fail.
         */
        init_dma_coherent_pool_size(SZ_1M);
+
+       /* Initialize the MBUS driver */
+       orion5x_pcie_id(&dev, &rev);
+       if (dev == MV88F5281_DEV_ID)
+               mbus_soc_name = "marvell,orion5x-88f5281-mbus";
+       else if (dev == MV88F5182_DEV_ID)
+               mbus_soc_name = "marvell,orion5x-88f5182-mbus";
+       else if (dev == MV88F5181_DEV_ID)
+               mbus_soc_name = "marvell,orion5x-88f5181-mbus";
+       else if (dev == MV88F6183_DEV_ID)
+               mbus_soc_name = "marvell,orion5x-88f6183-mbus";
+       else
+               mbus_soc_name = NULL;
+       mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
+                       ORION5X_BRIDGE_WINS_SZ,
+                       ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
+}
+
+void orion5x_setup_wins(void)
+{
+       /*
+        * The PCIe windows will no longer be statically allocated
+        * here once Orion5x is migrated to the pci-mvebu driver.
+        */
+       mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+                                         ORION5X_PCIE_IO_SIZE,
+                                         ORION5X_PCIE_IO_BUS_BASE,
+                                         MVEBU_MBUS_PCI_IO);
+       mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
+                                         ORION5X_PCIE_MEM_SIZE,
+                                         MVEBU_MBUS_NO_REMAP,
+                                         MVEBU_MBUS_PCI_MEM);
+       mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+                                         ORION5X_PCI_IO_SIZE,
+                                         ORION5X_PCI_IO_BUS_BASE,
+                                         MVEBU_MBUS_PCI_IO);
+       mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
+                                         ORION5X_PCI_MEM_SIZE,
+                                         MVEBU_MBUS_NO_REMAP,
+                                         MVEBU_MBUS_PCI_MEM);
 }
 
 int orion5x_tclk;
@@ -282,7 +325,7 @@ void __init orion5x_init(void)
        /*
         * Setup Orion address map
         */
-       orion5x_setup_cpu_mbus_bridge();
+       orion5x_setup_wins();
 
        /* Setup root of clk tree */
        clk_init();
index e60345760283a9263a10be96c3fa4fd54a7c9c91..cdaa01f3d186f59a9b41fd7bff58853c957817ec 100644 (file)
@@ -17,18 +17,7 @@ void clk_init(void);
 extern int orion5x_tclk;
 extern void orion5x_timer_init(void);
 
-/*
- * Enumerations and functions for Orion windows mapping. Used by Orion core
- * functions to map its interfaces and by the machine-setup to map its on-
- * board devices. Details in /mach-orion/addr-map.c
- */
-void orion5x_setup_cpu_mbus_bridge(void);
-void orion5x_setup_dev_boot_win(u32 base, u32 size);
-void orion5x_setup_dev0_win(u32 base, u32 size);
-void orion5x_setup_dev1_win(u32 base, u32 size);
-void orion5x_setup_dev2_win(u32 base, u32 size);
-void orion5x_setup_pcie_wa_win(u32 base, u32 size);
-void orion5x_setup_sram_win(void);
+void orion5x_setup_wins(void);
 
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
index 57d0af74874d0877a77dc0d4a44c4bebe56b7605..16c88bbabc9814d2b9967efa3aab2becaa054604 100644 (file)
@@ -317,8 +317,8 @@ static void __init d2net_init(void)
        d2net_sata_power_init();
        orion5x_sata_init(&d2net_sata_data);
 
-       orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE,
-                               D2NET_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
+                             D2NET_NOR_BOOT_SIZE);
        platform_device_register(&d2net_nor_flash);
 
        platform_device_register(&d2net_gpio_buttons);
index 76665640087b879f54ef5bbc150a95e3b7de923f..4e1263da38bb2b2e21119ebfbff1b890fd3e8051 100644 (file)
@@ -340,16 +340,19 @@ static void __init db88f5281_init(void)
        orion5x_uart0_init();
        orion5x_uart1_init();
 
-       orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
-                               DB88F5281_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
+                             DB88F5281_NOR_BOOT_SIZE);
        platform_device_register(&db88f5281_boot_flash);
 
-       orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+       mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
+                             DB88F5281_7SEG_SIZE);
 
-       orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+       mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
+                             DB88F5281_NOR_SIZE);
        platform_device_register(&db88f5281_nor_flash);
 
-       orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
+       mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
+                             DB88F5281_NAND_SIZE);
        platform_device_register(&db88f5281_nand_flash);
 
        i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
index 6eb1732757fd241132cbfea85e83f79272621c84..9e6baf581ed3ef71e338c494931a0b5069ca722d 100644 (file)
@@ -611,7 +611,8 @@ static void __init dns323_init(void)
        /* setup flash mapping
         * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
         */
-       orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
+                             DNS323_NOR_BOOT_SIZE);
        platform_device_register(&dns323_nor_flash);
 
        /* Sort out LEDs, Buttons and i2c devices */
index d675e727803d214f49320db72f5b059e54d076b2..147615510dd0ccd29f1dd8d62626661dbfdd0476 100644 (file)
@@ -154,8 +154,8 @@ void __init edmini_v2_init(void)
        orion5x_ehci0_init();
        orion5x_eth_init(&edmini_v2_eth_data);
 
-       orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE,
-                               EDMINI_V2_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
+                             EDMINI_V2_NOR_BOOT_SIZE);
        platform_device_register(&edmini_v2_nor_flash);
 
        pr_notice("edmini_v2: USB device port, flash write and power-off "
index d265f5484a8e6934a7a1105c196539d27e6d3b15..b78ff324886888844ff8f6de83a4dfe5b63996da 100644 (file)
  * Orion Registers Map
  ******************************************************************************/
 
+#define ORION5X_DDR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x00000)
+#define  ORION5X_DDR_WINS_BASE          (ORION5X_DDR_PHYS_BASE + 0x1500)
+#define  ORION5X_DDR_WINS_SZ            (0x10)
 #define ORION5X_DDR_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
 #define ORION5X_DEV_BUS_PHYS_BASE      (ORION5X_REGS_PHYS_BASE + 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE      (ORION5X_REGS_VIRT_BASE + 0x10000)
 #define ORION5X_DEV_BUS_REG(x)         (ORION5X_DEV_BUS_VIRT_BASE + (x))
@@ -81,6 +83,8 @@
 
 #define ORION5X_BRIDGE_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x20000)
 #define ORION5X_BRIDGE_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x20000)
+#define  ORION5X_BRIDGE_WINS_BASE       (ORION5X_BRIDGE_PHYS_BASE)
+#define  ORION5X_BRIDGE_WINS_SZ         (0x80)
 
 #define ORION5X_PCI_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x30000)
 
index b984035262180af2c072c7f8cca492c3baed97a0..aae10e4a917cbd9e41f3a0370e0dece8ba7feed9 100644 (file)
@@ -359,13 +359,13 @@ static void __init kurobox_pro_init(void)
        orion5x_uart1_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
-                                  KUROBOX_PRO_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
+                             KUROBOX_PRO_NOR_BOOT_SIZE);
        platform_device_register(&kurobox_pro_nor_flash);
 
        if (machine_is_kurobox_pro()) {
-               orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
-                                      KUROBOX_PRO_NAND_SIZE);
+               mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
+                                     KUROBOX_PRO_NAND_SIZE);
                platform_device_register(&kurobox_pro_nand_flash);
        }
 
index 044da5b6a6ae6057efff262eed3e870716691b26..24f4e14e58939b7453c689b93580fa33facd36f4 100644 (file)
@@ -294,8 +294,8 @@ static void __init lschl_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
-                                  LSCHL_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
+                             LSCHL_NOR_BOOT_SIZE);
        platform_device_register(&lschl_nor_flash);
 
        platform_device_register(&lschl_leds);
index d49f93423f52feaeb2061542982ce0db477d7fa3..fc653bb41e78f0889b5956b79db41e18d66f17bf 100644 (file)
@@ -243,8 +243,8 @@ static void __init ls_hgl_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE,
-                                  LS_HGL_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
+                             LS_HGL_NOR_BOOT_SIZE);
        platform_device_register(&ls_hgl_nor_flash);
 
        platform_device_register(&ls_hgl_button_device);
index 8e3965c6c0fe15fa96b615d55cc4c6e16aded6c3..18e66e617dc297e02063710ff87366ec465dad3a 100644 (file)
@@ -244,8 +244,8 @@ static void __init lsmini_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE,
-                                  LSMINI_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
+                             LSMINI_NOR_BOOT_SIZE);
        platform_device_register(&lsmini_nor_flash);
 
        platform_device_register(&lsmini_button_device);
index 0ec94a1f2b16e2fe9a9ac34bd7964867c42a8e20..827acbafc9dc2a3b841b869e5e35924d114ac632 100644 (file)
@@ -241,7 +241,8 @@ static void __init mss2_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
+                             MSS2_NOR_BOOT_SIZE);
        platform_device_register(&mss2_nor_flash);
 
        platform_device_register(&mss2_button_device);
index 18143f2a909398eb709066c7bba1a2d32261b575..92600ae2b4b6e4992ff7f27311ecf9186a2b401b 100644 (file)
@@ -204,7 +204,8 @@ static void __init mv2120_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
+                             MV2120_NOR_BOOT_SIZE);
        platform_device_register(&mv2120_nor_flash);
 
        platform_device_register(&mv2120_button_device);
index 282e503b003eb12c6ffd62b62ae4dd35cc09982c..dd0641a0d074447a1c1934128a8a90564b4860da 100644 (file)
@@ -397,8 +397,8 @@ static void __init net2big_init(void)
        net2big_sata_power_init();
        orion5x_sata_init(&net2big_sata_data);
 
-       orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE,
-                                  NET2BIG_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
+                             NET2BIG_NOR_BOOT_SIZE);
        platform_device_register(&net2big_nor_flash);
 
        platform_device_register(&net2big_gpio_buttons);
index 973db98a3c277f4c89fec32a2f0c5250815abbc8..503368023bb18ffdd1ba62f019a90adbe73c9522 100644 (file)
@@ -157,8 +157,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                   "read transaction workaround\n");
-               orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                         ORION5X_PCIE_WA_SIZE);
+               mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                                 ORION5X_PCIE_WA_PHYS_BASE,
+                                                 ORION5X_PCIE_WA_SIZE,
+                                                 MVEBU_MBUS_NO_REMAP,
+                                                 MVEBU_MBUS_PCI_WA);
                pcie_ops.read = pcie_rd_conf_wa;
        }
 
index d6e72f672afbf221a9066100a64b3d96107d9e5f..1c4498bf650a6cbc8d109a18de761f58beb9acd0 100644 (file)
@@ -123,8 +123,8 @@ static void __init rd88f5181l_fxo_init(void)
        orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
 
-       orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
-                                  RD88F5181L_FXO_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
+                             RD88F5181L_FXO_NOR_BOOT_SIZE);
        platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
 }
 
index c8b7913310e53b7f97ced2566fd0d4001512513f..adabe34c4fc62b1ac02e9333b90128add8809c3b 100644 (file)
@@ -130,8 +130,8 @@ static void __init rd88f5181l_ge_init(void)
        orion5x_i2c_init();
        orion5x_uart0_init();
 
-       orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
-                                  RD88F5181L_GE_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
+                             RD88F5181L_GE_NOR_BOOT_SIZE);
        platform_device_register(&rd88f5181l_ge_nor_boot_flash);
 
        i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
index f9e156725d7cf52e742972d90ba58776c57c7708..66e77ec91532ba1e42189af393772c7a2248dc81 100644 (file)
@@ -264,10 +264,11 @@ static void __init rd88f5182_init(void)
        orion5x_uart0_init();
        orion5x_xor_init();
 
-       orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
-                                  RD88F5182_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
+                             RD88F5182_NOR_BOOT_SIZE);
 
-       orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
+       mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
+                             RD88F5182_NOR_SIZE);
        platform_device_register(&rd88f5182_nor_flash);
        platform_device_register(&rd88f5182_gpio_leds);
 
index acc0877ec1c9848be42c2fceaf40a956532bb07c..a0bfa53e75569e292785af06eca421d6073c70af 100644 (file)
@@ -329,8 +329,8 @@ static void __init tsp2_init(void)
        /*
         * Configure peripherals.
         */
-       orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE,
-                                  TSP2_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
+                             TSP2_NOR_BOOT_SIZE);
        platform_device_register(&tsp2_nor_flash);
 
        orion5x_ehci0_init();
index 9c17f0c2b488616404472282be1d955dba515711..80174f0f168e7ce6c9ca91d73175a064bcad8ed6 100644 (file)
@@ -286,8 +286,8 @@ static void __init qnap_ts209_init(void)
        /*
         * Configure peripherals.
         */
-       orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
-                                  QNAP_TS209_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
+                             QNAP_TS209_NOR_BOOT_SIZE);
        platform_device_register(&qnap_ts209_nor_flash);
 
        orion5x_ehci0_init();
index 8cc5ab6c503e31f17f5f4b0bf9b9e8207d90657c..92592790d6da2eb9048fc06523c13b80dcf2c1d5 100644 (file)
@@ -277,8 +277,8 @@ static void __init qnap_ts409_init(void)
        /*
         * Configure peripherals.
         */
-       orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
-                                  QNAP_TS409_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
+                             QNAP_TS409_NOR_BOOT_SIZE);
        platform_device_register(&qnap_ts409_nor_flash);
 
        orion5x_ehci0_init();
index 66552ca7e05da68de13934ddaae342cd75622404..6b84863c018d6c4f83440a26b5c7e4ca85977e4f 100644 (file)
@@ -127,8 +127,8 @@ static void __init wnr854t_init(void)
        orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
 
-       orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
-                                  WNR854T_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
+                             WNR854T_NOR_BOOT_SIZE);
        platform_device_register(&wnr854t_nor_flash);
 }
 
index 2c5408e2e689431fdd40de391db45890f9821caa..fae684bc54f2b51f81dcec16bc7ad31fe210fb0d 100644 (file)
@@ -213,8 +213,8 @@ static void __init wrt350n_v2_init(void)
        orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
 
-       orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
-                                  WRT350N_V2_NOR_BOOT_SIZE);
+       mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
+                             WRT350N_V2_NOR_BOOT_SIZE);
        platform_device_register(&wrt350n_v2_nor_flash);
        platform_device_register(&wrt350n_v2_leds);
        platform_device_register(&wrt350n_v2_button_device);
index 9fd843e1785bdf48d3cbe975b1bc2054ab4be98b..09711cdc6817d625359edfd5110f5db345e1c118 100644 (file)
@@ -3,7 +3,6 @@
 #
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-$(CONFIG_ARCH_ORION5X)        += addr-map.o
 obj-$(CONFIG_ARCH_MV78XX0)        += addr-map.o
 
 orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o