drm/i915: don't wait for vblank while writing InfoFrames
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 28 May 2012 19:42:52 +0000 (16:42 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 30 May 2012 19:52:46 +0000 (21:52 +0200)
This function is called when the pipe is disabled, so it always gets
the 50ms timeout.

This function is called once for each InfoFrame, so we actually get a
100ms timeout. Will be more if we add more InfoFrames.

Also, the spec says we need to "wait for a VSync to ensure completion
of any pending DIP transmissions", not for a VBlank. OTOH, the
register documentation suggests that the DIPs are sent *during* the
VSync, so shouldn't we be waiting until *after* the VSync to ensure
all DIPs are sent?

So this wait_for_vblank seems, besides useless, totally wrong.

If we ever want to change some specific InfoFrame on-the-fly (outside
of the modeset code), the code that changes the InfoFrame will have to
do the waiting itself, and properly.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_hdmi.c

index de6f4c2c82acfc430bee0483dd39915004296ff8..614d83fb6738992a3e3675cf77b8c6fdc7b987a3 100644 (file)
@@ -158,8 +158,6 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
 
        WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
-
        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
        val |= g4x_infoframe_index(frame);
 
@@ -192,8 +190,6 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
 
        WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
-
        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
        val |= g4x_infoframe_index(frame);
 
@@ -229,8 +225,6 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
 
        WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
-
        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
        val |= g4x_infoframe_index(frame);
 
@@ -265,8 +259,6 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
        if (data_reg == 0)
                return;
 
-       intel_wait_for_vblank(dev, intel_crtc->pipe);
-
        val &= ~hsw_infoframe_enable(frame);
        I915_WRITE(ctl_reg, val);