pdata->set_timer_src = omap1_dm_timer_set_src;
pdata->timer_capability = OMAP_TIMER_ALWON |
- OMAP_TIMER_NEEDS_RESET;
+ OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
if (ret) {
.timer_capability = OMAP_TIMER_HAS_PWM,
};
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
/* timer1 */
struct omap_hwmod omap2xxx_timer1_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
};
.timer_capability = OMAP_TIMER_HAS_PWM,
};
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
/* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
+ .dev_attr = &capability_dsp_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.timer_capability = OMAP_TIMER_HAS_PWM,
};
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
/* timer1 */
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer6 */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer7 */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer8 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
+ .dev_attr = &capability_dsp_pwm_dev_attr,
};
/* timer9 */
#define OMAP_TIMER_ALWON 0x40000000
#define OMAP_TIMER_HAS_PWM 0x20000000
#define OMAP_TIMER_NEEDS_RESET 0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
struct omap_timer_capability_dev_attr {
u32 timer_capability;