drm/tegra: hdmi: Name register fields consistently

Name the fields of the SOR_SEQ_CTL register consistently.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 05213b2ec2bd608f8e26cd32b93410f07037b75b..06ab1783bba11e7b1299e3d950accf1547e20285 100644 (file)
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -952,7 +952,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
        }
 
        tegra_hdmi_writel(hdmi,
-                         SOR_SEQ_CTL_PU_PC(0) |
+                         SOR_SEQ_PU_PC(0) |
                          SOR_SEQ_PU_PC_ALT(0) |
                          SOR_SEQ_PD_PC(8) |
                          SOR_SEQ_PD_PC_ALT(8),

diff --git a/drivers/gpu/drm/tegra/hdmi.h b/drivers/gpu/drm/tegra/hdmi.h
index 919a19df4e1b59257b3969887fc288c11e43e1d1..a882514389cd05a35e503c8b0adb2bb39ba91ae4 100644 (file)
--- a/drivers/gpu/drm/tegra/hdmi.h
+++ b/drivers/gpu/drm/tegra/hdmi.h
@@ -201,7 +201,7 @@
 #define HDMI_NV_PDISP_SOR_CRCB                                 0x5d
 #define HDMI_NV_PDISP_SOR_BLANK                                        0x5e
 #define HDMI_NV_PDISP_SOR_SEQ_CTL                              0x5f
-#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) <<  0)
+#define SOR_SEQ_PU_PC(x)     (((x) & 0xf) <<  0)
 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) <<  4)
 #define SOR_SEQ_PD_PC(x)     (((x) & 0xf) <<  8)
 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)