ide_hwif_t *hwif = drive->hwif;
struct pci_dev *dev = to_pci_dev(hwif->dev);
struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
+ unsigned long setup_count;
unsigned int cycle_time;
- u8 setup_count, arttim = 0;
+ u8 arttim = 0;
static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
if (hwif->channel) {
ide_drive_t *pair = ide_get_pair_dev(drive);
- drive->drive_data = setup_count;
+ ide_set_drivedata(drive, (void *)setup_count);
if (pair)
- setup_count = max_t(u8, setup_count, pair->drive_data);
+ setup_count = max_t(u8, setup_count,
+ (unsigned long)ide_get_drivedata(pair));
}
if (setup_count > 5) /* shouldn't actually happen... */
struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
ide_drive_t *pair = ide_get_pair_dev(drive);
int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
u32 cast;
u8 cmd_pio = pio;
if (pair)
cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4));
- drive->drive_data &= (IDE_DRV_MASK << 8);
- drive->drive_data |= drv_timings[pio];
+ timings &= (IDE_DRV_MASK << 8);
+ timings |= drv_timings[pio];
+ ide_set_drivedata(drive, (void *)timings);
cs5536_program_dtc(drive, drv_timings[pio]);
struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
u32 etc;
cs5536_read(pdev, ETC, &etc);
etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
} else { /* MWDMA */
etc &= ~(IDE_ETC_UDMA_MASK << dshift);
- drive->drive_data &= IDE_DRV_MASK;
- drive->drive_data |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
+ timings &= IDE_DRV_MASK;
+ timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
+ ide_set_drivedata(drive, (void *)timings);
}
cs5536_write(pdev, ETC, etc);
static void cs5536_dma_start(ide_drive_t *drive)
{
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
+
if (drive->current_speed < XFER_UDMA_0 &&
- (drive->drive_data >> 8) != (drive->drive_data & IDE_DRV_MASK))
- cs5536_program_dtc(drive, drive->drive_data >> 8);
+ (timings >> 8) != (timings & IDE_DRV_MASK))
+ cs5536_program_dtc(drive, timings >> 8);
ide_dma_start(drive);
}
static int cs5536_dma_end(ide_drive_t *drive)
{
int ret = ide_dma_end(drive);
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
if (drive->current_speed < XFER_UDMA_0 &&
- (drive->drive_data >> 8) != (drive->drive_data & IDE_DRV_MASK))
- cs5536_program_dtc(drive, drive->drive_data & IDE_DRV_MASK);
+ (timings >> 8) != (timings & IDE_DRV_MASK))
+ cs5536_program_dtc(drive, timings & IDE_DRV_MASK);
return ret;
}
* bit3 (0x08): "1" 3 cycle time, "0" 2 cycle time (?)
*/
#define HT_CONFIG_PORT 0x3e6
-#define HT_CONFIG(drivea) (u8)(((drivea)->drive_data & 0xff00) >> 8)
+
+static inline u8 HT_CONFIG(ide_drive_t *drive)
+{
+ return ((unsigned long)ide_get_drivedata(drive) & 0xff00) >> 8;
+}
+
/*
* FIFO + PREFETCH (both a/b-model)
*/
* Active Time for each drive. Smaller value gives higher speed.
* In case of failures you should probably fall back to a higher value.
*/
-#define HT_TIMING(drivea) (u8)((drivea)->drive_data & 0x00ff)
+static inline u8 HT_TIMING(ide_drive_t *drive)
+{
+ return (unsigned long)ide_get_drivedata(drive) & 0x00ff;
+}
+
#define HT_TIMING_DEFAULT 0xff
/*
*/
static void ht_set_prefetch(ide_drive_t *drive, u8 state)
{
- unsigned long flags;
+ unsigned long flags, config;
int t = HT_PREFETCH_MODE << 8;
spin_lock_irqsave(&ht6560b_lock, flags);
+ config = (unsigned long)ide_get_drivedata(drive);
+
/*
* Prefetch mode and unmask irq seems to conflict
*/
if (state) {
- drive->drive_data |= t; /* enable prefetch mode */
+ config |= t; /* enable prefetch mode */
drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
drive->dev_flags &= ~IDE_DFLAG_UNMASK;
} else {
- drive->drive_data &= ~t; /* disable prefetch mode */
+ config &= ~t; /* disable prefetch mode */
drive->dev_flags &= ~IDE_DFLAG_NO_UNMASK;
}
+ ide_set_drivedata(drive, (void *)config);
+
spin_unlock_irqrestore(&ht6560b_lock, flags);
#ifdef DEBUG
static void ht6560b_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
- unsigned long flags;
+ unsigned long flags, config;
u8 timing;
switch (pio) {
timing = ht_pio2timings(drive, pio);
spin_lock_irqsave(&ht6560b_lock, flags);
- drive->drive_data &= 0xff00;
- drive->drive_data |= timing;
+ config = (unsigned long)ide_get_drivedata(drive);
+ config &= 0xff00;
+ config |= timing;
+ ide_set_drivedata(drive, (void *)config);
spin_unlock_irqrestore(&ht6560b_lock, flags);
#ifdef DEBUG
if (hwif->channel)
t |= (HT_SECONDARY_IF << 8);
- drive->drive_data = t;
+ ide_set_drivedata(drive, (void *)t);
}
static int probe_ht6560b;
*/
static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
{
- int cycle_time, use_dma_info = 0;
+ unsigned long cycle_time;
+ int use_dma_info = 0;
switch (xfer_mode) {
case XFER_MW_DMA_2:
if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
- drive->drive_data = cycle_time;
+ ide_set_drivedata(drive, (void *)cycle_time);
printk("%s: %s selected (peak %dMB/s)\n", drive->name,
- ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
+ ide_xfer_verbose(xfer_mode),
+ 2000 / (unsigned long)ide_get_drivedata(drive));
}
static const struct ide_port_ops icside_v6_port_ops = {
/*
* Select the correct timing for this drive.
*/
- set_dma_speed(ec->dma, drive->drive_data);
+ set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));
/*
* Tell the DMA engine about the SG table and
ide_hwif_t *hwif = drive->hwif;
ide_drive_t *pair = ide_get_pair_dev(drive);
unsigned long flags;
+ unsigned long mode = XFER_PIO_0 + pio, pair_mode;
u8 tim, misc, addr_pio = pio, clk;
/* DRDY is default 2 (by OPTi Databook) */
{ 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
};
- drive->drive_data = XFER_PIO_0 + pio;
+ ide_set_drivedata(drive, (void *)mode);
if (pair) {
- if (pair->drive_data && pair->drive_data < drive->drive_data)
- addr_pio = pair->drive_data - XFER_PIO_0;
+ pair_mode = (unsigned long)ide_get_drivedata(pair);
+ if (pair_mode && pair_mode < mode)
+ addr_pio = pair_mode - XFER_PIO_0;
}
spin_lock_irqsave(&opti621_lock, flags);
static void qd_set_timing (ide_drive_t *drive, u8 timing)
{
- drive->drive_data &= 0xff00;
- drive->drive_data |= timing;
+ unsigned long data = (unsigned long)ide_get_drivedata(drive);
+
+ data &= 0xff00;
+ data |= timing;
+ ide_set_drivedata(drive, (void *)data);
printk(KERN_DEBUG "%s: %#x\n", drive->name, timing);
}
u8 base = (hwif->config_data & 0xff00) >> 8;
u8 config = QD_CONFIG(hwif);
- drive->drive_data = QD6500_DEF_DATA;
+ ide_set_drivedata(drive, (void *)QD6500_DEF_DATA);
}
static void __init qd6580_init_dev(ide_drive_t *drive)
} else
t2 = t1 = hwif->channel ? QD6580_DEF_DATA2 : QD6580_DEF_DATA;
- drive->drive_data = (drive->dn & 1) ? t2 : t1;
+ ide_set_drivedata(drive, (void *)((drive->dn & 1) ? t2 : t1));
}
static const struct ide_tp_ops qd65xx_tp_ops = {
#define QD_CONFIG(hwif) ((hwif)->config_data & 0x00ff)
-#define QD_TIMING(drive) (u8)(((drive)->drive_data) & 0x00ff)
-#define QD_TIMREG(drive) (u8)((((drive)->drive_data) & 0xff00) >> 8)
+static inline u8 QD_TIMING(ide_drive_t *drive)
+{
+ return (unsigned long)ide_get_drivedata(drive) & 0x00ff;
+}
+
+static inline u8 QD_TIMREG(ide_drive_t *drive)
+{
+ return ((unsigned long)ide_get_drivedata(drive) & 0xff00) >> 8;
+}
#define QD6500_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0c : 0x08))
#define QD6580_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0a : 0x00))
static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
int reg = 0x44 + drive->dn * 4;
u16 drv_ctrl;
* Store the PIO timings so that we can restore them
* in case DMA will be turned off...
*/
- drive->drive_data &= 0xffff0000;
- drive->drive_data |= drv_ctrl;
+ timings &= 0xffff0000;
+ timings |= drv_ctrl;
+ ide_set_drivedata(drive, (void *)timings);
pci_write_config_word(dev, reg, drv_ctrl);
pci_read_config_word (dev, reg, &drv_ctrl);
static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
+ unsigned long timings = (unsigned long)ide_get_drivedata(drive);
u16 drv_ctrl;
DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
* Store the DMA timings so that we can actually program
* them when DMA will be turned on...
*/
- drive->drive_data &= 0x0000ffff;
- drive->drive_data |= (unsigned long)drv_ctrl << 16;
+ timings &= 0x0000ffff;
+ timings |= (unsigned long)drv_ctrl << 16;
+ ide_set_drivedata(drive, (void *)timings);
}
static int sl82c105_test_irq(ide_hwif_t *hwif)
DBG(("%s(drive:%s)\n", __func__, drive->name));
- pci_write_config_word(dev, reg, drive->drive_data >> 16);
+ pci_write_config_word(dev, reg,
+ (unsigned long)ide_get_drivedata(drive) >> 16);
sl82c105_reset_host(dev);
ide_dma_start(drive);
ret = ide_dma_end(drive);
- pci_write_config_word(dev, reg, drive->drive_data);
+ pci_write_config_word(dev, reg,
+ (unsigned long)ide_get_drivedata(drive));
return ret;
}
unsigned int bios_cyl; /* BIOS/fdisk/LILO number of cyls */
unsigned int cyl; /* "real" number of cyls */
- unsigned int drive_data; /* used by set_pio_mode/dev_select() */
+ void *drive_data; /* used by set_pio_mode/dev_select() */
unsigned int failures; /* current failure count */
unsigned int max_failures; /* maximum allowed failure count */
u64 probed_capacity;/* initial/native media capacity */
return (peer->dev_flags & IDE_DFLAG_PRESENT) ? peer : NULL;
}
+static inline void *ide_get_drivedata(ide_drive_t *drive)
+{
+ return drive->drive_data;
+}
+
+static inline void ide_set_drivedata(ide_drive_t *drive, void *data)
+{
+ drive->drive_data = data;
+}
+
#define ide_port_for_each_dev(i, dev, port) \
for ((i) = 0; ((dev) = (port)->devices[i]) || (i) < MAX_DRIVES; (i)++)