vpp: set the sr position reg correctly [1/1]

PD#SWPL-14963

Problem:
The position bits of super scaler is incorrect.

Solution:
Set the position bits correctly

Verify:
Verified on U212

Change-Id: I133662859456f65e130b8795f574da845039c717
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>

diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c
index b58be3f29626bbe7caf0a914ccaec20168ac81ee..50555466858e41e1e192fd467239bb0d358ada48 100644 (file)
--- a/drivers/amlogic/media/video_sink/video.c
+++ b/drivers/amlogic/media/video_sink/video.c
@@ -8625,9 +8625,9 @@ SET_FILTER:
                        if (cur_frame_par->sr0_position)
                                vpp_misc_set |=
                                        PREBLD_SR0_VD1_SCALER;
-                       else
+                       else /* SR0_AFTER_DNLP */
                                vpp_misc_set &=
-                                       ~SR0_AFTER_DNLP;
+                                       ~PREBLD_SR0_VD1_SCALER;
                else
                        vpp_misc_set |=
                                PREBLD_SR0_VD1_SCALER;
@@ -8638,9 +8638,9 @@ SET_FILTER:
                        if (cur_frame_par->sr1_position)
                                vpp_misc_set |=
                                        DNLP_SR1_CM;
-                       else
+                       else /* SR1_AFTER_POSTBLEN */
                                vpp_misc_set &=
-                                       ~SR1_AFTER_POSTBLEN;
+                                       ~DNLP_SR1_CM;
                else
                        vpp_misc_set |=
                                DNLP_SR1_CM;
@@ -13780,9 +13780,8 @@ static int __init video_early_init(void)
        } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
                WRITE_VCBUS_REG_BITS(
                        SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
-               /* TODO: check if the bit8 is available */
-               /* WRITE_VCBUS_REG_BITS( */
-               /*      SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1); */
+               WRITE_VCBUS_REG_BITS(
+                       SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
        }
        return 0;
 }

diff --git a/drivers/amlogic/media/video_sink/vpp.c b/drivers/amlogic/media/video_sink/vpp.c
index 0d8dc161fb862d460223cc9d89a0594b89450a33..2338cdb15b04ccdf4ed25e6a7c86b12ea9ead576 100644 (file)
--- a/drivers/amlogic/media/video_sink/vpp.c
+++ b/drivers/amlogic/media/video_sink/vpp.c
@@ -2039,6 +2039,16 @@ static void vpp_set_super_scaler(
                        next_frame_par->supsc1_vert_ratio ? 1 : 0;
                next_frame_par->supsc1_hori_ratio = 0;
        }
+
+       /*double check core0 input width for core0_vert_ratio!!!*/
+       if (next_frame_par->supsc0_vert_ratio &&
+           (width_out >> next_frame_par->supsc0_hori_ratio >
+            sr->core0_v_enable_width_max)) {
+               next_frame_par->supsc0_vert_ratio = 0;
+               if (next_frame_par->supsc0_hori_ratio == 0)
+                       next_frame_par->supsc0_enable = 0;
+       }
+
        /*double check core1 input width for core1_vert_ratio!!!*/
        if (next_frame_par->supsc1_vert_ratio &&
                (width_out >> next_frame_par->supsc1_hori_ratio >
@@ -2047,6 +2057,7 @@ static void vpp_set_super_scaler(
                if (next_frame_par->supsc1_hori_ratio == 0)
                        next_frame_par->supsc1_enable = 0;
        }
+
        /* option add patch */
        if ((ver_sc_multiple_num <= super_scaler_v_ratio) &&
                (src_height >= sr->core0_v_enable_width_max) &&